1*20a107bcSKathiravan Thirumoorthy /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*20a107bcSKathiravan Thirumoorthy /* 3*20a107bcSKathiravan Thirumoorthy * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4*20a107bcSKathiravan Thirumoorthy */ 5*20a107bcSKathiravan Thirumoorthy 6*20a107bcSKathiravan Thirumoorthy #ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5210_H 7*20a107bcSKathiravan Thirumoorthy #define _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5210_H 8*20a107bcSKathiravan Thirumoorthy 9*20a107bcSKathiravan Thirumoorthy #define GCC_ADSS_PWM_CLK 0 10*20a107bcSKathiravan Thirumoorthy #define GCC_ADSS_PWM_CLK_SRC 1 11*20a107bcSKathiravan Thirumoorthy #define GCC_CMN_12GPLL_AHB_CLK 2 12*20a107bcSKathiravan Thirumoorthy #define GCC_CMN_12GPLL_SYS_CLK 3 13*20a107bcSKathiravan Thirumoorthy #define GCC_CNOC_LPASS_CFG_CLK 4 14*20a107bcSKathiravan Thirumoorthy #define GCC_CNOC_PCIE0_1LANE_S_CLK 5 15*20a107bcSKathiravan Thirumoorthy #define GCC_CNOC_PCIE1_2LANE_S_CLK 6 16*20a107bcSKathiravan Thirumoorthy #define GCC_CNOC_USB_CLK 7 17*20a107bcSKathiravan Thirumoorthy #define GCC_GEPHY_SYS_CLK 8 18*20a107bcSKathiravan Thirumoorthy #define GCC_LPASS_AXIM_CLK_SRC 9 19*20a107bcSKathiravan Thirumoorthy #define GCC_LPASS_CORE_AXIM_CLK 10 20*20a107bcSKathiravan Thirumoorthy #define GCC_LPASS_SWAY_CLK 11 21*20a107bcSKathiravan Thirumoorthy #define GCC_LPASS_SWAY_CLK_SRC 12 22*20a107bcSKathiravan Thirumoorthy #define GCC_MDIO_AHB_CLK 13 23*20a107bcSKathiravan Thirumoorthy #define GCC_MDIO_GEPHY_AHB_CLK 14 24*20a107bcSKathiravan Thirumoorthy #define GCC_NSS_TS_CLK 15 25*20a107bcSKathiravan Thirumoorthy #define GCC_NSS_TS_CLK_SRC 16 26*20a107bcSKathiravan Thirumoorthy #define GCC_NSSCC_CLK 17 27*20a107bcSKathiravan Thirumoorthy #define GCC_NSSCFG_CLK 18 28*20a107bcSKathiravan Thirumoorthy #define GCC_NSSNOC_ATB_CLK 19 29*20a107bcSKathiravan Thirumoorthy #define GCC_NSSNOC_MEMNOC_1_CLK 20 30*20a107bcSKathiravan Thirumoorthy #define GCC_NSSNOC_MEMNOC_BFDCD_CLK_SRC 21 31*20a107bcSKathiravan Thirumoorthy #define GCC_NSSNOC_MEMNOC_CLK 22 32*20a107bcSKathiravan Thirumoorthy #define GCC_NSSNOC_MEMNOC_DIV_CLK_SRC 23 33*20a107bcSKathiravan Thirumoorthy #define GCC_NSSNOC_NSSCC_CLK 24 34*20a107bcSKathiravan Thirumoorthy #define GCC_NSSNOC_PCNOC_1_CLK 25 35*20a107bcSKathiravan Thirumoorthy #define GCC_NSSNOC_QOSGEN_REF_CLK 26 36*20a107bcSKathiravan Thirumoorthy #define GCC_NSSNOC_SNOC_1_CLK 27 37*20a107bcSKathiravan Thirumoorthy #define GCC_NSSNOC_SNOC_CLK 28 38*20a107bcSKathiravan Thirumoorthy #define GCC_NSSNOC_TIMEOUT_REF_CLK 29 39*20a107bcSKathiravan Thirumoorthy #define GCC_NSSNOC_XO_DCD_CLK 30 40*20a107bcSKathiravan Thirumoorthy #define GCC_PCIE0_AHB_CLK 31 41*20a107bcSKathiravan Thirumoorthy #define GCC_PCIE0_AUX_CLK 32 42*20a107bcSKathiravan Thirumoorthy #define GCC_PCIE0_AXI_M_CLK 33 43*20a107bcSKathiravan Thirumoorthy #define GCC_PCIE0_AXI_M_CLK_SRC 34 44*20a107bcSKathiravan Thirumoorthy #define GCC_PCIE0_AXI_S_BRIDGE_CLK 35 45*20a107bcSKathiravan Thirumoorthy #define GCC_PCIE0_AXI_S_CLK 36 46*20a107bcSKathiravan Thirumoorthy #define GCC_PCIE0_AXI_S_CLK_SRC 37 47*20a107bcSKathiravan Thirumoorthy #define GCC_PCIE0_PIPE_CLK 38 48*20a107bcSKathiravan Thirumoorthy #define GCC_PCIE0_PIPE_CLK_SRC 39 49*20a107bcSKathiravan Thirumoorthy #define GCC_PCIE0_RCHNG_CLK 40 50*20a107bcSKathiravan Thirumoorthy #define GCC_PCIE0_RCHNG_CLK_SRC 41 51*20a107bcSKathiravan Thirumoorthy #define GCC_PCIE1_AHB_CLK 42 52*20a107bcSKathiravan Thirumoorthy #define GCC_PCIE1_AUX_CLK 43 53*20a107bcSKathiravan Thirumoorthy #define GCC_PCIE1_AXI_M_CLK 44 54*20a107bcSKathiravan Thirumoorthy #define GCC_PCIE1_AXI_M_CLK_SRC 45 55*20a107bcSKathiravan Thirumoorthy #define GCC_PCIE1_AXI_S_BRIDGE_CLK 46 56*20a107bcSKathiravan Thirumoorthy #define GCC_PCIE1_AXI_S_CLK 47 57*20a107bcSKathiravan Thirumoorthy #define GCC_PCIE1_AXI_S_CLK_SRC 48 58*20a107bcSKathiravan Thirumoorthy #define GCC_PCIE1_PIPE_CLK 49 59*20a107bcSKathiravan Thirumoorthy #define GCC_PCIE1_PIPE_CLK_SRC 50 60*20a107bcSKathiravan Thirumoorthy #define GCC_PCIE1_RCHNG_CLK 51 61*20a107bcSKathiravan Thirumoorthy #define GCC_PCIE1_RCHNG_CLK_SRC 52 62*20a107bcSKathiravan Thirumoorthy #define GCC_PCIE_AUX_CLK_SRC 53 63*20a107bcSKathiravan Thirumoorthy #define GCC_PCNOC_BFDCD_CLK_SRC 54 64*20a107bcSKathiravan Thirumoorthy #define GCC_PON_APB_CLK 55 65*20a107bcSKathiravan Thirumoorthy #define GCC_PON_TM_CLK 56 66*20a107bcSKathiravan Thirumoorthy #define GCC_PON_TM2X_CLK 57 67*20a107bcSKathiravan Thirumoorthy #define GCC_PON_TM2X_CLK_SRC 58 68*20a107bcSKathiravan Thirumoorthy #define GCC_QDSS_AT_CLK 59 69*20a107bcSKathiravan Thirumoorthy #define GCC_QDSS_AT_CLK_SRC 60 70*20a107bcSKathiravan Thirumoorthy #define GCC_QDSS_DAP_CLK 61 71*20a107bcSKathiravan Thirumoorthy #define GCC_QDSS_TSCTR_CLK_SRC 62 72*20a107bcSKathiravan Thirumoorthy #define GCC_QPIC_AHB_CLK 63 73*20a107bcSKathiravan Thirumoorthy #define GCC_QPIC_CLK 64 74*20a107bcSKathiravan Thirumoorthy #define GCC_QPIC_CLK_SRC 65 75*20a107bcSKathiravan Thirumoorthy #define GCC_QPIC_IO_MACRO_CLK 66 76*20a107bcSKathiravan Thirumoorthy #define GCC_QPIC_IO_MACRO_CLK_SRC 67 77*20a107bcSKathiravan Thirumoorthy #define GCC_QRNG_AHB_CLK 68 78*20a107bcSKathiravan Thirumoorthy #define GCC_QUPV3_AHB_MST_CLK 69 79*20a107bcSKathiravan Thirumoorthy #define GCC_QUPV3_AHB_SLV_CLK 70 80*20a107bcSKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE0_CLK 71 81*20a107bcSKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE0_CLK_SRC 72 82*20a107bcSKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE1_CLK 73 83*20a107bcSKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE1_CLK_SRC 74 84*20a107bcSKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE2_CLK 75 85*20a107bcSKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE2_CLK_SRC 76 86*20a107bcSKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE3_CLK 77 87*20a107bcSKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE3_CLK_SRC 78 88*20a107bcSKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE4_CLK 79 89*20a107bcSKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE4_CLK_SRC 80 90*20a107bcSKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE5_CLK 81 91*20a107bcSKathiravan Thirumoorthy #define GCC_QUPV3_WRAP_SE5_CLK_SRC 82 92*20a107bcSKathiravan Thirumoorthy #define GCC_SDCC1_AHB_CLK 83 93*20a107bcSKathiravan Thirumoorthy #define GCC_SDCC1_APPS_CLK 84 94*20a107bcSKathiravan Thirumoorthy #define GCC_SDCC1_APPS_CLK_SRC 85 95*20a107bcSKathiravan Thirumoorthy #define GCC_SDCC1_ICE_CORE_CLK 86 96*20a107bcSKathiravan Thirumoorthy #define GCC_SDCC1_ICE_CORE_CLK_SRC 87 97*20a107bcSKathiravan Thirumoorthy #define GCC_SLEEP_CLK_SRC 88 98*20a107bcSKathiravan Thirumoorthy #define GCC_SNOC_LPASS_CLK 89 99*20a107bcSKathiravan Thirumoorthy #define GCC_SNOC_PCIE0_AXI_M_CLK 90 100*20a107bcSKathiravan Thirumoorthy #define GCC_SNOC_PCIE1_AXI_M_CLK 91 101*20a107bcSKathiravan Thirumoorthy #define GCC_SYSTEM_NOC_BFDCD_CLK_SRC 92 102*20a107bcSKathiravan Thirumoorthy #define GCC_UNIPHY0_AHB_CLK 93 103*20a107bcSKathiravan Thirumoorthy #define GCC_UNIPHY0_SYS_CLK 94 104*20a107bcSKathiravan Thirumoorthy #define GCC_UNIPHY1_AHB_CLK 95 105*20a107bcSKathiravan Thirumoorthy #define GCC_UNIPHY1_SYS_CLK 96 106*20a107bcSKathiravan Thirumoorthy #define GCC_UNIPHY2_AHB_CLK 97 107*20a107bcSKathiravan Thirumoorthy #define GCC_UNIPHY2_SYS_CLK 98 108*20a107bcSKathiravan Thirumoorthy #define GCC_UNIPHY_SYS_CLK_SRC 99 109*20a107bcSKathiravan Thirumoorthy #define GCC_USB0_AUX_CLK 100 110*20a107bcSKathiravan Thirumoorthy #define GCC_USB0_AUX_CLK_SRC 101 111*20a107bcSKathiravan Thirumoorthy #define GCC_USB0_MASTER_CLK 102 112*20a107bcSKathiravan Thirumoorthy #define GCC_USB0_MASTER_CLK_SRC 103 113*20a107bcSKathiravan Thirumoorthy #define GCC_USB0_MOCK_UTMI_CLK 104 114*20a107bcSKathiravan Thirumoorthy #define GCC_USB0_MOCK_UTMI_CLK_SRC 105 115*20a107bcSKathiravan Thirumoorthy #define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC 106 116*20a107bcSKathiravan Thirumoorthy #define GCC_USB0_PHY_CFG_AHB_CLK 107 117*20a107bcSKathiravan Thirumoorthy #define GCC_USB0_PIPE_CLK 108 118*20a107bcSKathiravan Thirumoorthy #define GCC_USB0_PIPE_CLK_SRC 109 119*20a107bcSKathiravan Thirumoorthy #define GCC_USB0_SLEEP_CLK 110 120*20a107bcSKathiravan Thirumoorthy #define GCC_XO_CLK_SRC 111 121*20a107bcSKathiravan Thirumoorthy #define GPLL0_MAIN 112 122*20a107bcSKathiravan Thirumoorthy #define GPLL0 113 123*20a107bcSKathiravan Thirumoorthy #define GPLL2_MAIN 114 124*20a107bcSKathiravan Thirumoorthy #define GPLL2 115 125*20a107bcSKathiravan Thirumoorthy #define GPLL4_MAIN 116 126*20a107bcSKathiravan Thirumoorthy #endif 127