19c92ab61SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 202824653SGeorgi Djakov /* 302824653SGeorgi Djakov * Copyright (c) 2014, The Linux Foundation. All rights reserved. 402824653SGeorgi Djakov */ 502824653SGeorgi Djakov 602824653SGeorgi Djakov #ifndef _DT_BINDINGS_CLK_APQ_GCC_8084_H 702824653SGeorgi Djakov #define _DT_BINDINGS_CLK_APQ_GCC_8084_H 802824653SGeorgi Djakov 902824653SGeorgi Djakov #define GPLL0 0 1002824653SGeorgi Djakov #define GPLL0_VOTE 1 1102824653SGeorgi Djakov #define GPLL1 2 1202824653SGeorgi Djakov #define GPLL1_VOTE 3 1302824653SGeorgi Djakov #define GPLL2 4 1402824653SGeorgi Djakov #define GPLL2_VOTE 5 1502824653SGeorgi Djakov #define GPLL3 6 1602824653SGeorgi Djakov #define GPLL3_VOTE 7 1702824653SGeorgi Djakov #define GPLL4 8 1802824653SGeorgi Djakov #define GPLL4_VOTE 9 1902824653SGeorgi Djakov #define CONFIG_NOC_CLK_SRC 10 2002824653SGeorgi Djakov #define PERIPH_NOC_CLK_SRC 11 2102824653SGeorgi Djakov #define SYSTEM_NOC_CLK_SRC 12 2202824653SGeorgi Djakov #define BLSP_UART_SIM_CLK_SRC 13 2302824653SGeorgi Djakov #define QDSS_TSCTR_CLK_SRC 14 2402824653SGeorgi Djakov #define UFS_AXI_CLK_SRC 15 2502824653SGeorgi Djakov #define RPM_CLK_SRC 16 2602824653SGeorgi Djakov #define KPSS_AHB_CLK_SRC 17 2702824653SGeorgi Djakov #define QDSS_AT_CLK_SRC 18 2802824653SGeorgi Djakov #define BIMC_DDR_CLK_SRC 19 2902824653SGeorgi Djakov #define USB30_MASTER_CLK_SRC 20 3002824653SGeorgi Djakov #define USB30_SEC_MASTER_CLK_SRC 21 3102824653SGeorgi Djakov #define USB_HSIC_AHB_CLK_SRC 22 3202824653SGeorgi Djakov #define MMSS_BIMC_GFX_CLK_SRC 23 3302824653SGeorgi Djakov #define QDSS_STM_CLK_SRC 24 3402824653SGeorgi Djakov #define ACC_CLK_SRC 25 3502824653SGeorgi Djakov #define SEC_CTRL_CLK_SRC 26 3602824653SGeorgi Djakov #define BLSP1_QUP1_I2C_APPS_CLK_SRC 27 3702824653SGeorgi Djakov #define BLSP1_QUP1_SPI_APPS_CLK_SRC 28 3802824653SGeorgi Djakov #define BLSP1_QUP2_I2C_APPS_CLK_SRC 29 3902824653SGeorgi Djakov #define BLSP1_QUP2_SPI_APPS_CLK_SRC 30 4002824653SGeorgi Djakov #define BLSP1_QUP3_I2C_APPS_CLK_SRC 31 4102824653SGeorgi Djakov #define BLSP1_QUP3_SPI_APPS_CLK_SRC 32 4202824653SGeorgi Djakov #define BLSP1_QUP4_I2C_APPS_CLK_SRC 33 4302824653SGeorgi Djakov #define BLSP1_QUP4_SPI_APPS_CLK_SRC 34 4402824653SGeorgi Djakov #define BLSP1_QUP5_I2C_APPS_CLK_SRC 35 4502824653SGeorgi Djakov #define BLSP1_QUP5_SPI_APPS_CLK_SRC 36 4602824653SGeorgi Djakov #define BLSP1_QUP6_I2C_APPS_CLK_SRC 37 4702824653SGeorgi Djakov #define BLSP1_QUP6_SPI_APPS_CLK_SRC 38 4802824653SGeorgi Djakov #define BLSP1_UART1_APPS_CLK_SRC 39 4902824653SGeorgi Djakov #define BLSP1_UART2_APPS_CLK_SRC 40 5002824653SGeorgi Djakov #define BLSP1_UART3_APPS_CLK_SRC 41 5102824653SGeorgi Djakov #define BLSP1_UART4_APPS_CLK_SRC 42 5202824653SGeorgi Djakov #define BLSP1_UART5_APPS_CLK_SRC 43 5302824653SGeorgi Djakov #define BLSP1_UART6_APPS_CLK_SRC 44 5402824653SGeorgi Djakov #define BLSP2_QUP1_I2C_APPS_CLK_SRC 45 5502824653SGeorgi Djakov #define BLSP2_QUP1_SPI_APPS_CLK_SRC 46 5602824653SGeorgi Djakov #define BLSP2_QUP2_I2C_APPS_CLK_SRC 47 5702824653SGeorgi Djakov #define BLSP2_QUP2_SPI_APPS_CLK_SRC 48 5802824653SGeorgi Djakov #define BLSP2_QUP3_I2C_APPS_CLK_SRC 49 5902824653SGeorgi Djakov #define BLSP2_QUP3_SPI_APPS_CLK_SRC 50 6002824653SGeorgi Djakov #define BLSP2_QUP4_I2C_APPS_CLK_SRC 51 6102824653SGeorgi Djakov #define BLSP2_QUP4_SPI_APPS_CLK_SRC 52 6202824653SGeorgi Djakov #define BLSP2_QUP5_I2C_APPS_CLK_SRC 53 6302824653SGeorgi Djakov #define BLSP2_QUP5_SPI_APPS_CLK_SRC 54 6402824653SGeorgi Djakov #define BLSP2_QUP6_I2C_APPS_CLK_SRC 55 6502824653SGeorgi Djakov #define BLSP2_QUP6_SPI_APPS_CLK_SRC 56 6602824653SGeorgi Djakov #define BLSP2_UART1_APPS_CLK_SRC 57 6702824653SGeorgi Djakov #define BLSP2_UART2_APPS_CLK_SRC 58 6802824653SGeorgi Djakov #define BLSP2_UART3_APPS_CLK_SRC 59 6902824653SGeorgi Djakov #define BLSP2_UART4_APPS_CLK_SRC 60 7002824653SGeorgi Djakov #define BLSP2_UART5_APPS_CLK_SRC 61 7102824653SGeorgi Djakov #define BLSP2_UART6_APPS_CLK_SRC 62 7202824653SGeorgi Djakov #define CE1_CLK_SRC 63 7302824653SGeorgi Djakov #define CE2_CLK_SRC 64 7402824653SGeorgi Djakov #define CE3_CLK_SRC 65 7502824653SGeorgi Djakov #define GP1_CLK_SRC 66 7602824653SGeorgi Djakov #define GP2_CLK_SRC 67 7702824653SGeorgi Djakov #define GP3_CLK_SRC 68 7802824653SGeorgi Djakov #define PDM2_CLK_SRC 69 7902824653SGeorgi Djakov #define QDSS_TRACECLKIN_CLK_SRC 70 8002824653SGeorgi Djakov #define RBCPR_CLK_SRC 71 8102824653SGeorgi Djakov #define SATA_ASIC0_CLK_SRC 72 8202824653SGeorgi Djakov #define SATA_PMALIVE_CLK_SRC 73 8302824653SGeorgi Djakov #define SATA_RX_CLK_SRC 74 8402824653SGeorgi Djakov #define SATA_RX_OOB_CLK_SRC 75 8502824653SGeorgi Djakov #define SDCC1_APPS_CLK_SRC 76 8602824653SGeorgi Djakov #define SDCC2_APPS_CLK_SRC 77 8702824653SGeorgi Djakov #define SDCC3_APPS_CLK_SRC 78 8802824653SGeorgi Djakov #define SDCC4_APPS_CLK_SRC 79 8902824653SGeorgi Djakov #define GCC_SNOC_BUS_TIMEOUT0_AHB_CLK 80 9002824653SGeorgi Djakov #define SPMI_AHB_CLK_SRC 81 9102824653SGeorgi Djakov #define SPMI_SER_CLK_SRC 82 9202824653SGeorgi Djakov #define TSIF_REF_CLK_SRC 83 9302824653SGeorgi Djakov #define USB30_MOCK_UTMI_CLK_SRC 84 9402824653SGeorgi Djakov #define USB30_SEC_MOCK_UTMI_CLK_SRC 85 9502824653SGeorgi Djakov #define USB_HS_SYSTEM_CLK_SRC 86 9602824653SGeorgi Djakov #define USB_HSIC_CLK_SRC 87 9702824653SGeorgi Djakov #define USB_HSIC_IO_CAL_CLK_SRC 88 9802824653SGeorgi Djakov #define USB_HSIC_MOCK_UTMI_CLK_SRC 89 9902824653SGeorgi Djakov #define USB_HSIC_SYSTEM_CLK_SRC 90 10002824653SGeorgi Djakov #define GCC_BAM_DMA_AHB_CLK 91 10102824653SGeorgi Djakov #define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK 92 10202824653SGeorgi Djakov #define DDR_CLK_SRC 93 10302824653SGeorgi Djakov #define GCC_BIMC_CFG_AHB_CLK 94 10402824653SGeorgi Djakov #define GCC_BIMC_CLK 95 10502824653SGeorgi Djakov #define GCC_BIMC_KPSS_AXI_CLK 96 10602824653SGeorgi Djakov #define GCC_BIMC_SLEEP_CLK 97 10702824653SGeorgi Djakov #define GCC_BIMC_SYSNOC_AXI_CLK 98 10802824653SGeorgi Djakov #define GCC_BIMC_XO_CLK 99 10902824653SGeorgi Djakov #define GCC_BLSP1_AHB_CLK 100 11002824653SGeorgi Djakov #define GCC_BLSP1_SLEEP_CLK 101 11102824653SGeorgi Djakov #define GCC_BLSP1_QUP1_I2C_APPS_CLK 102 11202824653SGeorgi Djakov #define GCC_BLSP1_QUP1_SPI_APPS_CLK 103 11302824653SGeorgi Djakov #define GCC_BLSP1_QUP2_I2C_APPS_CLK 104 11402824653SGeorgi Djakov #define GCC_BLSP1_QUP2_SPI_APPS_CLK 105 11502824653SGeorgi Djakov #define GCC_BLSP1_QUP3_I2C_APPS_CLK 106 11602824653SGeorgi Djakov #define GCC_BLSP1_QUP3_SPI_APPS_CLK 107 11702824653SGeorgi Djakov #define GCC_BLSP1_QUP4_I2C_APPS_CLK 108 11802824653SGeorgi Djakov #define GCC_BLSP1_QUP4_SPI_APPS_CLK 109 11902824653SGeorgi Djakov #define GCC_BLSP1_QUP5_I2C_APPS_CLK 110 12002824653SGeorgi Djakov #define GCC_BLSP1_QUP5_SPI_APPS_CLK 111 12102824653SGeorgi Djakov #define GCC_BLSP1_QUP6_I2C_APPS_CLK 112 12202824653SGeorgi Djakov #define GCC_BLSP1_QUP6_SPI_APPS_CLK 113 12302824653SGeorgi Djakov #define GCC_BLSP1_UART1_APPS_CLK 114 12402824653SGeorgi Djakov #define GCC_BLSP1_UART1_SIM_CLK 115 12502824653SGeorgi Djakov #define GCC_BLSP1_UART2_APPS_CLK 116 12602824653SGeorgi Djakov #define GCC_BLSP1_UART2_SIM_CLK 117 12702824653SGeorgi Djakov #define GCC_BLSP1_UART3_APPS_CLK 118 12802824653SGeorgi Djakov #define GCC_BLSP1_UART3_SIM_CLK 119 12902824653SGeorgi Djakov #define GCC_BLSP1_UART4_APPS_CLK 120 13002824653SGeorgi Djakov #define GCC_BLSP1_UART4_SIM_CLK 121 13102824653SGeorgi Djakov #define GCC_BLSP1_UART5_APPS_CLK 122 13202824653SGeorgi Djakov #define GCC_BLSP1_UART5_SIM_CLK 123 13302824653SGeorgi Djakov #define GCC_BLSP1_UART6_APPS_CLK 124 13402824653SGeorgi Djakov #define GCC_BLSP1_UART6_SIM_CLK 125 13502824653SGeorgi Djakov #define GCC_BLSP2_AHB_CLK 126 13602824653SGeorgi Djakov #define GCC_BLSP2_SLEEP_CLK 127 13702824653SGeorgi Djakov #define GCC_BLSP2_QUP1_I2C_APPS_CLK 128 13802824653SGeorgi Djakov #define GCC_BLSP2_QUP1_SPI_APPS_CLK 129 13902824653SGeorgi Djakov #define GCC_BLSP2_QUP2_I2C_APPS_CLK 130 14002824653SGeorgi Djakov #define GCC_BLSP2_QUP2_SPI_APPS_CLK 131 14102824653SGeorgi Djakov #define GCC_BLSP2_QUP3_I2C_APPS_CLK 132 14202824653SGeorgi Djakov #define GCC_BLSP2_QUP3_SPI_APPS_CLK 133 14302824653SGeorgi Djakov #define GCC_BLSP2_QUP4_I2C_APPS_CLK 134 14402824653SGeorgi Djakov #define GCC_BLSP2_QUP4_SPI_APPS_CLK 135 14502824653SGeorgi Djakov #define GCC_BLSP2_QUP5_I2C_APPS_CLK 136 14602824653SGeorgi Djakov #define GCC_BLSP2_QUP5_SPI_APPS_CLK 137 14702824653SGeorgi Djakov #define GCC_BLSP2_QUP6_I2C_APPS_CLK 138 14802824653SGeorgi Djakov #define GCC_BLSP2_QUP6_SPI_APPS_CLK 139 14902824653SGeorgi Djakov #define GCC_BLSP2_UART1_APPS_CLK 140 15002824653SGeorgi Djakov #define GCC_BLSP2_UART1_SIM_CLK 141 15102824653SGeorgi Djakov #define GCC_BLSP2_UART2_APPS_CLK 142 15202824653SGeorgi Djakov #define GCC_BLSP2_UART2_SIM_CLK 143 15302824653SGeorgi Djakov #define GCC_BLSP2_UART3_APPS_CLK 144 15402824653SGeorgi Djakov #define GCC_BLSP2_UART3_SIM_CLK 145 15502824653SGeorgi Djakov #define GCC_BLSP2_UART4_APPS_CLK 146 15602824653SGeorgi Djakov #define GCC_BLSP2_UART4_SIM_CLK 147 15702824653SGeorgi Djakov #define GCC_BLSP2_UART5_APPS_CLK 148 15802824653SGeorgi Djakov #define GCC_BLSP2_UART5_SIM_CLK 149 15902824653SGeorgi Djakov #define GCC_BLSP2_UART6_APPS_CLK 150 16002824653SGeorgi Djakov #define GCC_BLSP2_UART6_SIM_CLK 151 16102824653SGeorgi Djakov #define GCC_BOOT_ROM_AHB_CLK 152 16202824653SGeorgi Djakov #define GCC_CE1_AHB_CLK 153 16302824653SGeorgi Djakov #define GCC_CE1_AXI_CLK 154 16402824653SGeorgi Djakov #define GCC_CE1_CLK 155 16502824653SGeorgi Djakov #define GCC_CE2_AHB_CLK 156 16602824653SGeorgi Djakov #define GCC_CE2_AXI_CLK 157 16702824653SGeorgi Djakov #define GCC_CE2_CLK 158 16802824653SGeorgi Djakov #define GCC_CE3_AHB_CLK 159 16902824653SGeorgi Djakov #define GCC_CE3_AXI_CLK 160 17002824653SGeorgi Djakov #define GCC_CE3_CLK 161 17102824653SGeorgi Djakov #define GCC_CNOC_BUS_TIMEOUT0_AHB_CLK 162 17202824653SGeorgi Djakov #define GCC_CNOC_BUS_TIMEOUT1_AHB_CLK 163 17302824653SGeorgi Djakov #define GCC_CNOC_BUS_TIMEOUT2_AHB_CLK 164 17402824653SGeorgi Djakov #define GCC_CNOC_BUS_TIMEOUT3_AHB_CLK 165 17502824653SGeorgi Djakov #define GCC_CNOC_BUS_TIMEOUT4_AHB_CLK 166 17602824653SGeorgi Djakov #define GCC_CNOC_BUS_TIMEOUT5_AHB_CLK 167 17702824653SGeorgi Djakov #define GCC_CNOC_BUS_TIMEOUT6_AHB_CLK 168 17802824653SGeorgi Djakov #define GCC_CNOC_BUS_TIMEOUT7_AHB_CLK 169 17902824653SGeorgi Djakov #define GCC_CFG_NOC_AHB_CLK 170 18002824653SGeorgi Djakov #define GCC_CFG_NOC_DDR_CFG_CLK 171 18102824653SGeorgi Djakov #define GCC_CFG_NOC_RPM_AHB_CLK 172 18202824653SGeorgi Djakov #define GCC_COPSS_SMMU_AHB_CLK 173 18302824653SGeorgi Djakov #define GCC_COPSS_SMMU_AXI_CLK 174 18402824653SGeorgi Djakov #define GCC_DCD_XO_CLK 175 18502824653SGeorgi Djakov #define GCC_BIMC_DDR_CH0_CLK 176 18602824653SGeorgi Djakov #define GCC_BIMC_DDR_CH1_CLK 177 18702824653SGeorgi Djakov #define GCC_BIMC_DDR_CPLL0_CLK 178 18802824653SGeorgi Djakov #define GCC_BIMC_DDR_CPLL1_CLK 179 18902824653SGeorgi Djakov #define GCC_BIMC_GFX_CLK 180 19002824653SGeorgi Djakov #define GCC_DDR_DIM_CFG_CLK 181 19102824653SGeorgi Djakov #define GCC_DDR_DIM_SLEEP_CLK 182 19202824653SGeorgi Djakov #define GCC_DEHR_CLK 183 19302824653SGeorgi Djakov #define GCC_AHB_CLK 184 19402824653SGeorgi Djakov #define GCC_IM_SLEEP_CLK 185 19502824653SGeorgi Djakov #define GCC_XO_CLK 186 19602824653SGeorgi Djakov #define GCC_XO_DIV4_CLK 187 19702824653SGeorgi Djakov #define GCC_GP1_CLK 188 19802824653SGeorgi Djakov #define GCC_GP2_CLK 189 19902824653SGeorgi Djakov #define GCC_GP3_CLK 190 20002824653SGeorgi Djakov #define GCC_IMEM_AXI_CLK 191 20102824653SGeorgi Djakov #define GCC_IMEM_CFG_AHB_CLK 192 20202824653SGeorgi Djakov #define GCC_KPSS_AHB_CLK 193 20302824653SGeorgi Djakov #define GCC_KPSS_AXI_CLK 194 20402824653SGeorgi Djakov #define GCC_LPASS_MPORT_AXI_CLK 195 20502824653SGeorgi Djakov #define GCC_LPASS_Q6_AXI_CLK 196 20602824653SGeorgi Djakov #define GCC_LPASS_SWAY_CLK 197 20702824653SGeorgi Djakov #define GCC_MMSS_BIMC_GFX_CLK 198 20802824653SGeorgi Djakov #define GCC_MMSS_NOC_AT_CLK 199 20902824653SGeorgi Djakov #define GCC_MMSS_NOC_CFG_AHB_CLK 200 21002824653SGeorgi Djakov #define GCC_MMSS_VPU_MAPLE_SYS_NOC_AXI_CLK 201 21102824653SGeorgi Djakov #define GCC_OCMEM_NOC_CFG_AHB_CLK 202 21202824653SGeorgi Djakov #define GCC_OCMEM_SYS_NOC_AXI_CLK 203 21302824653SGeorgi Djakov #define GCC_MPM_AHB_CLK 204 21402824653SGeorgi Djakov #define GCC_MSG_RAM_AHB_CLK 205 21502824653SGeorgi Djakov #define GCC_NOC_CONF_XPU_AHB_CLK 206 21602824653SGeorgi Djakov #define GCC_PDM2_CLK 207 21702824653SGeorgi Djakov #define GCC_PDM_AHB_CLK 208 21802824653SGeorgi Djakov #define GCC_PDM_XO4_CLK 209 21902824653SGeorgi Djakov #define GCC_PERIPH_NOC_AHB_CLK 210 22002824653SGeorgi Djakov #define GCC_PERIPH_NOC_AT_CLK 211 22102824653SGeorgi Djakov #define GCC_PERIPH_NOC_CFG_AHB_CLK 212 22202824653SGeorgi Djakov #define GCC_PERIPH_NOC_USB_HSIC_AHB_CLK 213 22302824653SGeorgi Djakov #define GCC_PERIPH_NOC_MPU_CFG_AHB_CLK 214 22402824653SGeorgi Djakov #define GCC_PERIPH_XPU_AHB_CLK 215 22502824653SGeorgi Djakov #define GCC_PNOC_BUS_TIMEOUT0_AHB_CLK 216 22602824653SGeorgi Djakov #define GCC_PNOC_BUS_TIMEOUT1_AHB_CLK 217 22702824653SGeorgi Djakov #define GCC_PNOC_BUS_TIMEOUT2_AHB_CLK 218 22802824653SGeorgi Djakov #define GCC_PNOC_BUS_TIMEOUT3_AHB_CLK 219 22902824653SGeorgi Djakov #define GCC_PNOC_BUS_TIMEOUT4_AHB_CLK 220 23002824653SGeorgi Djakov #define GCC_PRNG_AHB_CLK 221 23102824653SGeorgi Djakov #define GCC_QDSS_AT_CLK 222 23202824653SGeorgi Djakov #define GCC_QDSS_CFG_AHB_CLK 223 23302824653SGeorgi Djakov #define GCC_QDSS_DAP_AHB_CLK 224 23402824653SGeorgi Djakov #define GCC_QDSS_DAP_CLK 225 23502824653SGeorgi Djakov #define GCC_QDSS_ETR_USB_CLK 226 23602824653SGeorgi Djakov #define GCC_QDSS_STM_CLK 227 23702824653SGeorgi Djakov #define GCC_QDSS_TRACECLKIN_CLK 228 23802824653SGeorgi Djakov #define GCC_QDSS_TSCTR_DIV16_CLK 229 23902824653SGeorgi Djakov #define GCC_QDSS_TSCTR_DIV2_CLK 230 24002824653SGeorgi Djakov #define GCC_QDSS_TSCTR_DIV3_CLK 231 24102824653SGeorgi Djakov #define GCC_QDSS_TSCTR_DIV4_CLK 232 24202824653SGeorgi Djakov #define GCC_QDSS_TSCTR_DIV8_CLK 233 24302824653SGeorgi Djakov #define GCC_QDSS_RBCPR_XPU_AHB_CLK 234 24402824653SGeorgi Djakov #define GCC_RBCPR_AHB_CLK 235 24502824653SGeorgi Djakov #define GCC_RBCPR_CLK 236 24602824653SGeorgi Djakov #define GCC_RPM_BUS_AHB_CLK 237 24702824653SGeorgi Djakov #define GCC_RPM_PROC_HCLK 238 24802824653SGeorgi Djakov #define GCC_RPM_SLEEP_CLK 239 24902824653SGeorgi Djakov #define GCC_RPM_TIMER_CLK 240 25002824653SGeorgi Djakov #define GCC_SATA_ASIC0_CLK 241 25102824653SGeorgi Djakov #define GCC_SATA_AXI_CLK 242 25202824653SGeorgi Djakov #define GCC_SATA_CFG_AHB_CLK 243 25302824653SGeorgi Djakov #define GCC_SATA_PMALIVE_CLK 244 25402824653SGeorgi Djakov #define GCC_SATA_RX_CLK 245 25502824653SGeorgi Djakov #define GCC_SATA_RX_OOB_CLK 246 25602824653SGeorgi Djakov #define GCC_SDCC1_AHB_CLK 247 25702824653SGeorgi Djakov #define GCC_SDCC1_APPS_CLK 248 25802824653SGeorgi Djakov #define GCC_SDCC1_CDCCAL_FF_CLK 249 25902824653SGeorgi Djakov #define GCC_SDCC1_CDCCAL_SLEEP_CLK 250 26002824653SGeorgi Djakov #define GCC_SDCC2_AHB_CLK 251 26102824653SGeorgi Djakov #define GCC_SDCC2_APPS_CLK 252 26202824653SGeorgi Djakov #define GCC_SDCC2_INACTIVITY_TIMERS_CLK 253 26302824653SGeorgi Djakov #define GCC_SDCC3_AHB_CLK 254 26402824653SGeorgi Djakov #define GCC_SDCC3_APPS_CLK 255 26502824653SGeorgi Djakov #define GCC_SDCC3_INACTIVITY_TIMERS_CLK 256 26602824653SGeorgi Djakov #define GCC_SDCC4_AHB_CLK 257 26702824653SGeorgi Djakov #define GCC_SDCC4_APPS_CLK 258 26802824653SGeorgi Djakov #define GCC_SDCC4_INACTIVITY_TIMERS_CLK 259 26902824653SGeorgi Djakov #define GCC_SEC_CTRL_ACC_CLK 260 27002824653SGeorgi Djakov #define GCC_SEC_CTRL_AHB_CLK 261 27102824653SGeorgi Djakov #define GCC_SEC_CTRL_BOOT_ROM_PATCH_CLK 262 27202824653SGeorgi Djakov #define GCC_SEC_CTRL_CLK 263 27302824653SGeorgi Djakov #define GCC_SEC_CTRL_SENSE_CLK 264 27402824653SGeorgi Djakov #define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 265 27502824653SGeorgi Djakov #define GCC_SNOC_BUS_TIMEOUT3_AHB_CLK 266 27602824653SGeorgi Djakov #define GCC_SPDM_BIMC_CY_CLK 267 27702824653SGeorgi Djakov #define GCC_SPDM_CFG_AHB_CLK 268 27802824653SGeorgi Djakov #define GCC_SPDM_DEBUG_CY_CLK 269 27902824653SGeorgi Djakov #define GCC_SPDM_FF_CLK 270 28002824653SGeorgi Djakov #define GCC_SPDM_MSTR_AHB_CLK 271 28102824653SGeorgi Djakov #define GCC_SPDM_PNOC_CY_CLK 272 28202824653SGeorgi Djakov #define GCC_SPDM_RPM_CY_CLK 273 28302824653SGeorgi Djakov #define GCC_SPDM_SNOC_CY_CLK 274 28402824653SGeorgi Djakov #define GCC_SPMI_AHB_CLK 275 28502824653SGeorgi Djakov #define GCC_SPMI_CNOC_AHB_CLK 276 28602824653SGeorgi Djakov #define GCC_SPMI_SER_CLK 277 28702824653SGeorgi Djakov #define GCC_SPSS_AHB_CLK 278 28802824653SGeorgi Djakov #define GCC_SNOC_CNOC_AHB_CLK 279 28902824653SGeorgi Djakov #define GCC_SNOC_PNOC_AHB_CLK 280 29002824653SGeorgi Djakov #define GCC_SYS_NOC_AT_CLK 281 29102824653SGeorgi Djakov #define GCC_SYS_NOC_AXI_CLK 282 29202824653SGeorgi Djakov #define GCC_SYS_NOC_KPSS_AHB_CLK 283 29302824653SGeorgi Djakov #define GCC_SYS_NOC_QDSS_STM_AXI_CLK 284 29402824653SGeorgi Djakov #define GCC_SYS_NOC_UFS_AXI_CLK 285 29502824653SGeorgi Djakov #define GCC_SYS_NOC_USB3_AXI_CLK 286 29602824653SGeorgi Djakov #define GCC_SYS_NOC_USB3_SEC_AXI_CLK 287 29702824653SGeorgi Djakov #define GCC_TCSR_AHB_CLK 288 29802824653SGeorgi Djakov #define GCC_TLMM_AHB_CLK 289 29902824653SGeorgi Djakov #define GCC_TLMM_CLK 290 30002824653SGeorgi Djakov #define GCC_TSIF_AHB_CLK 291 30102824653SGeorgi Djakov #define GCC_TSIF_INACTIVITY_TIMERS_CLK 292 30202824653SGeorgi Djakov #define GCC_TSIF_REF_CLK 293 30302824653SGeorgi Djakov #define GCC_UFS_AHB_CLK 294 30402824653SGeorgi Djakov #define GCC_UFS_AXI_CLK 295 30502824653SGeorgi Djakov #define GCC_UFS_RX_CFG_CLK 296 30602824653SGeorgi Djakov #define GCC_UFS_RX_SYMBOL_0_CLK 297 30702824653SGeorgi Djakov #define GCC_UFS_RX_SYMBOL_1_CLK 298 30802824653SGeorgi Djakov #define GCC_UFS_TX_CFG_CLK 299 30902824653SGeorgi Djakov #define GCC_UFS_TX_SYMBOL_0_CLK 300 31002824653SGeorgi Djakov #define GCC_UFS_TX_SYMBOL_1_CLK 301 31102824653SGeorgi Djakov #define GCC_USB2A_PHY_SLEEP_CLK 302 31202824653SGeorgi Djakov #define GCC_USB2B_PHY_SLEEP_CLK 303 31302824653SGeorgi Djakov #define GCC_USB30_MASTER_CLK 304 31402824653SGeorgi Djakov #define GCC_USB30_MOCK_UTMI_CLK 305 31502824653SGeorgi Djakov #define GCC_USB30_SLEEP_CLK 306 31602824653SGeorgi Djakov #define GCC_USB30_SEC_MASTER_CLK 307 31702824653SGeorgi Djakov #define GCC_USB30_SEC_MOCK_UTMI_CLK 308 31802824653SGeorgi Djakov #define GCC_USB30_SEC_SLEEP_CLK 309 31902824653SGeorgi Djakov #define GCC_USB_HS_AHB_CLK 310 32002824653SGeorgi Djakov #define GCC_USB_HS_INACTIVITY_TIMERS_CLK 311 32102824653SGeorgi Djakov #define GCC_USB_HS_SYSTEM_CLK 312 32202824653SGeorgi Djakov #define GCC_USB_HSIC_AHB_CLK 313 32302824653SGeorgi Djakov #define GCC_USB_HSIC_CLK 314 32402824653SGeorgi Djakov #define GCC_USB_HSIC_IO_CAL_CLK 315 32502824653SGeorgi Djakov #define GCC_USB_HSIC_IO_CAL_SLEEP_CLK 316 32602824653SGeorgi Djakov #define GCC_USB_HSIC_MOCK_UTMI_CLK 317 32702824653SGeorgi Djakov #define GCC_USB_HSIC_SYSTEM_CLK 318 3285424e102SGeorgi Djakov #define PCIE_0_AUX_CLK_SRC 319 3295424e102SGeorgi Djakov #define PCIE_0_PIPE_CLK_SRC 320 3305424e102SGeorgi Djakov #define PCIE_1_AUX_CLK_SRC 321 3315424e102SGeorgi Djakov #define PCIE_1_PIPE_CLK_SRC 322 3325424e102SGeorgi Djakov #define GCC_PCIE_0_AUX_CLK 323 3335424e102SGeorgi Djakov #define GCC_PCIE_0_CFG_AHB_CLK 324 3345424e102SGeorgi Djakov #define GCC_PCIE_0_MSTR_AXI_CLK 325 3355424e102SGeorgi Djakov #define GCC_PCIE_0_PIPE_CLK 326 3365424e102SGeorgi Djakov #define GCC_PCIE_0_SLV_AXI_CLK 327 3375424e102SGeorgi Djakov #define GCC_PCIE_1_AUX_CLK 328 3385424e102SGeorgi Djakov #define GCC_PCIE_1_CFG_AHB_CLK 329 3395424e102SGeorgi Djakov #define GCC_PCIE_1_MSTR_AXI_CLK 330 3405424e102SGeorgi Djakov #define GCC_PCIE_1_PIPE_CLK 331 3415424e102SGeorgi Djakov #define GCC_PCIE_1_SLV_AXI_CLK 332 342*93a63522SDmitry Baryshkov #define GCC_MMSS_GPLL0_CLK_SRC 333 34302824653SGeorgi Djakov 344639af949SRajendra Nayak /* gdscs */ 345639af949SRajendra Nayak #define USB_HS_HSIC_GDSC 0 346639af949SRajendra Nayak #define PCIE0_GDSC 1 347639af949SRajendra Nayak #define PCIE1_GDSC 2 348639af949SRajendra Nayak #define USB30_GDSC 3 349639af949SRajendra Nayak 35002824653SGeorgi Djakov #endif 351