1*6914b82fSKonrad Dybcio /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*6914b82fSKonrad Dybcio /* 3*6914b82fSKonrad Dybcio * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4*6914b82fSKonrad Dybcio * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> 5*6914b82fSKonrad Dybcio */ 6*6914b82fSKonrad Dybcio 7*6914b82fSKonrad Dybcio #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6350_H 8*6914b82fSKonrad Dybcio #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6350_H 9*6914b82fSKonrad Dybcio 10*6914b82fSKonrad Dybcio /* DISP_CC clocks */ 11*6914b82fSKonrad Dybcio #define DISP_CC_PLL0 0 12*6914b82fSKonrad Dybcio #define DISP_CC_MDSS_AHB_CLK 1 13*6914b82fSKonrad Dybcio #define DISP_CC_MDSS_AHB_CLK_SRC 2 14*6914b82fSKonrad Dybcio #define DISP_CC_MDSS_BYTE0_CLK 3 15*6914b82fSKonrad Dybcio #define DISP_CC_MDSS_BYTE0_CLK_SRC 4 16*6914b82fSKonrad Dybcio #define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5 17*6914b82fSKonrad Dybcio #define DISP_CC_MDSS_BYTE0_INTF_CLK 6 18*6914b82fSKonrad Dybcio #define DISP_CC_MDSS_DP_AUX_CLK 7 19*6914b82fSKonrad Dybcio #define DISP_CC_MDSS_DP_AUX_CLK_SRC 8 20*6914b82fSKonrad Dybcio #define DISP_CC_MDSS_DP_CRYPTO_CLK 9 21*6914b82fSKonrad Dybcio #define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 10 22*6914b82fSKonrad Dybcio #define DISP_CC_MDSS_DP_LINK_CLK 11 23*6914b82fSKonrad Dybcio #define DISP_CC_MDSS_DP_LINK_CLK_SRC 12 24*6914b82fSKonrad Dybcio #define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 13 25*6914b82fSKonrad Dybcio #define DISP_CC_MDSS_DP_LINK_INTF_CLK 14 26*6914b82fSKonrad Dybcio #define DISP_CC_MDSS_DP_PIXEL_CLK 15 27*6914b82fSKonrad Dybcio #define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 16 28*6914b82fSKonrad Dybcio #define DISP_CC_MDSS_ESC0_CLK 17 29*6914b82fSKonrad Dybcio #define DISP_CC_MDSS_ESC0_CLK_SRC 18 30*6914b82fSKonrad Dybcio #define DISP_CC_MDSS_MDP_CLK 19 31*6914b82fSKonrad Dybcio #define DISP_CC_MDSS_MDP_CLK_SRC 20 32*6914b82fSKonrad Dybcio #define DISP_CC_MDSS_MDP_LUT_CLK 21 33*6914b82fSKonrad Dybcio #define DISP_CC_MDSS_NON_GDSC_AHB_CLK 22 34*6914b82fSKonrad Dybcio #define DISP_CC_MDSS_PCLK0_CLK 23 35*6914b82fSKonrad Dybcio #define DISP_CC_MDSS_PCLK0_CLK_SRC 24 36*6914b82fSKonrad Dybcio #define DISP_CC_MDSS_ROT_CLK 25 37*6914b82fSKonrad Dybcio #define DISP_CC_MDSS_ROT_CLK_SRC 26 38*6914b82fSKonrad Dybcio #define DISP_CC_MDSS_RSCC_AHB_CLK 27 39*6914b82fSKonrad Dybcio #define DISP_CC_MDSS_RSCC_VSYNC_CLK 28 40*6914b82fSKonrad Dybcio #define DISP_CC_MDSS_VSYNC_CLK 29 41*6914b82fSKonrad Dybcio #define DISP_CC_MDSS_VSYNC_CLK_SRC 30 42*6914b82fSKonrad Dybcio #define DISP_CC_SLEEP_CLK 31 43*6914b82fSKonrad Dybcio #define DISP_CC_XO_CLK 32 44*6914b82fSKonrad Dybcio 45*6914b82fSKonrad Dybcio /* GDSCs */ 46*6914b82fSKonrad Dybcio #define MDSS_GDSC 0 47*6914b82fSKonrad Dybcio 48*6914b82fSKonrad Dybcio #endif 49