16c79d12eSTaniya Das /* SPDX-License-Identifier: GPL-2.0 */ 26c79d12eSTaniya Das /* 3*c1079b4eSTaniya Das * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. 46c79d12eSTaniya Das */ 56c79d12eSTaniya Das 66c79d12eSTaniya Das #ifndef _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H 76c79d12eSTaniya Das #define _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H 86c79d12eSTaniya Das 96c79d12eSTaniya Das /* DISP_CC clock registers */ 106c79d12eSTaniya Das #define DISP_CC_MDSS_AHB_CLK 0 116c79d12eSTaniya Das #define DISP_CC_MDSS_AXI_CLK 1 126c79d12eSTaniya Das #define DISP_CC_MDSS_BYTE0_CLK 2 136c79d12eSTaniya Das #define DISP_CC_MDSS_BYTE0_CLK_SRC 3 146c79d12eSTaniya Das #define DISP_CC_MDSS_BYTE0_INTF_CLK 4 156c79d12eSTaniya Das #define DISP_CC_MDSS_BYTE1_CLK 5 166c79d12eSTaniya Das #define DISP_CC_MDSS_BYTE1_CLK_SRC 6 176c79d12eSTaniya Das #define DISP_CC_MDSS_BYTE1_INTF_CLK 7 186c79d12eSTaniya Das #define DISP_CC_MDSS_ESC0_CLK 8 196c79d12eSTaniya Das #define DISP_CC_MDSS_ESC0_CLK_SRC 9 206c79d12eSTaniya Das #define DISP_CC_MDSS_ESC1_CLK 10 216c79d12eSTaniya Das #define DISP_CC_MDSS_ESC1_CLK_SRC 11 226c79d12eSTaniya Das #define DISP_CC_MDSS_MDP_CLK 12 236c79d12eSTaniya Das #define DISP_CC_MDSS_MDP_CLK_SRC 13 246c79d12eSTaniya Das #define DISP_CC_MDSS_MDP_LUT_CLK 14 256c79d12eSTaniya Das #define DISP_CC_MDSS_PCLK0_CLK 15 266c79d12eSTaniya Das #define DISP_CC_MDSS_PCLK0_CLK_SRC 16 276c79d12eSTaniya Das #define DISP_CC_MDSS_PCLK1_CLK 17 286c79d12eSTaniya Das #define DISP_CC_MDSS_PCLK1_CLK_SRC 18 296c79d12eSTaniya Das #define DISP_CC_MDSS_ROT_CLK 19 306c79d12eSTaniya Das #define DISP_CC_MDSS_ROT_CLK_SRC 20 316c79d12eSTaniya Das #define DISP_CC_MDSS_RSCC_AHB_CLK 21 326c79d12eSTaniya Das #define DISP_CC_MDSS_RSCC_VSYNC_CLK 22 336c79d12eSTaniya Das #define DISP_CC_MDSS_VSYNC_CLK 23 346c79d12eSTaniya Das #define DISP_CC_MDSS_VSYNC_CLK_SRC 24 356c79d12eSTaniya Das #define DISP_CC_PLL0 25 366c79d12eSTaniya Das #define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 26 376c79d12eSTaniya Das #define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 27 38*c1079b4eSTaniya Das #define DISP_CC_MDSS_DP_AUX_CLK 28 39*c1079b4eSTaniya Das #define DISP_CC_MDSS_DP_AUX_CLK_SRC 29 40*c1079b4eSTaniya Das #define DISP_CC_MDSS_DP_CRYPTO_CLK 30 41*c1079b4eSTaniya Das #define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 31 42*c1079b4eSTaniya Das #define DISP_CC_MDSS_DP_LINK_CLK 32 43*c1079b4eSTaniya Das #define DISP_CC_MDSS_DP_LINK_CLK_SRC 33 44*c1079b4eSTaniya Das #define DISP_CC_MDSS_DP_LINK_INTF_CLK 34 45*c1079b4eSTaniya Das #define DISP_CC_MDSS_DP_PIXEL1_CLK 35 46*c1079b4eSTaniya Das #define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 36 47*c1079b4eSTaniya Das #define DISP_CC_MDSS_DP_PIXEL_CLK 37 48*c1079b4eSTaniya Das #define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 38 496c79d12eSTaniya Das 506c79d12eSTaniya Das /* DISP_CC Reset */ 516c79d12eSTaniya Das #define DISP_CC_MDSS_RSCC_BCR 0 526c79d12eSTaniya Das 536c79d12eSTaniya Das /* DISP_CC GDSCR */ 546c79d12eSTaniya Das #define MDSS_GDSC 0 556c79d12eSTaniya Das 566c79d12eSTaniya Das #endif 57