1*ced3aaeaSTaniya Das /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*ced3aaeaSTaniya Das /* 3*ced3aaeaSTaniya Das * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4*ced3aaeaSTaniya Das */ 5*ced3aaeaSTaniya Das 6*ced3aaeaSTaniya Das #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7280_H 7*ced3aaeaSTaniya Das #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7280_H 8*ced3aaeaSTaniya Das 9*ced3aaeaSTaniya Das /* DISP_CC clocks */ 10*ced3aaeaSTaniya Das #define DISP_CC_PLL0 0 11*ced3aaeaSTaniya Das #define DISP_CC_MDSS_AHB_CLK 1 12*ced3aaeaSTaniya Das #define DISP_CC_MDSS_AHB_CLK_SRC 2 13*ced3aaeaSTaniya Das #define DISP_CC_MDSS_BYTE0_CLK 3 14*ced3aaeaSTaniya Das #define DISP_CC_MDSS_BYTE0_CLK_SRC 4 15*ced3aaeaSTaniya Das #define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5 16*ced3aaeaSTaniya Das #define DISP_CC_MDSS_BYTE0_INTF_CLK 6 17*ced3aaeaSTaniya Das #define DISP_CC_MDSS_DP_AUX_CLK 7 18*ced3aaeaSTaniya Das #define DISP_CC_MDSS_DP_AUX_CLK_SRC 8 19*ced3aaeaSTaniya Das #define DISP_CC_MDSS_DP_CRYPTO_CLK 9 20*ced3aaeaSTaniya Das #define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 10 21*ced3aaeaSTaniya Das #define DISP_CC_MDSS_DP_LINK_CLK 11 22*ced3aaeaSTaniya Das #define DISP_CC_MDSS_DP_LINK_CLK_SRC 12 23*ced3aaeaSTaniya Das #define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 13 24*ced3aaeaSTaniya Das #define DISP_CC_MDSS_DP_LINK_INTF_CLK 14 25*ced3aaeaSTaniya Das #define DISP_CC_MDSS_DP_PIXEL_CLK 15 26*ced3aaeaSTaniya Das #define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 16 27*ced3aaeaSTaniya Das #define DISP_CC_MDSS_EDP_AUX_CLK 17 28*ced3aaeaSTaniya Das #define DISP_CC_MDSS_EDP_AUX_CLK_SRC 18 29*ced3aaeaSTaniya Das #define DISP_CC_MDSS_EDP_LINK_CLK 19 30*ced3aaeaSTaniya Das #define DISP_CC_MDSS_EDP_LINK_CLK_SRC 20 31*ced3aaeaSTaniya Das #define DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC 21 32*ced3aaeaSTaniya Das #define DISP_CC_MDSS_EDP_LINK_INTF_CLK 22 33*ced3aaeaSTaniya Das #define DISP_CC_MDSS_EDP_PIXEL_CLK 23 34*ced3aaeaSTaniya Das #define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC 24 35*ced3aaeaSTaniya Das #define DISP_CC_MDSS_ESC0_CLK 25 36*ced3aaeaSTaniya Das #define DISP_CC_MDSS_ESC0_CLK_SRC 26 37*ced3aaeaSTaniya Das #define DISP_CC_MDSS_MDP_CLK 27 38*ced3aaeaSTaniya Das #define DISP_CC_MDSS_MDP_CLK_SRC 28 39*ced3aaeaSTaniya Das #define DISP_CC_MDSS_MDP_LUT_CLK 29 40*ced3aaeaSTaniya Das #define DISP_CC_MDSS_NON_GDSC_AHB_CLK 30 41*ced3aaeaSTaniya Das #define DISP_CC_MDSS_PCLK0_CLK 31 42*ced3aaeaSTaniya Das #define DISP_CC_MDSS_PCLK0_CLK_SRC 32 43*ced3aaeaSTaniya Das #define DISP_CC_MDSS_ROT_CLK 33 44*ced3aaeaSTaniya Das #define DISP_CC_MDSS_ROT_CLK_SRC 34 45*ced3aaeaSTaniya Das #define DISP_CC_MDSS_RSCC_AHB_CLK 35 46*ced3aaeaSTaniya Das #define DISP_CC_MDSS_RSCC_VSYNC_CLK 36 47*ced3aaeaSTaniya Das #define DISP_CC_MDSS_VSYNC_CLK 37 48*ced3aaeaSTaniya Das #define DISP_CC_MDSS_VSYNC_CLK_SRC 38 49*ced3aaeaSTaniya Das #define DISP_CC_SLEEP_CLK 39 50*ced3aaeaSTaniya Das #define DISP_CC_XO_CLK 40 51*ced3aaeaSTaniya Das 52*ced3aaeaSTaniya Das /* DISP_CC power domains */ 53*ced3aaeaSTaniya Das #define DISP_CC_MDSS_CORE_GDSC 0 54*ced3aaeaSTaniya Das 55*ced3aaeaSTaniya Das #endif 56