1*39c8378aSLars Povlsen /* SPDX-License-Identifier: GPL-2.0-only */ 2*39c8378aSLars Povlsen /* 3*39c8378aSLars Povlsen * Copyright (c) 2019 Microchip Inc. 4*39c8378aSLars Povlsen * 5*39c8378aSLars Povlsen * Author: Lars Povlsen <lars.povlsen@microchip.com> 6*39c8378aSLars Povlsen */ 7*39c8378aSLars Povlsen 8*39c8378aSLars Povlsen #ifndef _DT_BINDINGS_CLK_SPARX5_H 9*39c8378aSLars Povlsen #define _DT_BINDINGS_CLK_SPARX5_H 10*39c8378aSLars Povlsen 11*39c8378aSLars Povlsen #define CLK_ID_CORE 0 12*39c8378aSLars Povlsen #define CLK_ID_DDR 1 13*39c8378aSLars Povlsen #define CLK_ID_CPU2 2 14*39c8378aSLars Povlsen #define CLK_ID_ARM2 3 15*39c8378aSLars Povlsen #define CLK_ID_AUX1 4 16*39c8378aSLars Povlsen #define CLK_ID_AUX2 5 17*39c8378aSLars Povlsen #define CLK_ID_AUX3 6 18*39c8378aSLars Povlsen #define CLK_ID_AUX4 7 19*39c8378aSLars Povlsen #define CLK_ID_SYNCE 8 20*39c8378aSLars Povlsen 21*39c8378aSLars Povlsen #define N_CLOCKS 9 22*39c8378aSLars Povlsen 23*39c8378aSLars Povlsen #endif 24