1*a8159572SGiulio Benetti /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2*a8159572SGiulio Benetti /* 3*a8159572SGiulio Benetti * Copyright(C) 2019 4*a8159572SGiulio Benetti * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> 5*a8159572SGiulio Benetti */ 6*a8159572SGiulio Benetti 7*a8159572SGiulio Benetti #ifndef __DT_BINDINGS_CLOCK_IMXRT1050_H 8*a8159572SGiulio Benetti #define __DT_BINDINGS_CLOCK_IMXRT1050_H 9*a8159572SGiulio Benetti 10*a8159572SGiulio Benetti #define IMXRT1050_CLK_DUMMY 0 11*a8159572SGiulio Benetti #define IMXRT1050_CLK_CKIL 1 12*a8159572SGiulio Benetti #define IMXRT1050_CLK_CKIH 2 13*a8159572SGiulio Benetti #define IMXRT1050_CLK_OSC 3 14*a8159572SGiulio Benetti #define IMXRT1050_CLK_PLL2_PFD0_352M 4 15*a8159572SGiulio Benetti #define IMXRT1050_CLK_PLL2_PFD1_594M 5 16*a8159572SGiulio Benetti #define IMXRT1050_CLK_PLL2_PFD2_396M 6 17*a8159572SGiulio Benetti #define IMXRT1050_CLK_PLL3_PFD0_720M 7 18*a8159572SGiulio Benetti #define IMXRT1050_CLK_PLL3_PFD1_664_62M 8 19*a8159572SGiulio Benetti #define IMXRT1050_CLK_PLL3_PFD2_508_24M 9 20*a8159572SGiulio Benetti #define IMXRT1050_CLK_PLL3_PFD3_454_74M 10 21*a8159572SGiulio Benetti #define IMXRT1050_CLK_PLL2_198M 11 22*a8159572SGiulio Benetti #define IMXRT1050_CLK_PLL3_120M 12 23*a8159572SGiulio Benetti #define IMXRT1050_CLK_PLL3_80M 13 24*a8159572SGiulio Benetti #define IMXRT1050_CLK_PLL3_60M 14 25*a8159572SGiulio Benetti #define IMXRT1050_CLK_PLL1_BYPASS 15 26*a8159572SGiulio Benetti #define IMXRT1050_CLK_PLL2_BYPASS 16 27*a8159572SGiulio Benetti #define IMXRT1050_CLK_PLL3_BYPASS 17 28*a8159572SGiulio Benetti #define IMXRT1050_CLK_PLL5_BYPASS 19 29*a8159572SGiulio Benetti #define IMXRT1050_CLK_PLL1_REF_SEL 20 30*a8159572SGiulio Benetti #define IMXRT1050_CLK_PLL2_REF_SEL 21 31*a8159572SGiulio Benetti #define IMXRT1050_CLK_PLL3_REF_SEL 22 32*a8159572SGiulio Benetti #define IMXRT1050_CLK_PLL5_REF_SEL 23 33*a8159572SGiulio Benetti #define IMXRT1050_CLK_PRE_PERIPH_SEL 24 34*a8159572SGiulio Benetti #define IMXRT1050_CLK_PERIPH_SEL 25 35*a8159572SGiulio Benetti #define IMXRT1050_CLK_SEMC_ALT_SEL 26 36*a8159572SGiulio Benetti #define IMXRT1050_CLK_SEMC_SEL 27 37*a8159572SGiulio Benetti #define IMXRT1050_CLK_USDHC1_SEL 28 38*a8159572SGiulio Benetti #define IMXRT1050_CLK_USDHC2_SEL 29 39*a8159572SGiulio Benetti #define IMXRT1050_CLK_LPUART_SEL 30 40*a8159572SGiulio Benetti #define IMXRT1050_CLK_LCDIF_SEL 31 41*a8159572SGiulio Benetti #define IMXRT1050_CLK_VIDEO_POST_DIV_SEL 32 42*a8159572SGiulio Benetti #define IMXRT1050_CLK_VIDEO_DIV 33 43*a8159572SGiulio Benetti #define IMXRT1050_CLK_ARM_PODF 34 44*a8159572SGiulio Benetti #define IMXRT1050_CLK_LPUART_PODF 35 45*a8159572SGiulio Benetti #define IMXRT1050_CLK_USDHC1_PODF 36 46*a8159572SGiulio Benetti #define IMXRT1050_CLK_USDHC2_PODF 37 47*a8159572SGiulio Benetti #define IMXRT1050_CLK_SEMC_PODF 38 48*a8159572SGiulio Benetti #define IMXRT1050_CLK_AHB_PODF 39 49*a8159572SGiulio Benetti #define IMXRT1050_CLK_LCDIF_PRED 40 50*a8159572SGiulio Benetti #define IMXRT1050_CLK_LCDIF_PODF 41 51*a8159572SGiulio Benetti #define IMXRT1050_CLK_USDHC1 42 52*a8159572SGiulio Benetti #define IMXRT1050_CLK_USDHC2 43 53*a8159572SGiulio Benetti #define IMXRT1050_CLK_LPUART1 44 54*a8159572SGiulio Benetti #define IMXRT1050_CLK_SEMC 45 55*a8159572SGiulio Benetti #define IMXRT1050_CLK_LCDIF_APB 46 56*a8159572SGiulio Benetti #define IMXRT1050_CLK_PLL1_ARM 47 57*a8159572SGiulio Benetti #define IMXRT1050_CLK_PLL2_SYS 48 58*a8159572SGiulio Benetti #define IMXRT1050_CLK_PLL3_USB_OTG 49 59*a8159572SGiulio Benetti #define IMXRT1050_CLK_PLL4_AUDIO 50 60*a8159572SGiulio Benetti #define IMXRT1050_CLK_PLL5_VIDEO 51 61*a8159572SGiulio Benetti #define IMXRT1050_CLK_PLL6_ENET 52 62*a8159572SGiulio Benetti #define IMXRT1050_CLK_PLL7_USB_HOST 53 63*a8159572SGiulio Benetti #define IMXRT1050_CLK_LCDIF_PIX 54 64*a8159572SGiulio Benetti #define IMXRT1050_CLK_USBOH3 55 65*a8159572SGiulio Benetti #define IMXRT1050_CLK_IPG_PDOF 56 66*a8159572SGiulio Benetti #define IMXRT1050_CLK_PER_CLK_SEL 57 67*a8159572SGiulio Benetti #define IMXRT1050_CLK_PER_PDOF 58 68*a8159572SGiulio Benetti #define IMXRT1050_CLK_DMA 59 69*a8159572SGiulio Benetti #define IMXRT1050_CLK_DMA_MUX 60 70*a8159572SGiulio Benetti #define IMXRT1050_CLK_END 61 71*a8159572SGiulio Benetti 72*a8159572SGiulio Benetti #endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */ 73