1*1ccea77eSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2707d33cbSJiancheng Xue /* 3707d33cbSJiancheng Xue * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. 4707d33cbSJiancheng Xue */ 5707d33cbSJiancheng Xue 6707d33cbSJiancheng Xue #ifndef __DTS_HISTB_CLOCK_H 7707d33cbSJiancheng Xue #define __DTS_HISTB_CLOCK_H 8707d33cbSJiancheng Xue 9707d33cbSJiancheng Xue /* clocks provided by core CRG */ 10707d33cbSJiancheng Xue #define HISTB_OSC_CLK 0 11707d33cbSJiancheng Xue #define HISTB_APB_CLK 1 12707d33cbSJiancheng Xue #define HISTB_AHB_CLK 2 13707d33cbSJiancheng Xue #define HISTB_UART1_CLK 3 14707d33cbSJiancheng Xue #define HISTB_UART2_CLK 4 15707d33cbSJiancheng Xue #define HISTB_UART3_CLK 5 16707d33cbSJiancheng Xue #define HISTB_I2C0_CLK 6 17707d33cbSJiancheng Xue #define HISTB_I2C1_CLK 7 18707d33cbSJiancheng Xue #define HISTB_I2C2_CLK 8 19707d33cbSJiancheng Xue #define HISTB_I2C3_CLK 9 20707d33cbSJiancheng Xue #define HISTB_I2C4_CLK 10 21707d33cbSJiancheng Xue #define HISTB_I2C5_CLK 11 22707d33cbSJiancheng Xue #define HISTB_SPI0_CLK 12 23707d33cbSJiancheng Xue #define HISTB_SPI1_CLK 13 24707d33cbSJiancheng Xue #define HISTB_SPI2_CLK 14 25707d33cbSJiancheng Xue #define HISTB_SCI_CLK 15 26707d33cbSJiancheng Xue #define HISTB_FMC_CLK 16 27707d33cbSJiancheng Xue #define HISTB_MMC_BIU_CLK 17 28707d33cbSJiancheng Xue #define HISTB_MMC_CIU_CLK 18 29707d33cbSJiancheng Xue #define HISTB_MMC_DRV_CLK 19 30707d33cbSJiancheng Xue #define HISTB_MMC_SAMPLE_CLK 20 31707d33cbSJiancheng Xue #define HISTB_SDIO0_BIU_CLK 21 32707d33cbSJiancheng Xue #define HISTB_SDIO0_CIU_CLK 22 33707d33cbSJiancheng Xue #define HISTB_SDIO0_DRV_CLK 23 34707d33cbSJiancheng Xue #define HISTB_SDIO0_SAMPLE_CLK 24 35707d33cbSJiancheng Xue #define HISTB_PCIE_AUX_CLK 25 36707d33cbSJiancheng Xue #define HISTB_PCIE_PIPE_CLK 26 37707d33cbSJiancheng Xue #define HISTB_PCIE_SYS_CLK 27 38707d33cbSJiancheng Xue #define HISTB_PCIE_BUS_CLK 28 39707d33cbSJiancheng Xue #define HISTB_ETH0_MAC_CLK 29 40707d33cbSJiancheng Xue #define HISTB_ETH0_MACIF_CLK 30 41707d33cbSJiancheng Xue #define HISTB_ETH1_MAC_CLK 31 42707d33cbSJiancheng Xue #define HISTB_ETH1_MACIF_CLK 32 43707d33cbSJiancheng Xue #define HISTB_COMBPHY1_CLK 33 440d846596SJiancheng Xue #define HISTB_USB2_BUS_CLK 34 450d846596SJiancheng Xue #define HISTB_USB2_PHY_CLK 35 460d846596SJiancheng Xue #define HISTB_USB2_UTMI_CLK 36 470d846596SJiancheng Xue #define HISTB_USB2_12M_CLK 37 480d846596SJiancheng Xue #define HISTB_USB2_48M_CLK 38 490d846596SJiancheng Xue #define HISTB_USB2_OTG_UTMI_CLK 39 500d846596SJiancheng Xue #define HISTB_USB2_PHY1_REF_CLK 40 510d846596SJiancheng Xue #define HISTB_USB2_PHY2_REF_CLK 41 5280f8ce58SJianguo Sun #define HISTB_COMBPHY0_CLK 42 5380820a7bSJianguo Sun #define HISTB_USB3_BUS_CLK 43 5480820a7bSJianguo Sun #define HISTB_USB3_UTMI_CLK 44 5580820a7bSJianguo Sun #define HISTB_USB3_PIPE_CLK 45 5680820a7bSJianguo Sun #define HISTB_USB3_SUSPEND_CLK 46 5780820a7bSJianguo Sun #define HISTB_USB3_BUS_CLK1 47 5880820a7bSJianguo Sun #define HISTB_USB3_UTMI_CLK1 48 5980820a7bSJianguo Sun #define HISTB_USB3_PIPE_CLK1 49 6080820a7bSJianguo Sun #define HISTB_USB3_SUSPEND_CLK1 50 61707d33cbSJiancheng Xue 62707d33cbSJiancheng Xue /* clocks provided by mcu CRG */ 63707d33cbSJiancheng Xue #define HISTB_MCE_CLK 1 64707d33cbSJiancheng Xue #define HISTB_IR_CLK 2 65707d33cbSJiancheng Xue #define HISTB_TIMER01_CLK 3 66707d33cbSJiancheng Xue #define HISTB_LEDC_CLK 4 67707d33cbSJiancheng Xue #define HISTB_UART0_CLK 5 68707d33cbSJiancheng Xue #define HISTB_LSADC_CLK 6 69707d33cbSJiancheng Xue 70707d33cbSJiancheng Xue #endif /* __DTS_HISTB_CLOCK_H */ 71