1*923a77a2SYu Tu /* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ 2*923a77a2SYu Tu /* 3*923a77a2SYu Tu * Copyright (c) 2022-2023 Amlogic, Inc. All rights reserved. 4*923a77a2SYu Tu * Author: Yu Tu <yu.tu@amlogic.com> 5*923a77a2SYu Tu */ 6*923a77a2SYu Tu 7*923a77a2SYu Tu #ifndef _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H 8*923a77a2SYu Tu #define _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H 9*923a77a2SYu Tu 10*923a77a2SYu Tu #define CLKID_FIXED_PLL_DCO 0 11*923a77a2SYu Tu #define CLKID_FIXED_PLL 1 12*923a77a2SYu Tu #define CLKID_FCLK_DIV2_DIV 2 13*923a77a2SYu Tu #define CLKID_FCLK_DIV2 3 14*923a77a2SYu Tu #define CLKID_FCLK_DIV3_DIV 4 15*923a77a2SYu Tu #define CLKID_FCLK_DIV3 5 16*923a77a2SYu Tu #define CLKID_FCLK_DIV4_DIV 6 17*923a77a2SYu Tu #define CLKID_FCLK_DIV4 7 18*923a77a2SYu Tu #define CLKID_FCLK_DIV5_DIV 8 19*923a77a2SYu Tu #define CLKID_FCLK_DIV5 9 20*923a77a2SYu Tu #define CLKID_FCLK_DIV7_DIV 10 21*923a77a2SYu Tu #define CLKID_FCLK_DIV7 11 22*923a77a2SYu Tu #define CLKID_FCLK_DIV2P5_DIV 12 23*923a77a2SYu Tu #define CLKID_FCLK_DIV2P5 13 24*923a77a2SYu Tu #define CLKID_GP0_PLL_DCO 14 25*923a77a2SYu Tu #define CLKID_GP0_PLL 15 26*923a77a2SYu Tu #define CLKID_HIFI_PLL_DCO 16 27*923a77a2SYu Tu #define CLKID_HIFI_PLL 17 28*923a77a2SYu Tu #define CLKID_HDMI_PLL_DCO 18 29*923a77a2SYu Tu #define CLKID_HDMI_PLL_OD 19 30*923a77a2SYu Tu #define CLKID_HDMI_PLL 20 31*923a77a2SYu Tu #define CLKID_MPLL_50M_DIV 21 32*923a77a2SYu Tu #define CLKID_MPLL_50M 22 33*923a77a2SYu Tu #define CLKID_MPLL_PREDIV 23 34*923a77a2SYu Tu #define CLKID_MPLL0_DIV 24 35*923a77a2SYu Tu #define CLKID_MPLL0 25 36*923a77a2SYu Tu #define CLKID_MPLL1_DIV 26 37*923a77a2SYu Tu #define CLKID_MPLL1 27 38*923a77a2SYu Tu #define CLKID_MPLL2_DIV 28 39*923a77a2SYu Tu #define CLKID_MPLL2 29 40*923a77a2SYu Tu #define CLKID_MPLL3_DIV 30 41*923a77a2SYu Tu #define CLKID_MPLL3 31 42*923a77a2SYu Tu 43*923a77a2SYu Tu #endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H */ 44