xref: /linux/scripts/dtc/include-prefixes/dt-bindings/clock/amlogic,a9-aoclkc.h (revision 502d45774af09f1c681c754c4b7cdfb5d7f72fd9)
1*d4255960SJian Hu /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2*d4255960SJian Hu /*
3*d4255960SJian Hu  * Copyright (C) 2026 Amlogic, Inc. All rights reserved.
4*d4255960SJian Hu  */
5*d4255960SJian Hu 
6*d4255960SJian Hu #ifndef __AMLOGIC_A9_AO_CLKC_H
7*d4255960SJian Hu #define __AMLOGIC_A9_AO_CLKC_H
8*d4255960SJian Hu 
9*d4255960SJian Hu #define CLKID_AO_XTAL_IN			0
10*d4255960SJian Hu #define CLKID_AO_XTAL				1
11*d4255960SJian Hu #define CLKID_AO_SYS				2
12*d4255960SJian Hu #define CLKID_AO_SYS_I3C			3
13*d4255960SJian Hu #define CLKID_AO_SYS_RTC_REG			4
14*d4255960SJian Hu #define CLKID_AO_SYS_CLKTREE			5
15*d4255960SJian Hu #define CLKID_AO_SYS_RST_CTRL			6
16*d4255960SJian Hu #define CLKID_AO_SYS_PAD			7
17*d4255960SJian Hu #define CLKID_AO_SYS_RTC_DIG			8
18*d4255960SJian Hu #define CLKID_AO_SYS_IRQ			9
19*d4255960SJian Hu #define CLKID_AO_SYS_PWRCTRL			10
20*d4255960SJian Hu #define CLKID_AO_SYS_PWM_A			11
21*d4255960SJian Hu #define CLKID_AO_SYS_PWM_B			12
22*d4255960SJian Hu #define CLKID_AO_SYS_PWM_C			13
23*d4255960SJian Hu #define CLKID_AO_SYS_PWM_D			14
24*d4255960SJian Hu #define CLKID_AO_SYS_PWM_E			15
25*d4255960SJian Hu #define CLKID_AO_SYS_PWM_F			16
26*d4255960SJian Hu #define CLKID_AO_SYS_PWM_G			17
27*d4255960SJian Hu #define CLKID_AO_SYS_I2C_A			18
28*d4255960SJian Hu #define CLKID_AO_SYS_I2C_B			19
29*d4255960SJian Hu #define CLKID_AO_SYS_I2C_C			20
30*d4255960SJian Hu #define CLKID_AO_SYS_I2C_D			21
31*d4255960SJian Hu #define CLKID_AO_SYS_SED			22
32*d4255960SJian Hu #define CLKID_AO_SYS_IR_CTRL			23
33*d4255960SJian Hu #define CLKID_AO_SYS_UART_B			24
34*d4255960SJian Hu #define CLKID_AO_SYS_UART_C			25
35*d4255960SJian Hu #define CLKID_AO_SYS_UART_D			26
36*d4255960SJian Hu #define CLKID_AO_SYS_UART_E			27
37*d4255960SJian Hu #define CLKID_AO_SYS_SPISG_0			28
38*d4255960SJian Hu #define CLKID_AO_SYS_RTC_SECURE			29
39*d4255960SJian Hu #define CLKID_AO_SYS_CEC			30
40*d4255960SJian Hu #define CLKID_AO_SYS_AOCPU			31
41*d4255960SJian Hu #define CLKID_AO_SYS_SRAM			32
42*d4255960SJian Hu #define CLKID_AO_SYS_SPISG_1			33
43*d4255960SJian Hu #define CLKID_AO_SYS_SPISG_2			34
44*d4255960SJian Hu #define CLKID_AO_PWM_A_SEL			35
45*d4255960SJian Hu #define CLKID_AO_PWM_A_DIV			36
46*d4255960SJian Hu #define CLKID_AO_PWM_A				37
47*d4255960SJian Hu #define CLKID_AO_PWM_B_SEL			38
48*d4255960SJian Hu #define CLKID_AO_PWM_B_DIV			39
49*d4255960SJian Hu #define CLKID_AO_PWM_B				40
50*d4255960SJian Hu #define CLKID_AO_PWM_C_SEL			41
51*d4255960SJian Hu #define CLKID_AO_PWM_C_DIV			42
52*d4255960SJian Hu #define CLKID_AO_PWM_C				43
53*d4255960SJian Hu #define CLKID_AO_PWM_D_SEL			44
54*d4255960SJian Hu #define CLKID_AO_PWM_D_DIV			45
55*d4255960SJian Hu #define CLKID_AO_PWM_D				46
56*d4255960SJian Hu #define CLKID_AO_PWM_E_SEL			47
57*d4255960SJian Hu #define CLKID_AO_PWM_E_DIV			48
58*d4255960SJian Hu #define CLKID_AO_PWM_E				49
59*d4255960SJian Hu #define CLKID_AO_PWM_F_SEL			50
60*d4255960SJian Hu #define CLKID_AO_PWM_F_DIV			51
61*d4255960SJian Hu #define CLKID_AO_PWM_F				52
62*d4255960SJian Hu #define CLKID_AO_PWM_G_SEL			53
63*d4255960SJian Hu #define CLKID_AO_PWM_G_DIV			54
64*d4255960SJian Hu #define CLKID_AO_PWM_G				55
65*d4255960SJian Hu #define CLKID_AO_RTC_DUALDIV_IN			56
66*d4255960SJian Hu #define CLKID_AO_RTC_DUALDIV_DIV		57
67*d4255960SJian Hu #define CLKID_AO_RTC_DUALDIV_SEL		58
68*d4255960SJian Hu #define CLKID_AO_RTC_DUALDIV			59
69*d4255960SJian Hu #define CLKID_AO_RTC				60
70*d4255960SJian Hu #define CLKID_AO_CEC_DUALDIV_IN			61
71*d4255960SJian Hu #define CLKID_AO_CEC_DUALDIV_DIV		62
72*d4255960SJian Hu #define CLKID_AO_CEC_DUALDIV_SEL		63
73*d4255960SJian Hu #define CLKID_AO_CEC_DUALDIV			64
74*d4255960SJian Hu #define CLKID_AO_CEC				65
75*d4255960SJian Hu 
76*d4255960SJian Hu #endif  /* __AMLOGIC_A9_AO_CLKC_H */
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