1ef797b53SMichal Simek// SPDX-License-Identifier: GPL-2.0+ 2ef797b53SMichal Simek/* 3ef797b53SMichal Simek * dts file for Xilinx ZynqMP ZCU102 Rev1.0 4ef797b53SMichal Simek * 5ef797b53SMichal Simek * (C) Copyright 2016 - 2018, Xilinx, Inc. 6ef797b53SMichal Simek * 74e4ddd3dSMichal Simek * Michal Simek <michal.simek@amd.com> 8ef797b53SMichal Simek */ 9ef797b53SMichal Simek 10ef797b53SMichal Simek#include "zynqmp-zcu102-revB.dts" 11ef797b53SMichal Simek 12ef797b53SMichal Simek/ { 13ef797b53SMichal Simek model = "ZynqMP ZCU102 Rev1.0"; 14ef797b53SMichal Simek compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; 15ef797b53SMichal Simek}; 16ef797b53SMichal Simek 17*e31de4edSTanmay Shah&rproc_split { 18*e31de4edSTanmay Shah status = "okay"; 19*e31de4edSTanmay Shah}; 20*e31de4edSTanmay Shah 21*e31de4edSTanmay Shah&rproc_lockstep { 22*e31de4edSTanmay Shah status = "disabled"; 23*e31de4edSTanmay Shah}; 24*e31de4edSTanmay Shah 25ef797b53SMichal Simek&eeprom { 26ef797b53SMichal Simek #address-cells = <1>; 27ef797b53SMichal Simek #size-cells = <1>; 28ef797b53SMichal Simek 29ef797b53SMichal Simek board_sn: board-sn@0 { 30ef797b53SMichal Simek reg = <0x0 0x14>; 31ef797b53SMichal Simek }; 32ef797b53SMichal Simek 33ef797b53SMichal Simek eth_mac: eth-mac@20 { 34ef797b53SMichal Simek reg = <0x20 0x6>; 35ef797b53SMichal Simek }; 36ef797b53SMichal Simek 37ef797b53SMichal Simek board_name: board-name@d0 { 38ef797b53SMichal Simek reg = <0xd0 0x6>; 39ef797b53SMichal Simek }; 40ef797b53SMichal Simek 41ef797b53SMichal Simek board_revision: board-revision@e0 { 42ef797b53SMichal Simek reg = <0xe0 0x3>; 43ef797b53SMichal Simek }; 44ef797b53SMichal Simek}; 45