1d665c743SMichal Simek// SPDX-License-Identifier: GPL-2.0+ 2d665c743SMichal Simek/* 3d665c743SMichal Simek * dts file for Xilinx ZynqMP ZC1254 4d665c743SMichal Simek * 556e54601SMichal Simek * (C) Copyright 2015 - 2021, Xilinx, Inc. 6d665c743SMichal Simek * 74e4ddd3dSMichal Simek * Michal Simek <michal.simek@amd.com> 84e4ddd3dSMichal Simek * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> 9d665c743SMichal Simek */ 10d665c743SMichal Simek 11d665c743SMichal Simek/dts-v1/; 12d665c743SMichal Simek 13d665c743SMichal Simek#include "zynqmp.dtsi" 149c8a47b4SRajan Vaja#include "zynqmp-clk-ccf.dtsi" 15d665c743SMichal Simek 16d665c743SMichal Simek/ { 17d665c743SMichal Simek model = "ZynqMP ZC1254 RevA"; 18d665c743SMichal Simek compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; 19d665c743SMichal Simek 20d665c743SMichal Simek aliases { 21d665c743SMichal Simek serial0 = &uart0; 22d665c743SMichal Simek serial1 = &dcc; 2356e54601SMichal Simek spi0 = &qspi; 24d665c743SMichal Simek }; 25d665c743SMichal Simek 26d665c743SMichal Simek chosen { 27d665c743SMichal Simek bootargs = "earlycon"; 28d665c743SMichal Simek stdout-path = "serial0:115200n8"; 29d665c743SMichal Simek }; 30d665c743SMichal Simek 31d665c743SMichal Simek memory@0 { 32d665c743SMichal Simek device_type = "memory"; 33d665c743SMichal Simek reg = <0x0 0x0 0x0 0x80000000>; 34d665c743SMichal Simek }; 35d665c743SMichal Simek}; 36d665c743SMichal Simek 37d665c743SMichal Simek&dcc { 38d665c743SMichal Simek status = "okay"; 39d665c743SMichal Simek}; 40d665c743SMichal Simek 4156e54601SMichal Simek&qspi { 4256e54601SMichal Simek status = "okay"; 4356e54601SMichal Simek flash@0 { 4456e54601SMichal Simek compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ 4556e54601SMichal Simek #address-cells = <1>; 4656e54601SMichal Simek #size-cells = <1>; 4756e54601SMichal Simek reg = <0x0>; 48*1d831cadSAmit Kumar Mahapatra spi-tx-bus-width = <4>; 4956e54601SMichal Simek spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ 5056e54601SMichal Simek spi-max-frequency = <108000000>; /* Based on DC1 spec */ 5156e54601SMichal Simek }; 5256e54601SMichal Simek}; 5356e54601SMichal Simek 54d665c743SMichal Simek&uart0 { 55d665c743SMichal Simek status = "okay"; 56d665c743SMichal Simek}; 57