1*01a86031SMichal Simek /* SPDX-License-Identifier: GPL-2.0 */ 2*01a86031SMichal Simek /* 3*01a86031SMichal Simek * Xilinx Zynq MPSoC Firmware layer 4*01a86031SMichal Simek * 5*01a86031SMichal Simek * Copyright (C) 2014-2018 Xilinx, Inc. 6*01a86031SMichal Simek * 7*01a86031SMichal Simek */ 8*01a86031SMichal Simek 9*01a86031SMichal Simek #ifndef _XLNX_ZYNQMP_CLK_H 10*01a86031SMichal Simek #define _XLNX_ZYNQMP_CLK_H 11*01a86031SMichal Simek 12*01a86031SMichal Simek #define IOPLL 0 13*01a86031SMichal Simek #define RPLL 1 14*01a86031SMichal Simek #define APLL 2 15*01a86031SMichal Simek #define DPLL 3 16*01a86031SMichal Simek #define VPLL 4 17*01a86031SMichal Simek #define IOPLL_TO_FPD 5 18*01a86031SMichal Simek #define RPLL_TO_FPD 6 19*01a86031SMichal Simek #define APLL_TO_LPD 7 20*01a86031SMichal Simek #define DPLL_TO_LPD 8 21*01a86031SMichal Simek #define VPLL_TO_LPD 9 22*01a86031SMichal Simek #define ACPU 10 23*01a86031SMichal Simek #define ACPU_HALF 11 24*01a86031SMichal Simek #define DBF_FPD 12 25*01a86031SMichal Simek #define DBF_LPD 13 26*01a86031SMichal Simek #define DBG_TRACE 14 27*01a86031SMichal Simek #define DBG_TSTMP 15 28*01a86031SMichal Simek #define DP_VIDEO_REF 16 29*01a86031SMichal Simek #define DP_AUDIO_REF 17 30*01a86031SMichal Simek #define DP_STC_REF 18 31*01a86031SMichal Simek #define GDMA_REF 19 32*01a86031SMichal Simek #define DPDMA_REF 20 33*01a86031SMichal Simek #define DDR_REF 21 34*01a86031SMichal Simek #define SATA_REF 22 35*01a86031SMichal Simek #define PCIE_REF 23 36*01a86031SMichal Simek #define GPU_REF 24 37*01a86031SMichal Simek #define GPU_PP0_REF 25 38*01a86031SMichal Simek #define GPU_PP1_REF 26 39*01a86031SMichal Simek #define TOPSW_MAIN 27 40*01a86031SMichal Simek #define TOPSW_LSBUS 28 41*01a86031SMichal Simek #define GTGREF0_REF 29 42*01a86031SMichal Simek #define LPD_SWITCH 30 43*01a86031SMichal Simek #define LPD_LSBUS 31 44*01a86031SMichal Simek #define USB0_BUS_REF 32 45*01a86031SMichal Simek #define USB1_BUS_REF 33 46*01a86031SMichal Simek #define USB3_DUAL_REF 34 47*01a86031SMichal Simek #define USB0 35 48*01a86031SMichal Simek #define USB1 36 49*01a86031SMichal Simek #define CPU_R5 37 50*01a86031SMichal Simek #define CPU_R5_CORE 38 51*01a86031SMichal Simek #define CSU_SPB 39 52*01a86031SMichal Simek #define CSU_PLL 40 53*01a86031SMichal Simek #define PCAP 41 54*01a86031SMichal Simek #define IOU_SWITCH 42 55*01a86031SMichal Simek #define GEM_TSU_REF 43 56*01a86031SMichal Simek #define GEM_TSU 44 57*01a86031SMichal Simek #define GEM0_TX 45 58*01a86031SMichal Simek #define GEM1_TX 46 59*01a86031SMichal Simek #define GEM2_TX 47 60*01a86031SMichal Simek #define GEM3_TX 48 61*01a86031SMichal Simek #define GEM0_RX 49 62*01a86031SMichal Simek #define GEM1_RX 50 63*01a86031SMichal Simek #define GEM2_RX 51 64*01a86031SMichal Simek #define GEM3_RX 52 65*01a86031SMichal Simek #define QSPI_REF 53 66*01a86031SMichal Simek #define SDIO0_REF 54 67*01a86031SMichal Simek #define SDIO1_REF 55 68*01a86031SMichal Simek #define UART0_REF 56 69*01a86031SMichal Simek #define UART1_REF 57 70*01a86031SMichal Simek #define SPI0_REF 58 71*01a86031SMichal Simek #define SPI1_REF 59 72*01a86031SMichal Simek #define NAND_REF 60 73*01a86031SMichal Simek #define I2C0_REF 61 74*01a86031SMichal Simek #define I2C1_REF 62 75*01a86031SMichal Simek #define CAN0_REF 63 76*01a86031SMichal Simek #define CAN1_REF 64 77*01a86031SMichal Simek #define CAN0 65 78*01a86031SMichal Simek #define CAN1 66 79*01a86031SMichal Simek #define DLL_REF 67 80*01a86031SMichal Simek #define ADMA_REF 68 81*01a86031SMichal Simek #define TIMESTAMP_REF 69 82*01a86031SMichal Simek #define AMS_REF 70 83*01a86031SMichal Simek #define PL0_REF 71 84*01a86031SMichal Simek #define PL1_REF 72 85*01a86031SMichal Simek #define PL2_REF 73 86*01a86031SMichal Simek #define PL3_REF 74 87*01a86031SMichal Simek #define WDT 75 88*01a86031SMichal Simek #define IOPLL_INT 76 89*01a86031SMichal Simek #define IOPLL_PRE_SRC 77 90*01a86031SMichal Simek #define IOPLL_HALF 78 91*01a86031SMichal Simek #define IOPLL_INT_MUX 79 92*01a86031SMichal Simek #define IOPLL_POST_SRC 80 93*01a86031SMichal Simek #define RPLL_INT 81 94*01a86031SMichal Simek #define RPLL_PRE_SRC 82 95*01a86031SMichal Simek #define RPLL_HALF 83 96*01a86031SMichal Simek #define RPLL_INT_MUX 84 97*01a86031SMichal Simek #define RPLL_POST_SRC 85 98*01a86031SMichal Simek #define APLL_INT 86 99*01a86031SMichal Simek #define APLL_PRE_SRC 87 100*01a86031SMichal Simek #define APLL_HALF 88 101*01a86031SMichal Simek #define APLL_INT_MUX 89 102*01a86031SMichal Simek #define APLL_POST_SRC 90 103*01a86031SMichal Simek #define DPLL_INT 91 104*01a86031SMichal Simek #define DPLL_PRE_SRC 92 105*01a86031SMichal Simek #define DPLL_HALF 93 106*01a86031SMichal Simek #define DPLL_INT_MUX 94 107*01a86031SMichal Simek #define DPLL_POST_SRC 95 108*01a86031SMichal Simek #define VPLL_INT 96 109*01a86031SMichal Simek #define VPLL_PRE_SRC 97 110*01a86031SMichal Simek #define VPLL_HALF 98 111*01a86031SMichal Simek #define VPLL_INT_MUX 99 112*01a86031SMichal Simek #define VPLL_POST_SRC 100 113*01a86031SMichal Simek #define CAN0_MIO 101 114*01a86031SMichal Simek #define CAN1_MIO 102 115*01a86031SMichal Simek #define ACPU_FULL 103 116*01a86031SMichal Simek #define GEM0_REF 104 117*01a86031SMichal Simek #define GEM1_REF 105 118*01a86031SMichal Simek #define GEM2_REF 106 119*01a86031SMichal Simek #define GEM3_REF 107 120*01a86031SMichal Simek #define GEM0_REF_UNG 108 121*01a86031SMichal Simek #define GEM1_REF_UNG 109 122*01a86031SMichal Simek #define GEM2_REF_UNG 110 123*01a86031SMichal Simek #define GEM3_REF_UNG 111 124*01a86031SMichal Simek #define LPD_WDT 112 125*01a86031SMichal Simek 126*01a86031SMichal Simek #endif /* _XLNX_ZYNQMP_CLK_H */ 127