1*e1ab33a3SMichal Simek /* SPDX-License-Identifier: GPL-2.0 */ 2*e1ab33a3SMichal Simek /* 3*e1ab33a3SMichal Simek * Copyright (C) 2020 - 2022, Xilinx, Inc. 4*e1ab33a3SMichal Simek * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. 5*e1ab33a3SMichal Simek */ 6*e1ab33a3SMichal Simek 7*e1ab33a3SMichal Simek #ifndef _XLNX_VERSAL_RESETS_H 8*e1ab33a3SMichal Simek #define _XLNX_VERSAL_RESETS_H 9*e1ab33a3SMichal Simek 10*e1ab33a3SMichal Simek #define VERSAL_RST_PMC_POR (0xc30c001U) 11*e1ab33a3SMichal Simek #define VERSAL_RST_PMC (0xc410002U) 12*e1ab33a3SMichal Simek #define VERSAL_RST_PS_POR (0xc30c003U) 13*e1ab33a3SMichal Simek #define VERSAL_RST_PL_POR (0xc30c004U) 14*e1ab33a3SMichal Simek #define VERSAL_RST_NOC_POR (0xc30c005U) 15*e1ab33a3SMichal Simek #define VERSAL_RST_FPD_POR (0xc30c006U) 16*e1ab33a3SMichal Simek #define VERSAL_RST_ACPU_0_POR (0xc30c007U) 17*e1ab33a3SMichal Simek #define VERSAL_RST_ACPU_1_POR (0xc30c008U) 18*e1ab33a3SMichal Simek #define VERSAL_RST_OCM2_POR (0xc30c009U) 19*e1ab33a3SMichal Simek #define VERSAL_RST_PS_SRST (0xc41000aU) 20*e1ab33a3SMichal Simek #define VERSAL_RST_PL_SRST (0xc41000bU) 21*e1ab33a3SMichal Simek #define VERSAL_RST_NOC (0xc41000cU) 22*e1ab33a3SMichal Simek #define VERSAL_RST_NPI (0xc41000dU) 23*e1ab33a3SMichal Simek #define VERSAL_RST_SYS_RST_1 (0xc41000eU) 24*e1ab33a3SMichal Simek #define VERSAL_RST_SYS_RST_2 (0xc41000fU) 25*e1ab33a3SMichal Simek #define VERSAL_RST_SYS_RST_3 (0xc410010U) 26*e1ab33a3SMichal Simek #define VERSAL_RST_FPD (0xc410011U) 27*e1ab33a3SMichal Simek #define VERSAL_RST_PL0 (0xc410012U) 28*e1ab33a3SMichal Simek #define VERSAL_RST_PL1 (0xc410013U) 29*e1ab33a3SMichal Simek #define VERSAL_RST_PL2 (0xc410014U) 30*e1ab33a3SMichal Simek #define VERSAL_RST_PL3 (0xc410015U) 31*e1ab33a3SMichal Simek #define VERSAL_RST_APU (0xc410016U) 32*e1ab33a3SMichal Simek #define VERSAL_RST_ACPU_0 (0xc410017U) 33*e1ab33a3SMichal Simek #define VERSAL_RST_ACPU_1 (0xc410018U) 34*e1ab33a3SMichal Simek #define VERSAL_RST_ACPU_L2 (0xc410019U) 35*e1ab33a3SMichal Simek #define VERSAL_RST_ACPU_GIC (0xc41001aU) 36*e1ab33a3SMichal Simek #define VERSAL_RST_RPU_ISLAND (0xc41001bU) 37*e1ab33a3SMichal Simek #define VERSAL_RST_RPU_AMBA (0xc41001cU) 38*e1ab33a3SMichal Simek #define VERSAL_RST_R5_0 (0xc41001dU) 39*e1ab33a3SMichal Simek #define VERSAL_RST_R5_1 (0xc41001eU) 40*e1ab33a3SMichal Simek #define VERSAL_RST_SYSMON_PMC_SEQ_RST (0xc41001fU) 41*e1ab33a3SMichal Simek #define VERSAL_RST_SYSMON_PMC_CFG_RST (0xc410020U) 42*e1ab33a3SMichal Simek #define VERSAL_RST_SYSMON_FPD_CFG_RST (0xc410021U) 43*e1ab33a3SMichal Simek #define VERSAL_RST_SYSMON_FPD_SEQ_RST (0xc410022U) 44*e1ab33a3SMichal Simek #define VERSAL_RST_SYSMON_LPD (0xc410023U) 45*e1ab33a3SMichal Simek #define VERSAL_RST_PDMA_RST1 (0xc410024U) 46*e1ab33a3SMichal Simek #define VERSAL_RST_PDMA_RST0 (0xc410025U) 47*e1ab33a3SMichal Simek #define VERSAL_RST_ADMA (0xc410026U) 48*e1ab33a3SMichal Simek #define VERSAL_RST_TIMESTAMP (0xc410027U) 49*e1ab33a3SMichal Simek #define VERSAL_RST_OCM (0xc410028U) 50*e1ab33a3SMichal Simek #define VERSAL_RST_OCM2_RST (0xc410029U) 51*e1ab33a3SMichal Simek #define VERSAL_RST_IPI (0xc41002aU) 52*e1ab33a3SMichal Simek #define VERSAL_RST_SBI (0xc41002bU) 53*e1ab33a3SMichal Simek #define VERSAL_RST_LPD (0xc41002cU) 54*e1ab33a3SMichal Simek #define VERSAL_RST_QSPI (0xc10402dU) 55*e1ab33a3SMichal Simek #define VERSAL_RST_OSPI (0xc10402eU) 56*e1ab33a3SMichal Simek #define VERSAL_RST_SDIO_0 (0xc10402fU) 57*e1ab33a3SMichal Simek #define VERSAL_RST_SDIO_1 (0xc104030U) 58*e1ab33a3SMichal Simek #define VERSAL_RST_I2C_PMC (0xc104031U) 59*e1ab33a3SMichal Simek #define VERSAL_RST_GPIO_PMC (0xc104032U) 60*e1ab33a3SMichal Simek #define VERSAL_RST_GEM_0 (0xc104033U) 61*e1ab33a3SMichal Simek #define VERSAL_RST_GEM_1 (0xc104034U) 62*e1ab33a3SMichal Simek #define VERSAL_RST_SPARE (0xc104035U) 63*e1ab33a3SMichal Simek #define VERSAL_RST_USB_0 (0xc104036U) 64*e1ab33a3SMichal Simek #define VERSAL_RST_UART_0 (0xc104037U) 65*e1ab33a3SMichal Simek #define VERSAL_RST_UART_1 (0xc104038U) 66*e1ab33a3SMichal Simek #define VERSAL_RST_SPI_0 (0xc104039U) 67*e1ab33a3SMichal Simek #define VERSAL_RST_SPI_1 (0xc10403aU) 68*e1ab33a3SMichal Simek #define VERSAL_RST_CAN_FD_0 (0xc10403bU) 69*e1ab33a3SMichal Simek #define VERSAL_RST_CAN_FD_1 (0xc10403cU) 70*e1ab33a3SMichal Simek #define VERSAL_RST_I2C_0 (0xc10403dU) 71*e1ab33a3SMichal Simek #define VERSAL_RST_I2C_1 (0xc10403eU) 72*e1ab33a3SMichal Simek #define VERSAL_RST_GPIO_LPD (0xc10403fU) 73*e1ab33a3SMichal Simek #define VERSAL_RST_TTC_0 (0xc104040U) 74*e1ab33a3SMichal Simek #define VERSAL_RST_TTC_1 (0xc104041U) 75*e1ab33a3SMichal Simek #define VERSAL_RST_TTC_2 (0xc104042U) 76*e1ab33a3SMichal Simek #define VERSAL_RST_TTC_3 (0xc104043U) 77*e1ab33a3SMichal Simek #define VERSAL_RST_SWDT_FPD (0xc104044U) 78*e1ab33a3SMichal Simek #define VERSAL_RST_SWDT_LPD (0xc104045U) 79*e1ab33a3SMichal Simek #define VERSAL_RST_USB (0xc104046U) 80*e1ab33a3SMichal Simek #define VERSAL_RST_DPC (0xc208047U) 81*e1ab33a3SMichal Simek #define VERSAL_RST_PMCDBG (0xc208048U) 82*e1ab33a3SMichal Simek #define VERSAL_RST_DBG_TRACE (0xc208049U) 83*e1ab33a3SMichal Simek #define VERSAL_RST_DBG_FPD (0xc20804aU) 84*e1ab33a3SMichal Simek #define VERSAL_RST_DBG_TSTMP (0xc20804bU) 85*e1ab33a3SMichal Simek #define VERSAL_RST_RPU0_DBG (0xc20804cU) 86*e1ab33a3SMichal Simek #define VERSAL_RST_RPU1_DBG (0xc20804dU) 87*e1ab33a3SMichal Simek #define VERSAL_RST_HSDP (0xc20804eU) 88*e1ab33a3SMichal Simek #define VERSAL_RST_DBG_LPD (0xc20804fU) 89*e1ab33a3SMichal Simek #define VERSAL_RST_CPM_POR (0xc30c050U) 90*e1ab33a3SMichal Simek #define VERSAL_RST_CPM (0xc410051U) 91*e1ab33a3SMichal Simek #define VERSAL_RST_CPMDBG (0xc208052U) 92*e1ab33a3SMichal Simek #define VERSAL_RST_PCIE_CFG (0xc410053U) 93*e1ab33a3SMichal Simek #define VERSAL_RST_PCIE_CORE0 (0xc410054U) 94*e1ab33a3SMichal Simek #define VERSAL_RST_PCIE_CORE1 (0xc410055U) 95*e1ab33a3SMichal Simek #define VERSAL_RST_PCIE_DMA (0xc410056U) 96*e1ab33a3SMichal Simek #define VERSAL_RST_CMN (0xc410057U) 97*e1ab33a3SMichal Simek #define VERSAL_RST_L2_0 (0xc410058U) 98*e1ab33a3SMichal Simek #define VERSAL_RST_L2_1 (0xc410059U) 99*e1ab33a3SMichal Simek #define VERSAL_RST_ADDR_REMAP (0xc41005aU) 100*e1ab33a3SMichal Simek #define VERSAL_RST_CPI0 (0xc41005bU) 101*e1ab33a3SMichal Simek #define VERSAL_RST_CPI1 (0xc41005cU) 102*e1ab33a3SMichal Simek #define VERSAL_RST_XRAM (0xc30c05dU) 103*e1ab33a3SMichal Simek #define VERSAL_RST_AIE_ARRAY (0xc10405eU) 104*e1ab33a3SMichal Simek #define VERSAL_RST_AIE_SHIM (0xc10405fU) 105*e1ab33a3SMichal Simek 106*e1ab33a3SMichal Simek #endif 107