1*e1ab33a3SMichal Simek /* SPDX-License-Identifier: GPL-2.0 */ 2*e1ab33a3SMichal Simek /* 3*e1ab33a3SMichal Simek * Copyright (C) 2019 - 2022, Xilinx, Inc. 4*e1ab33a3SMichal Simek * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. 5*e1ab33a3SMichal Simek */ 6*e1ab33a3SMichal Simek 7*e1ab33a3SMichal Simek #ifndef _XLNX_VERSAL_POWER_H 8*e1ab33a3SMichal Simek #define _XLNX_VERSAL_POWER_H 9*e1ab33a3SMichal Simek 10*e1ab33a3SMichal Simek #define PM_DEV_RPU0_0 (0x18110005U) 11*e1ab33a3SMichal Simek #define PM_DEV_RPU0_1 (0x18110006U) 12*e1ab33a3SMichal Simek #define PM_DEV_OCM_0 (0x18314007U) 13*e1ab33a3SMichal Simek #define PM_DEV_OCM_1 (0x18314008U) 14*e1ab33a3SMichal Simek #define PM_DEV_OCM_2 (0x18314009U) 15*e1ab33a3SMichal Simek #define PM_DEV_OCM_3 (0x1831400aU) 16*e1ab33a3SMichal Simek #define PM_DEV_TCM_0_A (0x1831800bU) 17*e1ab33a3SMichal Simek #define PM_DEV_TCM_0_B (0x1831800cU) 18*e1ab33a3SMichal Simek #define PM_DEV_TCM_1_A (0x1831800dU) 19*e1ab33a3SMichal Simek #define PM_DEV_TCM_1_B (0x1831800eU) 20*e1ab33a3SMichal Simek #define PM_DEV_USB_0 (0x18224018U) 21*e1ab33a3SMichal Simek #define PM_DEV_GEM_0 (0x18224019U) 22*e1ab33a3SMichal Simek #define PM_DEV_GEM_1 (0x1822401aU) 23*e1ab33a3SMichal Simek #define PM_DEV_SPI_0 (0x1822401bU) 24*e1ab33a3SMichal Simek #define PM_DEV_SPI_1 (0x1822401cU) 25*e1ab33a3SMichal Simek #define PM_DEV_I2C_0 (0x1822401dU) 26*e1ab33a3SMichal Simek #define PM_DEV_I2C_1 (0x1822401eU) 27*e1ab33a3SMichal Simek #define PM_DEV_CAN_FD_0 (0x1822401fU) 28*e1ab33a3SMichal Simek #define PM_DEV_CAN_FD_1 (0x18224020U) 29*e1ab33a3SMichal Simek #define PM_DEV_UART_0 (0x18224021U) 30*e1ab33a3SMichal Simek #define PM_DEV_UART_1 (0x18224022U) 31*e1ab33a3SMichal Simek #define PM_DEV_GPIO (0x18224023U) 32*e1ab33a3SMichal Simek #define PM_DEV_TTC_0 (0x18224024U) 33*e1ab33a3SMichal Simek #define PM_DEV_TTC_1 (0x18224025U) 34*e1ab33a3SMichal Simek #define PM_DEV_TTC_2 (0x18224026U) 35*e1ab33a3SMichal Simek #define PM_DEV_TTC_3 (0x18224027U) 36*e1ab33a3SMichal Simek #define PM_DEV_SWDT_LPD (0x18224028U) 37*e1ab33a3SMichal Simek #define PM_DEV_SWDT_FPD (0x18224029U) 38*e1ab33a3SMichal Simek #define PM_DEV_OSPI (0x1822402aU) 39*e1ab33a3SMichal Simek #define PM_DEV_QSPI (0x1822402bU) 40*e1ab33a3SMichal Simek #define PM_DEV_GPIO_PMC (0x1822402cU) 41*e1ab33a3SMichal Simek #define PM_DEV_I2C_PMC (0x1822402dU) 42*e1ab33a3SMichal Simek #define PM_DEV_SDIO_0 (0x1822402eU) 43*e1ab33a3SMichal Simek #define PM_DEV_SDIO_1 (0x1822402fU) 44*e1ab33a3SMichal Simek #define PM_DEV_RTC (0x18224034U) 45*e1ab33a3SMichal Simek #define PM_DEV_ADMA_0 (0x18224035U) 46*e1ab33a3SMichal Simek #define PM_DEV_ADMA_1 (0x18224036U) 47*e1ab33a3SMichal Simek #define PM_DEV_ADMA_2 (0x18224037U) 48*e1ab33a3SMichal Simek #define PM_DEV_ADMA_3 (0x18224038U) 49*e1ab33a3SMichal Simek #define PM_DEV_ADMA_4 (0x18224039U) 50*e1ab33a3SMichal Simek #define PM_DEV_ADMA_5 (0x1822403aU) 51*e1ab33a3SMichal Simek #define PM_DEV_ADMA_6 (0x1822403bU) 52*e1ab33a3SMichal Simek #define PM_DEV_ADMA_7 (0x1822403cU) 53*e1ab33a3SMichal Simek #define PM_DEV_AI (0x18224072U) 54*e1ab33a3SMichal Simek 55*e1ab33a3SMichal Simek #endif 56