1*e1ab33a3SMichal Simek /* SPDX-License-Identifier: GPL-2.0 */ 2*e1ab33a3SMichal Simek /* 3*e1ab33a3SMichal Simek * Copyright (C) 2022, Xilinx, Inc. 4*e1ab33a3SMichal Simek * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. 5*e1ab33a3SMichal Simek */ 6*e1ab33a3SMichal Simek 7*e1ab33a3SMichal Simek #ifndef _XLNX_VERSAL_NET_POWER_H 8*e1ab33a3SMichal Simek #define _XLNX_VERSAL_NET_POWER_H 9*e1ab33a3SMichal Simek 10*e1ab33a3SMichal Simek #include "xlnx-versal-power.h" 11*e1ab33a3SMichal Simek 12*e1ab33a3SMichal Simek #define PM_DEV_USB_1 (0x182240d7U) 13*e1ab33a3SMichal Simek #define PM_DEV_FPD_SWDT_0 (0x182240dbU) 14*e1ab33a3SMichal Simek #define PM_DEV_FPD_SWDT_1 (0x182240dcU) 15*e1ab33a3SMichal Simek #define PM_DEV_FPD_SWDT_2 (0x182240ddU) 16*e1ab33a3SMichal Simek #define PM_DEV_FPD_SWDT_3 (0x182240deU) 17*e1ab33a3SMichal Simek #define PM_DEV_TCM_A_0A (0x183180cbU) 18*e1ab33a3SMichal Simek #define PM_DEV_TCM_A_0B (0x183180ccU) 19*e1ab33a3SMichal Simek #define PM_DEV_TCM_A_0C (0x183180cdU) 20*e1ab33a3SMichal Simek #define PM_DEV_RPU_A_0 (0x181100bfU) 21*e1ab33a3SMichal Simek #define PM_DEV_LPD_SWDT_0 (0x182240d9U) 22*e1ab33a3SMichal Simek #define PM_DEV_LPD_SWDT_1 (0x182240daU) 23*e1ab33a3SMichal Simek 24*e1ab33a3SMichal Simek /* Remove Versal specific node IDs */ 25*e1ab33a3SMichal Simek #undef PM_DEV_RPU0_0 26*e1ab33a3SMichal Simek #undef PM_DEV_RPU0_1 27*e1ab33a3SMichal Simek #undef PM_DEV_OCM_0 28*e1ab33a3SMichal Simek #undef PM_DEV_OCM_1 29*e1ab33a3SMichal Simek #undef PM_DEV_OCM_2 30*e1ab33a3SMichal Simek #undef PM_DEV_OCM_3 31*e1ab33a3SMichal Simek #undef PM_DEV_TCM_0_A 32*e1ab33a3SMichal Simek #undef PM_DEV_TCM_1_A 33*e1ab33a3SMichal Simek #undef PM_DEV_TCM_0_B 34*e1ab33a3SMichal Simek #undef PM_DEV_TCM_1_B 35*e1ab33a3SMichal Simek #undef PM_DEV_SWDT_FPD 36*e1ab33a3SMichal Simek #undef PM_DEV_AI 37*e1ab33a3SMichal Simek 38*e1ab33a3SMichal Simek #endif 39