1*e1ab33a3SMichal Simek /* SPDX-License-Identifier: GPL-2.0 */ 2*e1ab33a3SMichal Simek /* 3*e1ab33a3SMichal Simek * Copyright (C) 2022, Xilinx, Inc. 4*e1ab33a3SMichal Simek * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. 5*e1ab33a3SMichal Simek */ 6*e1ab33a3SMichal Simek 7*e1ab33a3SMichal Simek #ifndef _XLNX_VERSAL_NET_CLK_H 8*e1ab33a3SMichal Simek #define _XLNX_VERSAL_NET_CLK_H 9*e1ab33a3SMichal Simek 10*e1ab33a3SMichal Simek #include "xlnx-versal-clk.h" 11*e1ab33a3SMichal Simek 12*e1ab33a3SMichal Simek #define CAN0_REF_2X 0x9e 13*e1ab33a3SMichal Simek #define CAN1_REF_2X 0xac 14*e1ab33a3SMichal Simek #define FPD_WWDT0 0xb5 15*e1ab33a3SMichal Simek #define FPD_WWDT1 0xb6 16*e1ab33a3SMichal Simek #define FPD_WWDT2 0xb7 17*e1ab33a3SMichal Simek #define FPD_WWDT3 0xb8 18*e1ab33a3SMichal Simek #define LPD_WWDT0 0xb9 19*e1ab33a3SMichal Simek #define LPD_WWDT1 0xba 20*e1ab33a3SMichal Simek #define ACPU_0 0x98 21*e1ab33a3SMichal Simek #define ACPU_1 0x9b 22*e1ab33a3SMichal Simek #define ACPU_2 0x9a 23*e1ab33a3SMichal Simek #define ACPU_3 0x99 24*e1ab33a3SMichal Simek #define I3C0_REF 0x9d 25*e1ab33a3SMichal Simek #define I3C1_REF 0x9f 26*e1ab33a3SMichal Simek #define USB1_BUS_REF 0xae 27*e1ab33a3SMichal Simek #define LPD_WWDT 0xad 28*e1ab33a3SMichal Simek 29*e1ab33a3SMichal Simek /* Remove Versal specific node IDs */ 30*e1ab33a3SMichal Simek #undef APU_PLL 31*e1ab33a3SMichal Simek #undef RPU_PLL 32*e1ab33a3SMichal Simek #undef CPM_PLL 33*e1ab33a3SMichal Simek #undef APU_PRESRC 34*e1ab33a3SMichal Simek #undef APU_POSTCLK 35*e1ab33a3SMichal Simek #undef APU_PLL_OUT 36*e1ab33a3SMichal Simek #undef APLL 37*e1ab33a3SMichal Simek #undef RPU_PRESRC 38*e1ab33a3SMichal Simek #undef RPU_POSTCLK 39*e1ab33a3SMichal Simek #undef RPU_PLL_OUT 40*e1ab33a3SMichal Simek #undef RPLL 41*e1ab33a3SMichal Simek #undef CPM_PRESRC 42*e1ab33a3SMichal Simek #undef CPM_POSTCLK 43*e1ab33a3SMichal Simek #undef CPM_PLL_OUT 44*e1ab33a3SMichal Simek #undef CPLL 45*e1ab33a3SMichal Simek #undef APLL_TO_XPD 46*e1ab33a3SMichal Simek #undef RPLL_TO_XPD 47*e1ab33a3SMichal Simek #undef RCLK_PMC 48*e1ab33a3SMichal Simek #undef RCLK_LPD 49*e1ab33a3SMichal Simek #undef WDT 50*e1ab33a3SMichal Simek #undef MUXED_IRO_DIV2 51*e1ab33a3SMichal Simek #undef MUXED_IRO_DIV4 52*e1ab33a3SMichal Simek #undef PSM_REF 53*e1ab33a3SMichal Simek #undef CPM_CORE_REF 54*e1ab33a3SMichal Simek #undef CPM_LSBUS_REF 55*e1ab33a3SMichal Simek #undef CPM_DBG_REF 56*e1ab33a3SMichal Simek #undef CPM_AUX0_REF 57*e1ab33a3SMichal Simek #undef CPM_AUX1_REF 58*e1ab33a3SMichal Simek #undef CPU_R5 59*e1ab33a3SMichal Simek #undef CPU_R5_CORE 60*e1ab33a3SMichal Simek #undef CPU_R5_OCM 61*e1ab33a3SMichal Simek #undef CPU_R5_OCM2 62*e1ab33a3SMichal Simek #undef CAN0_REF 63*e1ab33a3SMichal Simek #undef CAN1_REF 64*e1ab33a3SMichal Simek #undef I2C0_REF 65*e1ab33a3SMichal Simek #undef I2C1_REF 66*e1ab33a3SMichal Simek #undef CPM_TOPSW_REF 67*e1ab33a3SMichal Simek #undef USB3_DUAL_REF 68*e1ab33a3SMichal Simek #undef MUXED_IRO 69*e1ab33a3SMichal Simek #undef PL_EXT 70*e1ab33a3SMichal Simek #undef PL_LB 71*e1ab33a3SMichal Simek #undef MIO_50_OR_51 72*e1ab33a3SMichal Simek #undef MIO_24_OR_25 73*e1ab33a3SMichal Simek 74*e1ab33a3SMichal Simek #endif 75