1*99adc529SMichal Simek// SPDX-License-Identifier: GPL-2.0 2*99adc529SMichal Simek/* 3*99adc529SMichal Simek * dts file for Xilinx Versal Net VNX board revA 4*99adc529SMichal Simek * 5*99adc529SMichal Simek * (C) Copyright 2022, Xilinx, Inc. 6*99adc529SMichal Simek * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc. 7*99adc529SMichal Simek * 8*99adc529SMichal Simek * Michal Simek <michal.simek@amd.com> 9*99adc529SMichal Simek */ 10*99adc529SMichal Simek 11*99adc529SMichal Simek/dts-v1/; 12*99adc529SMichal Simek 13*99adc529SMichal Simek#include "versal-net.dtsi" 14*99adc529SMichal Simek#include "versal-net-clk.dtsi" 15*99adc529SMichal Simek#include <dt-bindings/gpio/gpio.h> 16*99adc529SMichal Simek 17*99adc529SMichal Simek/ { 18*99adc529SMichal Simek compatible = "xlnx,versal-net-vnx-revA", "xlnx,versal-net-vnx", "xlnx,versal-net"; 19*99adc529SMichal Simek model = "Xilinx Versal NET VNX revA"; 20*99adc529SMichal Simek dma-coherent; 21*99adc529SMichal Simek 22*99adc529SMichal Simek memory: memory@0 { 23*99adc529SMichal Simek reg = <0 0 0 0x80000000>; 24*99adc529SMichal Simek device_type = "memory"; 25*99adc529SMichal Simek }; 26*99adc529SMichal Simek 27*99adc529SMichal Simek memory_hi: memory@800000000 { 28*99adc529SMichal Simek reg = <8 0 3 0x80000000>; 29*99adc529SMichal Simek device_type = "memory"; 30*99adc529SMichal Simek }; 31*99adc529SMichal Simek 32*99adc529SMichal Simek memory_hi2: memory@50000000000 { 33*99adc529SMichal Simek reg = <0x500 0 4 0>; 34*99adc529SMichal Simek device_type = "memory"; 35*99adc529SMichal Simek }; 36*99adc529SMichal Simek 37*99adc529SMichal Simek chosen { 38*99adc529SMichal Simek bootargs = "console=ttyAMA1,115200n8"; 39*99adc529SMichal Simek stdout-path = "serial1:115200n8"; 40*99adc529SMichal Simek }; 41*99adc529SMichal Simek 42*99adc529SMichal Simek reserved-memory { 43*99adc529SMichal Simek #address-cells = <2>; 44*99adc529SMichal Simek #size-cells = <2>; 45*99adc529SMichal Simek ranges; 46*99adc529SMichal Simek rsc_tbl_carveout: rproc@bbf14000 { 47*99adc529SMichal Simek reg = <0 0xbbf14000 0 0x1000>; 48*99adc529SMichal Simek no-map; 49*99adc529SMichal Simek }; 50*99adc529SMichal Simek rpu0vdev0vring0: rpu0vdev0vring0@bbf15000 { 51*99adc529SMichal Simek reg = <0 0xbbf15000 0 0x1000>; 52*99adc529SMichal Simek no-map; 53*99adc529SMichal Simek }; 54*99adc529SMichal Simek rpu0vdev0vring1: rpu0vdev0vring1@bbf16000 { 55*99adc529SMichal Simek reg = <0 0xbbf16000 0 0x1000>; 56*99adc529SMichal Simek no-map; 57*99adc529SMichal Simek }; 58*99adc529SMichal Simek rpu0vdev0buffer: rpu0vdev0buffer@bbf17000 { 59*99adc529SMichal Simek reg = <0 0xbbf17000 0 0xD000>; 60*99adc529SMichal Simek no-map; 61*99adc529SMichal Simek }; 62*99adc529SMichal Simek reserve_others: reserveothers@0 { 63*99adc529SMichal Simek reg = <0 0x0 0 0x1c200000>; 64*99adc529SMichal Simek no-map; 65*99adc529SMichal Simek }; 66*99adc529SMichal Simek pdi_update: pdiupdate@1c200000 { 67*99adc529SMichal Simek reg = <0 0x1c200000 0 0x6000000>; 68*99adc529SMichal Simek no-map; 69*99adc529SMichal Simek }; 70*99adc529SMichal Simek reserve_optee_atf: reserveopteeatf@22200000 { 71*99adc529SMichal Simek reg = <0 0x22200000 0 0x4100000>; 72*99adc529SMichal Simek no-map; 73*99adc529SMichal Simek }; 74*99adc529SMichal Simek }; 75*99adc529SMichal Simek}; 76*99adc529SMichal Simek 77*99adc529SMichal Simek&gem1 { 78*99adc529SMichal Simek status = "okay"; 79*99adc529SMichal Simek iommus = <&smmu 0x235>; 80*99adc529SMichal Simek phy-handle = <&phy>; 81*99adc529SMichal Simek phy-mode = "rmii"; 82*99adc529SMichal Simek mdio { 83*99adc529SMichal Simek #address-cells = <1>; 84*99adc529SMichal Simek #size-cells = <0>; 85*99adc529SMichal Simek phy: ethernet-phy@4 { 86*99adc529SMichal Simek reg = <4>; 87*99adc529SMichal Simek }; 88*99adc529SMichal Simek }; 89*99adc529SMichal Simek}; 90*99adc529SMichal Simek 91*99adc529SMichal Simek&ospi { 92*99adc529SMichal Simek num-cs = <2>; 93*99adc529SMichal Simek iommus = <&smmu 0x245>; 94*99adc529SMichal Simek #address-cells = <1>; 95*99adc529SMichal Simek #size-cells = <0>; 96*99adc529SMichal Simek}; 97*99adc529SMichal Simek 98*99adc529SMichal Simek&sdhci1 { 99*99adc529SMichal Simek status = "okay"; 100*99adc529SMichal Simek iommus = <&smmu 0x243>; 101*99adc529SMichal Simek non-removable; 102*99adc529SMichal Simek disable-wp; 103*99adc529SMichal Simek no-sd; 104*99adc529SMichal Simek no-sdio; 105*99adc529SMichal Simek cap-mmc-hw-reset; 106*99adc529SMichal Simek bus-width = <8>; 107*99adc529SMichal Simek no-1-8-v; 108*99adc529SMichal Simek}; 109*99adc529SMichal Simek 110*99adc529SMichal Simek&serial1 { 111*99adc529SMichal Simek status = "okay"; 112*99adc529SMichal Simek}; 113*99adc529SMichal Simek 114*99adc529SMichal Simek&smmu { 115*99adc529SMichal Simek status = "okay"; 116*99adc529SMichal Simek}; 117