1*2742d963SBeleswar Padhi// SPDX-License-Identifier: GPL-2.0-only OR MIT 2*2742d963SBeleswar Padhi/** 3*2742d963SBeleswar Padhi * Device Tree Source for enabling IPC using TI SDK firmware on J784S4 SoCs 4*2742d963SBeleswar Padhi * 5*2742d963SBeleswar Padhi * Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ 6*2742d963SBeleswar Padhi */ 7*2742d963SBeleswar Padhi 8*2742d963SBeleswar Padhi&reserved_memory { 9*2742d963SBeleswar Padhi c71_3_dma_memory_region: memory@ab000000 { 10*2742d963SBeleswar Padhi compatible = "shared-dma-pool"; 11*2742d963SBeleswar Padhi reg = <0x00 0xab000000 0x00 0x100000>; 12*2742d963SBeleswar Padhi no-map; 13*2742d963SBeleswar Padhi }; 14*2742d963SBeleswar Padhi 15*2742d963SBeleswar Padhi c71_3_memory_region: memory@ab100000 { 16*2742d963SBeleswar Padhi compatible = "shared-dma-pool"; 17*2742d963SBeleswar Padhi reg = <0x00 0xab100000 0x00 0xf00000>; 18*2742d963SBeleswar Padhi no-map; 19*2742d963SBeleswar Padhi }; 20*2742d963SBeleswar Padhi}; 21*2742d963SBeleswar Padhi 22*2742d963SBeleswar Padhi&mailbox0_cluster5 { 23*2742d963SBeleswar Padhi 24*2742d963SBeleswar Padhi mbox_c71_3: mbox-c71-3 { 25*2742d963SBeleswar Padhi ti,mbox-rx = <2 0 0>; 26*2742d963SBeleswar Padhi ti,mbox-tx = <3 0 0>; 27*2742d963SBeleswar Padhi }; 28*2742d963SBeleswar Padhi}; 29*2742d963SBeleswar Padhi 30*2742d963SBeleswar Padhi&c71_3 { 31*2742d963SBeleswar Padhi mboxes = <&mailbox0_cluster5 &mbox_c71_3>; 32*2742d963SBeleswar Padhi memory-region = <&c71_3_dma_memory_region>, 33*2742d963SBeleswar Padhi <&c71_3_memory_region>; 34*2742d963SBeleswar Padhi status = "okay"; 35*2742d963SBeleswar Padhi}; 36