xref: /linux/scripts/dtc/include-prefixes/arm64/ti/k3-j722s-ti-ipc-firmware.dtsi (revision 4f38da1f027ea2c9f01bb71daa7a299c191b6940)
1*3cc04e49SBeleswar Padhi// SPDX-License-Identifier: GPL-2.0-only OR MIT
2*3cc04e49SBeleswar Padhi/**
3*3cc04e49SBeleswar Padhi * Device Tree Source for enabling IPC using TI SDK firmware on J722S SoCs
4*3cc04e49SBeleswar Padhi *
5*3cc04e49SBeleswar Padhi * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com/
6*3cc04e49SBeleswar Padhi */
7*3cc04e49SBeleswar Padhi
8*3cc04e49SBeleswar Padhi&reserved_memory {
9*3cc04e49SBeleswar Padhi	mcu_r5fss0_core0_dma_memory_region: memory@a1000000 {
10*3cc04e49SBeleswar Padhi		compatible = "shared-dma-pool";
11*3cc04e49SBeleswar Padhi		reg = <0x00 0xa1000000 0x00 0x100000>;
12*3cc04e49SBeleswar Padhi		no-map;
13*3cc04e49SBeleswar Padhi	};
14*3cc04e49SBeleswar Padhi
15*3cc04e49SBeleswar Padhi	mcu_r5fss0_core0_memory_region: memory@a1100000 {
16*3cc04e49SBeleswar Padhi		compatible = "shared-dma-pool";
17*3cc04e49SBeleswar Padhi		reg = <0x00 0xa1100000 0x00 0xf00000>;
18*3cc04e49SBeleswar Padhi		no-map;
19*3cc04e49SBeleswar Padhi	};
20*3cc04e49SBeleswar Padhi
21*3cc04e49SBeleswar Padhi	main_r5fss0_core0_dma_memory_region: memory@a2000000 {
22*3cc04e49SBeleswar Padhi		compatible = "shared-dma-pool";
23*3cc04e49SBeleswar Padhi		reg = <0x00 0xa2000000 0x00 0x100000>;
24*3cc04e49SBeleswar Padhi		no-map;
25*3cc04e49SBeleswar Padhi	};
26*3cc04e49SBeleswar Padhi
27*3cc04e49SBeleswar Padhi	main_r5fss0_core0_memory_region: memory@a2100000 {
28*3cc04e49SBeleswar Padhi		compatible = "shared-dma-pool";
29*3cc04e49SBeleswar Padhi		reg = <0x00 0xa2100000 0x00 0xf00000>;
30*3cc04e49SBeleswar Padhi		no-map;
31*3cc04e49SBeleswar Padhi	};
32*3cc04e49SBeleswar Padhi
33*3cc04e49SBeleswar Padhi	c7x_0_dma_memory_region: memory@a3000000 {
34*3cc04e49SBeleswar Padhi		compatible = "shared-dma-pool";
35*3cc04e49SBeleswar Padhi		reg = <0x00 0xa3000000 0x00 0x100000>;
36*3cc04e49SBeleswar Padhi		no-map;
37*3cc04e49SBeleswar Padhi	};
38*3cc04e49SBeleswar Padhi
39*3cc04e49SBeleswar Padhi	c7x_0_memory_region: memory@a3100000 {
40*3cc04e49SBeleswar Padhi		compatible = "shared-dma-pool";
41*3cc04e49SBeleswar Padhi		reg = <0x00 0xa3100000 0x00 0xf00000>;
42*3cc04e49SBeleswar Padhi		no-map;
43*3cc04e49SBeleswar Padhi	};
44*3cc04e49SBeleswar Padhi
45*3cc04e49SBeleswar Padhi	c7x_1_dma_memory_region: memory@a4000000 {
46*3cc04e49SBeleswar Padhi		compatible = "shared-dma-pool";
47*3cc04e49SBeleswar Padhi		reg = <0x00 0xa4000000 0x00 0x100000>;
48*3cc04e49SBeleswar Padhi		no-map;
49*3cc04e49SBeleswar Padhi	};
50*3cc04e49SBeleswar Padhi
51*3cc04e49SBeleswar Padhi	c7x_1_memory_region: memory@a4100000 {
52*3cc04e49SBeleswar Padhi		compatible = "shared-dma-pool";
53*3cc04e49SBeleswar Padhi		reg = <0x00 0xa4100000 0x00 0xf00000>;
54*3cc04e49SBeleswar Padhi		no-map;
55*3cc04e49SBeleswar Padhi	};
56*3cc04e49SBeleswar Padhi
57*3cc04e49SBeleswar Padhi	rtos_ipc_memory_region: memory@a5000000 {
58*3cc04e49SBeleswar Padhi		reg = <0x00 0xa5000000 0x00 0x1c00000>;
59*3cc04e49SBeleswar Padhi		alignment = <0x1000>;
60*3cc04e49SBeleswar Padhi		no-map;
61*3cc04e49SBeleswar Padhi	};
62*3cc04e49SBeleswar Padhi};
63*3cc04e49SBeleswar Padhi
64*3cc04e49SBeleswar Padhi&mailbox0_cluster0 {
65*3cc04e49SBeleswar Padhi	status = "okay";
66*3cc04e49SBeleswar Padhi
67*3cc04e49SBeleswar Padhi	mbox_wkup_r5_0: mbox-wkup-r5-0 {
68*3cc04e49SBeleswar Padhi		ti,mbox-rx = <0 0 0>;
69*3cc04e49SBeleswar Padhi		ti,mbox-tx = <1 0 0>;
70*3cc04e49SBeleswar Padhi	};
71*3cc04e49SBeleswar Padhi};
72*3cc04e49SBeleswar Padhi
73*3cc04e49SBeleswar Padhi&mailbox0_cluster1 {
74*3cc04e49SBeleswar Padhi	status = "okay";
75*3cc04e49SBeleswar Padhi
76*3cc04e49SBeleswar Padhi	mbox_mcu_r5_0: mbox-mcu-r5-0 {
77*3cc04e49SBeleswar Padhi		ti,mbox-rx = <0 0 0>;
78*3cc04e49SBeleswar Padhi		ti,mbox-tx = <1 0 0>;
79*3cc04e49SBeleswar Padhi	};
80*3cc04e49SBeleswar Padhi};
81*3cc04e49SBeleswar Padhi
82*3cc04e49SBeleswar Padhi&mailbox0_cluster2 {
83*3cc04e49SBeleswar Padhi	status = "okay";
84*3cc04e49SBeleswar Padhi
85*3cc04e49SBeleswar Padhi	mbox_c7x_0: mbox-c7x-0 {
86*3cc04e49SBeleswar Padhi		ti,mbox-rx = <0 0 0>;
87*3cc04e49SBeleswar Padhi		ti,mbox-tx = <1 0 0>;
88*3cc04e49SBeleswar Padhi	};
89*3cc04e49SBeleswar Padhi};
90*3cc04e49SBeleswar Padhi
91*3cc04e49SBeleswar Padhi&mailbox0_cluster3 {
92*3cc04e49SBeleswar Padhi	status = "okay";
93*3cc04e49SBeleswar Padhi
94*3cc04e49SBeleswar Padhi	mbox_main_r5_0: mbox-main-r5-0 {
95*3cc04e49SBeleswar Padhi		ti,mbox-rx = <0 0 0>;
96*3cc04e49SBeleswar Padhi		ti,mbox-tx = <1 0 0>;
97*3cc04e49SBeleswar Padhi	};
98*3cc04e49SBeleswar Padhi
99*3cc04e49SBeleswar Padhi	mbox_c7x_1: mbox-c7x-1 {
100*3cc04e49SBeleswar Padhi		ti,mbox-rx = <2 0 0>;
101*3cc04e49SBeleswar Padhi		ti,mbox-tx = <3 0 0>;
102*3cc04e49SBeleswar Padhi	};
103*3cc04e49SBeleswar Padhi};
104*3cc04e49SBeleswar Padhi
105*3cc04e49SBeleswar Padhi/* Timers are used by Remoteproc firmware */
106*3cc04e49SBeleswar Padhi&main_timer0 {
107*3cc04e49SBeleswar Padhi	status = "reserved";
108*3cc04e49SBeleswar Padhi};
109*3cc04e49SBeleswar Padhi
110*3cc04e49SBeleswar Padhi&main_timer1 {
111*3cc04e49SBeleswar Padhi	status = "reserved";
112*3cc04e49SBeleswar Padhi};
113*3cc04e49SBeleswar Padhi
114*3cc04e49SBeleswar Padhi&main_timer2 {
115*3cc04e49SBeleswar Padhi	status = "reserved";
116*3cc04e49SBeleswar Padhi};
117*3cc04e49SBeleswar Padhi
118*3cc04e49SBeleswar Padhi&wkup_r5fss0 {
119*3cc04e49SBeleswar Padhi	status = "okay";
120*3cc04e49SBeleswar Padhi};
121*3cc04e49SBeleswar Padhi
122*3cc04e49SBeleswar Padhi&wkup_r5fss0_core0 {
123*3cc04e49SBeleswar Padhi	mboxes = <&mailbox0_cluster0 &mbox_wkup_r5_0>;
124*3cc04e49SBeleswar Padhi	memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
125*3cc04e49SBeleswar Padhi			<&wkup_r5fss0_core0_memory_region>;
126*3cc04e49SBeleswar Padhi	status = "okay";
127*3cc04e49SBeleswar Padhi};
128*3cc04e49SBeleswar Padhi
129*3cc04e49SBeleswar Padhi&mcu_r5fss0 {
130*3cc04e49SBeleswar Padhi	status = "okay";
131*3cc04e49SBeleswar Padhi};
132*3cc04e49SBeleswar Padhi
133*3cc04e49SBeleswar Padhi&mcu_r5fss0_core0 {
134*3cc04e49SBeleswar Padhi	mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>;
135*3cc04e49SBeleswar Padhi	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
136*3cc04e49SBeleswar Padhi			<&mcu_r5fss0_core0_memory_region>;
137*3cc04e49SBeleswar Padhi	status = "okay";
138*3cc04e49SBeleswar Padhi};
139*3cc04e49SBeleswar Padhi
140*3cc04e49SBeleswar Padhi&main_r5fss0 {
141*3cc04e49SBeleswar Padhi	status = "okay";
142*3cc04e49SBeleswar Padhi};
143*3cc04e49SBeleswar Padhi
144*3cc04e49SBeleswar Padhi&main_r5fss0_core0 {
145*3cc04e49SBeleswar Padhi	mboxes = <&mailbox0_cluster3 &mbox_main_r5_0>;
146*3cc04e49SBeleswar Padhi	memory-region = <&main_r5fss0_core0_dma_memory_region>,
147*3cc04e49SBeleswar Padhi			<&main_r5fss0_core0_memory_region>;
148*3cc04e49SBeleswar Padhi	status = "okay";
149*3cc04e49SBeleswar Padhi};
150*3cc04e49SBeleswar Padhi
151*3cc04e49SBeleswar Padhi&c7x_0 {
152*3cc04e49SBeleswar Padhi	mboxes = <&mailbox0_cluster2 &mbox_c7x_0>;
153*3cc04e49SBeleswar Padhi	memory-region = <&c7x_0_dma_memory_region>,
154*3cc04e49SBeleswar Padhi			<&c7x_0_memory_region>;
155*3cc04e49SBeleswar Padhi	status = "okay";
156*3cc04e49SBeleswar Padhi};
157*3cc04e49SBeleswar Padhi
158*3cc04e49SBeleswar Padhi&c7x_1 {
159*3cc04e49SBeleswar Padhi	mboxes = <&mailbox0_cluster3 &mbox_c7x_1>;
160*3cc04e49SBeleswar Padhi	memory-region = <&c7x_1_dma_memory_region>,
161*3cc04e49SBeleswar Padhi			<&c7x_1_memory_region>;
162*3cc04e49SBeleswar Padhi	status = "okay";
163*3cc04e49SBeleswar Padhi};
164