xref: /linux/scripts/dtc/include-prefixes/arm64/ti/k3-am67a-kontron-sa67-base.dts (revision 0cac5ce06e524755b3dac1e0a060b05992076d93)
1*1c3c4df0SMichael Walle// SPDX-License-Identifier: GPL-2.0-only OR MIT
2*1c3c4df0SMichael Walle/*
3*1c3c4df0SMichael Walle * Kontron SMARC-sAM67 module
4*1c3c4df0SMichael Walle *
5*1c3c4df0SMichael Walle * Copyright (c) 2025 Kontron Europe GmbH
6*1c3c4df0SMichael Walle */
7*1c3c4df0SMichael Walle
8*1c3c4df0SMichael Walle/dts-v1/;
9*1c3c4df0SMichael Walle
10*1c3c4df0SMichael Walle#include <dt-bindings/gpio/gpio.h>
11*1c3c4df0SMichael Walle#include <dt-bindings/interrupt-controller/irq.h>
12*1c3c4df0SMichael Walle#include <dt-bindings/phy/phy.h>
13*1c3c4df0SMichael Walle#include "k3-j722s.dtsi"
14*1c3c4df0SMichael Walle#include "k3-serdes.h"
15*1c3c4df0SMichael Walle
16*1c3c4df0SMichael Walle/ {
17*1c3c4df0SMichael Walle	compatible = "kontron,sa67", "ti,j722s";
18*1c3c4df0SMichael Walle	model = "Kontron SMARC-sAM67";
19*1c3c4df0SMichael Walle
20*1c3c4df0SMichael Walle	aliases {
21*1c3c4df0SMichael Walle		serial0 = &mcu_uart0;
22*1c3c4df0SMichael Walle		serial1 = &main_uart0;
23*1c3c4df0SMichael Walle		serial2 = &main_uart5;
24*1c3c4df0SMichael Walle		serial3 = &wkup_uart0;
25*1c3c4df0SMichael Walle		mmc0 = &sdhci0;
26*1c3c4df0SMichael Walle		mmc1 = &sdhci1;
27*1c3c4df0SMichael Walle		rtc0 = &wkup_rtc0;
28*1c3c4df0SMichael Walle	};
29*1c3c4df0SMichael Walle
30*1c3c4df0SMichael Walle	lcd0_backlight: backlight-1 {
31*1c3c4df0SMichael Walle		compatible = "pwm-backlight";
32*1c3c4df0SMichael Walle		pinctrl-names = "default";
33*1c3c4df0SMichael Walle		pinctrl-0 = <&lcd0_backlight_pins_default>;
34*1c3c4df0SMichael Walle		pwms = <&epwm1 0 50000 0>;
35*1c3c4df0SMichael Walle		brightness-levels = <0 32 64 96 128 160 192 224 255>;
36*1c3c4df0SMichael Walle		default-brightness-level = <8>;
37*1c3c4df0SMichael Walle		enable-gpios = <&main_gpio0 29 GPIO_ACTIVE_HIGH>;
38*1c3c4df0SMichael Walle		status = "disabled";
39*1c3c4df0SMichael Walle	};
40*1c3c4df0SMichael Walle
41*1c3c4df0SMichael Walle	lcd1_backlight: backlight-2 {
42*1c3c4df0SMichael Walle		compatible = "pwm-backlight";
43*1c3c4df0SMichael Walle		pinctrl-names = "default";
44*1c3c4df0SMichael Walle		pinctrl-0 = <&lcd1_backlight_pins_default>;
45*1c3c4df0SMichael Walle		pwms = <&epwm1 1 50000 0>;
46*1c3c4df0SMichael Walle		brightness-levels = <0 32 64 96 128 160 192 224 255>;
47*1c3c4df0SMichael Walle		default-brightness-level = <8>;
48*1c3c4df0SMichael Walle		enable-gpios = <&main_gpio1 18 GPIO_ACTIVE_HIGH>;
49*1c3c4df0SMichael Walle		status = "disabled";
50*1c3c4df0SMichael Walle	};
51*1c3c4df0SMichael Walle
52*1c3c4df0SMichael Walle	chosen {
53*1c3c4df0SMichael Walle		stdout-path = "serial1:115200n8";
54*1c3c4df0SMichael Walle	};
55*1c3c4df0SMichael Walle
56*1c3c4df0SMichael Walle	connector-1 {
57*1c3c4df0SMichael Walle		compatible = "gpio-usb-b-connector", "usb-b-connector";
58*1c3c4df0SMichael Walle		pinctrl-names = "default";
59*1c3c4df0SMichael Walle		pinctrl-0 = <&usb0_connector_pins_default>;
60*1c3c4df0SMichael Walle		type = "micro";
61*1c3c4df0SMichael Walle		id-gpios = <&main_gpio0 34 GPIO_ACTIVE_HIGH>;
62*1c3c4df0SMichael Walle		vbus-supply = <&vcc_usb0_vbus>;
63*1c3c4df0SMichael Walle
64*1c3c4df0SMichael Walle		port  {
65*1c3c4df0SMichael Walle			usb0_connector: endpoint {
66*1c3c4df0SMichael Walle				remote-endpoint = <&usb0_hc>;
67*1c3c4df0SMichael Walle			};
68*1c3c4df0SMichael Walle		};
69*1c3c4df0SMichael Walle
70*1c3c4df0SMichael Walle	};
71*1c3c4df0SMichael Walle
72*1c3c4df0SMichael Walle	memory@80000000 {
73*1c3c4df0SMichael Walle		/* Filled in by bootloader */
74*1c3c4df0SMichael Walle		reg = <0x00000000 0x00000000 0x00000000 0x00000000>,
75*1c3c4df0SMichael Walle		      <0x00000000 0x00000000 0x00000000 0x00000000>;
76*1c3c4df0SMichael Walle		device_type = "memory";
77*1c3c4df0SMichael Walle		bootph-pre-ram;
78*1c3c4df0SMichael Walle	};
79*1c3c4df0SMichael Walle
80*1c3c4df0SMichael Walle	reserved_memory: reserved-memory {
81*1c3c4df0SMichael Walle		#address-cells = <2>;
82*1c3c4df0SMichael Walle		#size-cells = <2>;
83*1c3c4df0SMichael Walle		ranges;
84*1c3c4df0SMichael Walle
85*1c3c4df0SMichael Walle		linux,cma {
86*1c3c4df0SMichael Walle			compatible = "shared-dma-pool";
87*1c3c4df0SMichael Walle			reusable;
88*1c3c4df0SMichael Walle			size = <0x10000000>;
89*1c3c4df0SMichael Walle			alignment = <0x2000>;
90*1c3c4df0SMichael Walle			linux,cma-default;
91*1c3c4df0SMichael Walle		};
92*1c3c4df0SMichael Walle
93*1c3c4df0SMichael Walle		secure_tfa_ddr: tfa@9e780000 {
94*1c3c4df0SMichael Walle			reg = <0x00 0x9e780000 0x00 0x80000>;
95*1c3c4df0SMichael Walle			no-map;
96*1c3c4df0SMichael Walle		};
97*1c3c4df0SMichael Walle
98*1c3c4df0SMichael Walle		secure_ddr: optee@9e800000 {
99*1c3c4df0SMichael Walle			reg = <0x00 0x9e800000 0x00 0x01800000>;
100*1c3c4df0SMichael Walle			no-map;
101*1c3c4df0SMichael Walle		};
102*1c3c4df0SMichael Walle
103*1c3c4df0SMichael Walle		wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 {
104*1c3c4df0SMichael Walle			compatible = "shared-dma-pool";
105*1c3c4df0SMichael Walle			reg = <0x00 0xa0100000 0x00 0xf00000>;
106*1c3c4df0SMichael Walle			no-map;
107*1c3c4df0SMichael Walle		};
108*1c3c4df0SMichael Walle	};
109*1c3c4df0SMichael Walle
110*1c3c4df0SMichael Walle	vin_5p0: regulator-1 {
111*1c3c4df0SMichael Walle		compatible = "regulator-fixed";
112*1c3c4df0SMichael Walle		regulator-name = "V_3V0_5V25_IN";
113*1c3c4df0SMichael Walle		regulator-min-microvolt = <5000000>;
114*1c3c4df0SMichael Walle		regulator-max-microvolt = <5000000>;
115*1c3c4df0SMichael Walle		regulator-always-on;
116*1c3c4df0SMichael Walle		regulator-boot-on;
117*1c3c4df0SMichael Walle		bootph-all;
118*1c3c4df0SMichael Walle	};
119*1c3c4df0SMichael Walle
120*1c3c4df0SMichael Walle	vcc_3p3_s5: regulator-2 {
121*1c3c4df0SMichael Walle		compatible = "regulator-fixed";
122*1c3c4df0SMichael Walle		regulator-name = "V_3V3_S5";
123*1c3c4df0SMichael Walle		regulator-min-microvolt = <3300000>;
124*1c3c4df0SMichael Walle		regulator-max-microvolt = <3300000>;
125*1c3c4df0SMichael Walle		vin-supply = <&vin_5p0>;
126*1c3c4df0SMichael Walle		regulator-always-on;
127*1c3c4df0SMichael Walle		regulator-boot-on;
128*1c3c4df0SMichael Walle		bootph-all;
129*1c3c4df0SMichael Walle	};
130*1c3c4df0SMichael Walle
131*1c3c4df0SMichael Walle	vcc_1p8_s5: regulator-3 {
132*1c3c4df0SMichael Walle		compatible = "regulator-fixed";
133*1c3c4df0SMichael Walle		regulator-name = "V_1V8_S5";
134*1c3c4df0SMichael Walle		regulator-min-microvolt = <1800000>;
135*1c3c4df0SMichael Walle		regulator-max-microvolt = <1800000>;
136*1c3c4df0SMichael Walle		vin-supply = <&vin_5p0>;
137*1c3c4df0SMichael Walle		regulator-always-on;
138*1c3c4df0SMichael Walle		regulator-boot-on;
139*1c3c4df0SMichael Walle		bootph-all;
140*1c3c4df0SMichael Walle	};
141*1c3c4df0SMichael Walle
142*1c3c4df0SMichael Walle	vcc_3p3_s0: regulator-4 {
143*1c3c4df0SMichael Walle		compatible = "regulator-fixed";
144*1c3c4df0SMichael Walle		regulator-name = "V_3V3_S0";
145*1c3c4df0SMichael Walle		regulator-min-microvolt = <3300000>;
146*1c3c4df0SMichael Walle		regulator-max-microvolt = <3300000>;
147*1c3c4df0SMichael Walle		vin-supply = <&vcc_3p3_s5>;
148*1c3c4df0SMichael Walle		regulator-always-on;
149*1c3c4df0SMichael Walle		regulator-boot-on;
150*1c3c4df0SMichael Walle		enable-active-high;
151*1c3c4df0SMichael Walle		gpios = <&tps652g1 1 GPIO_ACTIVE_HIGH>;
152*1c3c4df0SMichael Walle		bootph-all;
153*1c3c4df0SMichael Walle	};
154*1c3c4df0SMichael Walle
155*1c3c4df0SMichael Walle	vcc_3p3_sd_s0: regulator-5 {
156*1c3c4df0SMichael Walle		compatible = "regulator-fixed";
157*1c3c4df0SMichael Walle		regulator-name = "SDIO_PWR_EN";
158*1c3c4df0SMichael Walle		pinctrl-names = "default";
159*1c3c4df0SMichael Walle		pinctrl-0 = <&vcc_3p3_sd_s0_pins_default>;
160*1c3c4df0SMichael Walle		regulator-min-microvolt = <3300000>;
161*1c3c4df0SMichael Walle		regulator-max-microvolt = <3300000>;
162*1c3c4df0SMichael Walle		regulator-boot-on;
163*1c3c4df0SMichael Walle		enable-active-high;
164*1c3c4df0SMichael Walle		gpios = <&main_gpio0 7 GPIO_ACTIVE_HIGH>;
165*1c3c4df0SMichael Walle		bootph-all;
166*1c3c4df0SMichael Walle	};
167*1c3c4df0SMichael Walle
168*1c3c4df0SMichael Walle	vcc_3p3_sd_vio_s0: regulator-6 {
169*1c3c4df0SMichael Walle		compatible = "regulator-gpio";
170*1c3c4df0SMichael Walle		regulator-name = "V_3V3_1V8_SD_S0";
171*1c3c4df0SMichael Walle		pinctrl-names = "default";
172*1c3c4df0SMichael Walle		pinctrl-0 = <&vcc_3p3_sd_vio_s0_pins_default>;
173*1c3c4df0SMichael Walle		regulator-min-microvolt = <1800000>;
174*1c3c4df0SMichael Walle		regulator-max-microvolt = <3300000>;
175*1c3c4df0SMichael Walle		vin-supply = <&vcc_3p3_s0>;
176*1c3c4df0SMichael Walle		regulator-boot-on;
177*1c3c4df0SMichael Walle		enable-gpios = <&main_gpio0 7 GPIO_ACTIVE_HIGH>;
178*1c3c4df0SMichael Walle		gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>;
179*1c3c4df0SMichael Walle		states = <3300000 0x0>,
180*1c3c4df0SMichael Walle			 <1800000 0x1>;
181*1c3c4df0SMichael Walle		bootph-all;
182*1c3c4df0SMichael Walle	};
183*1c3c4df0SMichael Walle
184*1c3c4df0SMichael Walle	vcc_3p3_cam_s0: regulator-7 {
185*1c3c4df0SMichael Walle		compatible = "regulator-fixed";
186*1c3c4df0SMichael Walle		regulator-name = "V_3V3_CAM_S0";
187*1c3c4df0SMichael Walle		pinctrl-names = "default";
188*1c3c4df0SMichael Walle		pinctrl-0 = <&vcc_3p3_cam_s0_pins_default>;
189*1c3c4df0SMichael Walle		regulator-min-microvolt = <3300000>;
190*1c3c4df0SMichael Walle		regulator-max-microvolt = <3300000>;
191*1c3c4df0SMichael Walle		vin-supply = <&vcc_3p3_s5>;
192*1c3c4df0SMichael Walle		enable-active-high;
193*1c3c4df0SMichael Walle		interrupts-extended = <&main_gpio1 30 IRQ_TYPE_EDGE_FALLING>;
194*1c3c4df0SMichael Walle		bootph-all;
195*1c3c4df0SMichael Walle	};
196*1c3c4df0SMichael Walle
197*1c3c4df0SMichael Walle	vcc_1p1_s0: regulator-8 {
198*1c3c4df0SMichael Walle		compatible = "regulator-fixed";
199*1c3c4df0SMichael Walle		regulator-name = "V_1V1_S0";
200*1c3c4df0SMichael Walle		regulator-min-microvolt = <1100000>;
201*1c3c4df0SMichael Walle		regulator-max-microvolt = <1100000>;
202*1c3c4df0SMichael Walle		vin-supply = <&vcc_1p1_s3>;
203*1c3c4df0SMichael Walle		regulator-always-on;
204*1c3c4df0SMichael Walle		regulator-boot-on;
205*1c3c4df0SMichael Walle		enable-active-high;
206*1c3c4df0SMichael Walle		/* shared with V_0V75_0V85_CORE_S0 */
207*1c3c4df0SMichael Walle		gpios = <&tps652g1 4 GPIO_ACTIVE_HIGH>;
208*1c3c4df0SMichael Walle		bootph-all;
209*1c3c4df0SMichael Walle	};
210*1c3c4df0SMichael Walle
211*1c3c4df0SMichael Walle	vcc_0p85_vcore_s0: regulator-9 {
212*1c3c4df0SMichael Walle		compatible = "regulator-fixed";
213*1c3c4df0SMichael Walle		regulator-name = "V_0V75_0V85_CORE_S0";
214*1c3c4df0SMichael Walle		regulator-min-microvolt = <850000>;
215*1c3c4df0SMichael Walle		regulator-max-microvolt = <850000>;
216*1c3c4df0SMichael Walle		vin-supply = <&vin_5p0>;
217*1c3c4df0SMichael Walle		regulator-always-on;
218*1c3c4df0SMichael Walle		regulator-boot-on;
219*1c3c4df0SMichael Walle		enable-active-high;
220*1c3c4df0SMichael Walle		gpios = <&tps652g1 4 GPIO_ACTIVE_HIGH>;
221*1c3c4df0SMichael Walle		bootph-all;
222*1c3c4df0SMichael Walle	};
223*1c3c4df0SMichael Walle
224*1c3c4df0SMichael Walle	vcc_lcd0_panel: regulator-10 {
225*1c3c4df0SMichael Walle		compatible = "regulator-fixed";
226*1c3c4df0SMichael Walle		regulator-name = "LCD0_VDD_EN";
227*1c3c4df0SMichael Walle		pinctrl-names = "default";
228*1c3c4df0SMichael Walle		pinctrl-0 = <&vcc_lcd0_panel_pins_default>;
229*1c3c4df0SMichael Walle		enable-active-high;
230*1c3c4df0SMichael Walle		gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>;
231*1c3c4df0SMichael Walle	};
232*1c3c4df0SMichael Walle
233*1c3c4df0SMichael Walle	vcc_lcd1_panel: regulator-11 {
234*1c3c4df0SMichael Walle		compatible = "regulator-fixed";
235*1c3c4df0SMichael Walle		regulator-name = "LCD1_VDD_EN";
236*1c3c4df0SMichael Walle		pinctrl-names = "default";
237*1c3c4df0SMichael Walle		pinctrl-0 = <&vcc_lcd1_panel_pins_default>;
238*1c3c4df0SMichael Walle		enable-active-high;
239*1c3c4df0SMichael Walle		gpios = <&main_gpio1 19 GPIO_ACTIVE_HIGH>;
240*1c3c4df0SMichael Walle	};
241*1c3c4df0SMichael Walle
242*1c3c4df0SMichael Walle	vcc_usb0_vbus: regulator-12 {
243*1c3c4df0SMichael Walle		compatible = "regulator-fixed";
244*1c3c4df0SMichael Walle		regulator-name = "USB0_EN_OC#";
245*1c3c4df0SMichael Walle		pinctrl-names = "default";
246*1c3c4df0SMichael Walle		pinctrl-0 = <&vcc_usb0_vbus_pins_default>;
247*1c3c4df0SMichael Walle		regulator-min-microvolt = <5000000>;
248*1c3c4df0SMichael Walle		regulator-max-microvolt = <5000000>;
249*1c3c4df0SMichael Walle		enable-active-high;
250*1c3c4df0SMichael Walle		gpios = <&main_gpio1 50 GPIO_ACTIVE_HIGH>;
251*1c3c4df0SMichael Walle	};
252*1c3c4df0SMichael Walle};
253*1c3c4df0SMichael Walle
254*1c3c4df0SMichael Walle&audio_refclk0 {
255*1c3c4df0SMichael Walle	pinctrl-names = "default";
256*1c3c4df0SMichael Walle	pinctrl-0 = <&audio_refclk0_pins_default>;
257*1c3c4df0SMichael Walle	status = "disabled";
258*1c3c4df0SMichael Walle};
259*1c3c4df0SMichael Walle
260*1c3c4df0SMichael Walle&audio_refclk1 {
261*1c3c4df0SMichael Walle	pinctrl-names = "default";
262*1c3c4df0SMichael Walle	pinctrl-0 = <&audio_refclk1_pins_default>;
263*1c3c4df0SMichael Walle	status = "disabled";
264*1c3c4df0SMichael Walle};
265*1c3c4df0SMichael Walle
266*1c3c4df0SMichael Walle&cpsw3g {
267*1c3c4df0SMichael Walle	pinctrl-names = "default";
268*1c3c4df0SMichael Walle	pinctrl-0 = <&cpsw3g_pins_default>, <&rgmii1_pins_default>,
269*1c3c4df0SMichael Walle		    <&rgmii2_pins_default>;
270*1c3c4df0SMichael Walle	status = "okay";
271*1c3c4df0SMichael Walle};
272*1c3c4df0SMichael Walle
273*1c3c4df0SMichael Walle&cpsw3g_mdio {
274*1c3c4df0SMichael Walle	pinctrl-names = "default";
275*1c3c4df0SMichael Walle	pinctrl-0 = <&cpsw3g_mdio_pins_default>;
276*1c3c4df0SMichael Walle	status = "okay";
277*1c3c4df0SMichael Walle
278*1c3c4df0SMichael Walle	phy0: ethernet-phy@0 {
279*1c3c4df0SMichael Walle		reg = <0>;
280*1c3c4df0SMichael Walle	};
281*1c3c4df0SMichael Walle
282*1c3c4df0SMichael Walle	phy1: ethernet-phy@1 {
283*1c3c4df0SMichael Walle		reg = <1>;
284*1c3c4df0SMichael Walle	};
285*1c3c4df0SMichael Walle};
286*1c3c4df0SMichael Walle
287*1c3c4df0SMichael Walle&cpsw_port1 {
288*1c3c4df0SMichael Walle	phy-connection-type = "rgmii-id";
289*1c3c4df0SMichael Walle	phy-handle = <&phy0>;
290*1c3c4df0SMichael Walle	nvmem-cells = <&base_mac_address 0>;
291*1c3c4df0SMichael Walle	nvmem-cell-names = "mac-address";
292*1c3c4df0SMichael Walle	status = "okay";
293*1c3c4df0SMichael Walle};
294*1c3c4df0SMichael Walle
295*1c3c4df0SMichael Walle&main_gpio0 {
296*1c3c4df0SMichael Walle	gpio-line-names =
297*1c3c4df0SMichael Walle		"", "", "", "", "", "", "", "SOC_SDIO_PWR_EN", "VSD_SEL",
298*1c3c4df0SMichael Walle		"RESET_OUT#", "I2C_MUX_RST#", "SPI_FLASH_CS#", "QPSI_CS0#",
299*1c3c4df0SMichael Walle		"QSPI_CS1#", "BOOT_SEL1", "BRDCFG0", "BRDCFG1", "BRDCFG2",
300*1c3c4df0SMichael Walle		"BRDCFG3", "BRDCFG4", "", "BRDREV0", "BRDREV1", "", "", "", "",
301*1c3c4df0SMichael Walle		"", "", "LCD0_BKLT_EN", "LCD0_VDD_EN", "GBE_INT#", "DSI0_TE",
302*1c3c4df0SMichael Walle		"CHARGING#", "USB0_OTG_ID", "PMIC_INT#", "RTC_INT#",
303*1c3c4df0SMichael Walle		"EDP_BRIDGE_EN", "EDP_BRIDGE_IRQ#", "", "CHARGER_PRSNT#", "",
304*1c3c4df0SMichael Walle		"", "", "", "BOOT_SEL2#", "CAM2_RST#", "CAM2_PWR#", "",
305*1c3c4df0SMichael Walle		"CAM3_RST#", "CAM3_PWR#", "GPIO0", "GPIO1", "", "", "", "", "",
306*1c3c4df0SMichael Walle		"", "", "", "", "", "", "", "", "", "", "", "GPIO10", "GPIO11",
307*1c3c4df0SMichael Walle		"SLEEP#", "LID#";
308*1c3c4df0SMichael Walle
309*1c3c4df0SMichael Walle	bootph-all;
310*1c3c4df0SMichael Walle	status = "okay";
311*1c3c4df0SMichael Walle};
312*1c3c4df0SMichael Walle
313*1c3c4df0SMichael Walle&main_gpio1 {
314*1c3c4df0SMichael Walle	gpio-line-names =
315*1c3c4df0SMichael Walle		"", "", "", "", "", "", "", "GPIO6", "GPIO7", "", "", "", "",
316*1c3c4df0SMichael Walle		"GPIO8", "GPIO9", "PCIE_A_RST#", "", "BATLOW#", "LCD1_BKLT_EN",
317*1c3c4df0SMichael Walle		"LCD1_VDD_EN", "", "", "", "", "GPIO2", "GPIO3", "", "",
318*1c3c4df0SMichael Walle		"GPIO4", "GPIO5", "CAM_S0_FAULT#", "BOOT_SEL0#", "", "", "", "",
319*1c3c4df0SMichael Walle		"", "", "", "", "", "", "", "", "", "", "", "", "SDIO_CD#", "",
320*1c3c4df0SMichael Walle		"USB0_DRVVBUS", "USB1_DRVVBUS";
321*1c3c4df0SMichael Walle
322*1c3c4df0SMichael Walle	bootph-all;
323*1c3c4df0SMichael Walle	status = "okay";
324*1c3c4df0SMichael Walle};
325*1c3c4df0SMichael Walle
326*1c3c4df0SMichael Walle/* I2C_LOCAL */
327*1c3c4df0SMichael Walle&main_i2c0 {
328*1c3c4df0SMichael Walle	pinctrl-names = "default";
329*1c3c4df0SMichael Walle	pinctrl-0 = <&main_i2c0_pins_default>;
330*1c3c4df0SMichael Walle	clock-frequency = <100000>;
331*1c3c4df0SMichael Walle	bootph-all;
332*1c3c4df0SMichael Walle	status = "okay";
333*1c3c4df0SMichael Walle
334*1c3c4df0SMichael Walle	tps652g1: pmic@44 {
335*1c3c4df0SMichael Walle		compatible = "ti,tps652g1";
336*1c3c4df0SMichael Walle		reg = <0x44>;
337*1c3c4df0SMichael Walle		ti,primary-pmic;
338*1c3c4df0SMichael Walle		system-power-controller;
339*1c3c4df0SMichael Walle
340*1c3c4df0SMichael Walle		gpio-controller;
341*1c3c4df0SMichael Walle		#gpio-cells = <2>;
342*1c3c4df0SMichael Walle		gpio-line-names =
343*1c3c4df0SMichael Walle			"LPM_EN#", "EN_3V3_S0", "POWER_BTN#", "CARRIER_STBY#",
344*1c3c4df0SMichael Walle			"EN_0V75_0V85_VCORE_S0", "PMIC_WAKEUP";
345*1c3c4df0SMichael Walle
346*1c3c4df0SMichael Walle		pinctrl-names = "default";
347*1c3c4df0SMichael Walle		pinctrl-0 = <&pmic_irq_pins_default>;
348*1c3c4df0SMichael Walle		interrupts-extended = <&main_gpio0 35 IRQ_TYPE_EDGE_FALLING>;
349*1c3c4df0SMichael Walle
350*1c3c4df0SMichael Walle		buck1-supply = <&vin_5p0>;
351*1c3c4df0SMichael Walle		buck2-supply = <&vin_5p0>;
352*1c3c4df0SMichael Walle		buck3-supply = <&vin_5p0>;
353*1c3c4df0SMichael Walle		buck4-supply = <&vin_5p0>;
354*1c3c4df0SMichael Walle		ldo1-supply = <&vin_5p0>;
355*1c3c4df0SMichael Walle		ldo2-supply = <&vin_5p0>;
356*1c3c4df0SMichael Walle		ldo3-supply = <&vin_5p0>;
357*1c3c4df0SMichael Walle
358*1c3c4df0SMichael Walle		bootph-all;
359*1c3c4df0SMichael Walle
360*1c3c4df0SMichael Walle		regulators {
361*1c3c4df0SMichael Walle			vcc_0p85_s0: buck1 {
362*1c3c4df0SMichael Walle				regulator-name = "V_0V85_S0";
363*1c3c4df0SMichael Walle				regulator-min-microvolt = <850000>;
364*1c3c4df0SMichael Walle				regulator-max-microvolt = <850000>;
365*1c3c4df0SMichael Walle				regulator-boot-on;
366*1c3c4df0SMichael Walle				regulator-always-on;
367*1c3c4df0SMichael Walle			};
368*1c3c4df0SMichael Walle
369*1c3c4df0SMichael Walle			vcc_1p1_s3: buck2 {
370*1c3c4df0SMichael Walle				regulator-name = "V_1V1_S3";
371*1c3c4df0SMichael Walle				regulator-min-microvolt = <1100000>;
372*1c3c4df0SMichael Walle				regulator-max-microvolt = <1100000>;
373*1c3c4df0SMichael Walle				regulator-boot-on;
374*1c3c4df0SMichael Walle				regulator-always-on;
375*1c3c4df0SMichael Walle			};
376*1c3c4df0SMichael Walle
377*1c3c4df0SMichael Walle			vcc_1p8_s0: buck3 {
378*1c3c4df0SMichael Walle				regulator-name = "V_1V8_S0";
379*1c3c4df0SMichael Walle				regulator-min-microvolt = <1800000>;
380*1c3c4df0SMichael Walle				regulator-max-microvolt = <1800000>;
381*1c3c4df0SMichael Walle				regulator-boot-on;
382*1c3c4df0SMichael Walle				regulator-always-on;
383*1c3c4df0SMichael Walle			};
384*1c3c4df0SMichael Walle
385*1c3c4df0SMichael Walle			vcc_1p2_s0: buck4 {
386*1c3c4df0SMichael Walle				regulator-name = "V_1V2_S0";
387*1c3c4df0SMichael Walle				regulator-min-microvolt = <1200000>;
388*1c3c4df0SMichael Walle				regulator-max-microvolt = <1200000>;
389*1c3c4df0SMichael Walle				regulator-boot-on;
390*1c3c4df0SMichael Walle				regulator-always-on;
391*1c3c4df0SMichael Walle			};
392*1c3c4df0SMichael Walle
393*1c3c4df0SMichael Walle			vcc_1p8_vda_pll_s0: ldo1 {
394*1c3c4df0SMichael Walle				regulator-name = "V_1V8_VDA_PLL_S0";
395*1c3c4df0SMichael Walle				regulator-min-microvolt = <1800000>;
396*1c3c4df0SMichael Walle				regulator-max-microvolt = <1800000>;
397*1c3c4df0SMichael Walle				regulator-boot-on;
398*1c3c4df0SMichael Walle				regulator-always-on;
399*1c3c4df0SMichael Walle			};
400*1c3c4df0SMichael Walle
401*1c3c4df0SMichael Walle			vcc_1p8_s3: ldo2 {
402*1c3c4df0SMichael Walle				regulator-name = "V_1V8_S3";
403*1c3c4df0SMichael Walle				regulator-min-microvolt = <1800000>;
404*1c3c4df0SMichael Walle				regulator-max-microvolt = <1800000>;
405*1c3c4df0SMichael Walle				regulator-boot-on;
406*1c3c4df0SMichael Walle				regulator-always-on;
407*1c3c4df0SMichael Walle			};
408*1c3c4df0SMichael Walle
409*1c3c4df0SMichael Walle			vcc_1p8_ret_s5: ldo3 {
410*1c3c4df0SMichael Walle				regulator-name = "V_1V8_RET_S5";
411*1c3c4df0SMichael Walle				regulator-min-microvolt = <1800000>;
412*1c3c4df0SMichael Walle				regulator-max-microvolt = <1800000>;
413*1c3c4df0SMichael Walle				regulator-boot-on;
414*1c3c4df0SMichael Walle				regulator-always-on;
415*1c3c4df0SMichael Walle			};
416*1c3c4df0SMichael Walle		};
417*1c3c4df0SMichael Walle	};
418*1c3c4df0SMichael Walle
419*1c3c4df0SMichael Walle	system-controller@4a {
420*1c3c4df0SMichael Walle		compatible = "kontron,sa67mcu", "kontron,sl28cpld";
421*1c3c4df0SMichael Walle		reg = <0x4a>;
422*1c3c4df0SMichael Walle		#address-cells = <1>;
423*1c3c4df0SMichael Walle		#size-cells = <0>;
424*1c3c4df0SMichael Walle
425*1c3c4df0SMichael Walle		watchdog@4 {
426*1c3c4df0SMichael Walle			compatible = "kontron,sa67mcu-wdt", "kontron,sl28cpld-wdt";
427*1c3c4df0SMichael Walle			reg = <0x4>;
428*1c3c4df0SMichael Walle			kontron,assert-wdt-timeout-pin;
429*1c3c4df0SMichael Walle		};
430*1c3c4df0SMichael Walle
431*1c3c4df0SMichael Walle		hwmon@8 {
432*1c3c4df0SMichael Walle			compatible = "kontron,sa67mcu-hwmon";
433*1c3c4df0SMichael Walle			reg = <0x8>;
434*1c3c4df0SMichael Walle		};
435*1c3c4df0SMichael Walle	};
436*1c3c4df0SMichael Walle};
437*1c3c4df0SMichael Walle
438*1c3c4df0SMichael Walle/* I2C_CAM */
439*1c3c4df0SMichael Walle&main_i2c2 {
440*1c3c4df0SMichael Walle	pinctrl-names = "default";
441*1c3c4df0SMichael Walle	pinctrl-0 = <&main_i2c2_pins_default>;
442*1c3c4df0SMichael Walle	clock-frequency = <100000>;
443*1c3c4df0SMichael Walle	status = "okay";
444*1c3c4df0SMichael Walle
445*1c3c4df0SMichael Walle	i2c-mux@70 {
446*1c3c4df0SMichael Walle		compatible = "nxp,pca9546";
447*1c3c4df0SMichael Walle		reg = <0x70>;
448*1c3c4df0SMichael Walle		#address-cells = <1>;
449*1c3c4df0SMichael Walle		#size-cells = <0>;
450*1c3c4df0SMichael Walle
451*1c3c4df0SMichael Walle		pinctrl-names = "default";
452*1c3c4df0SMichael Walle		pinctrl-0 = <&i2c_mux_pins_default>;
453*1c3c4df0SMichael Walle
454*1c3c4df0SMichael Walle		vdd-supply = <&vcc_1p8_s0>;
455*1c3c4df0SMichael Walle		reset-gpios = <&main_gpio0 10 GPIO_ACTIVE_LOW>;
456*1c3c4df0SMichael Walle
457*1c3c4df0SMichael Walle		i2c_cam0: i2c@0 {
458*1c3c4df0SMichael Walle			#address-cells = <1>;
459*1c3c4df0SMichael Walle			#size-cells = <0>;
460*1c3c4df0SMichael Walle			reg = <0>;
461*1c3c4df0SMichael Walle		};
462*1c3c4df0SMichael Walle
463*1c3c4df0SMichael Walle		i2c_cam1: i2c@1 {
464*1c3c4df0SMichael Walle			#address-cells = <1>;
465*1c3c4df0SMichael Walle			#size-cells = <0>;
466*1c3c4df0SMichael Walle			reg = <1>;
467*1c3c4df0SMichael Walle		};
468*1c3c4df0SMichael Walle
469*1c3c4df0SMichael Walle		i2c_cam2: i2c@2 {
470*1c3c4df0SMichael Walle			#address-cells = <1>;
471*1c3c4df0SMichael Walle			#size-cells = <0>;
472*1c3c4df0SMichael Walle			reg = <2>;
473*1c3c4df0SMichael Walle		};
474*1c3c4df0SMichael Walle
475*1c3c4df0SMichael Walle		i2c_cam3: i2c@3 {
476*1c3c4df0SMichael Walle			#address-cells = <1>;
477*1c3c4df0SMichael Walle			#size-cells = <0>;
478*1c3c4df0SMichael Walle			reg = <3>;
479*1c3c4df0SMichael Walle		};
480*1c3c4df0SMichael Walle	};
481*1c3c4df0SMichael Walle};
482*1c3c4df0SMichael Walle
483*1c3c4df0SMichael Walle/* I2C_LCD */
484*1c3c4df0SMichael Walle&main_i2c3 {
485*1c3c4df0SMichael Walle	pinctrl-names = "default";
486*1c3c4df0SMichael Walle	pinctrl-0 = <&main_i2c3_pins_default>;
487*1c3c4df0SMichael Walle	clock-frequency = <100000>;
488*1c3c4df0SMichael Walle	status = "okay";
489*1c3c4df0SMichael Walle};
490*1c3c4df0SMichael Walle
491*1c3c4df0SMichael Walle&main_pmx0 {
492*1c3c4df0SMichael Walle	audio_refclk0_pins_default: audio-refclk0-default-pins {
493*1c3c4df0SMichael Walle		pinctrl-single,pins = <
494*1c3c4df0SMichael Walle			J722S_IOPAD(0x0c4, PIN_OUTPUT, 5)	/* (W23) VOUT0_DATA3.AUDIO_EXT_REFCLK0 */
495*1c3c4df0SMichael Walle		>;
496*1c3c4df0SMichael Walle	};
497*1c3c4df0SMichael Walle
498*1c3c4df0SMichael Walle	audio_refclk1_pins_default: audio-refclk1-default-pins {
499*1c3c4df0SMichael Walle		pinctrl-single,pins = <
500*1c3c4df0SMichael Walle			J722S_IOPAD(0x0a0, PIN_OUTPUT, 1)	/* (N24) GPMC0_WPn.AUDIO_EXT_REFCLK1 */
501*1c3c4df0SMichael Walle		>;
502*1c3c4df0SMichael Walle	};
503*1c3c4df0SMichael Walle
504*1c3c4df0SMichael Walle	cpsw3g_mdio_pins_default: cpsw3g-mdio-default-pins {
505*1c3c4df0SMichael Walle		pinctrl-single,pins = <
506*1c3c4df0SMichael Walle			J722S_IOPAD(0x160, PIN_OUTPUT, 0)	/* (AC24) MDIO0_MDC */
507*1c3c4df0SMichael Walle			J722S_IOPAD(0x15c, PIN_INPUT, 0)	/* (AD25) MDIO0_MDIO */
508*1c3c4df0SMichael Walle		>;
509*1c3c4df0SMichael Walle	};
510*1c3c4df0SMichael Walle
511*1c3c4df0SMichael Walle	cpsw3g_pins_default: cpsw3g-default-pins {
512*1c3c4df0SMichael Walle		pinctrl-single,pins = <
513*1c3c4df0SMichael Walle			J722S_IOPAD(0x1b8, PIN_OUTPUT, 1)	/* (C20) SPI0_CS1.CP_GEMAC_CPTS0_TS_COMP */
514*1c3c4df0SMichael Walle		>;
515*1c3c4df0SMichael Walle	};
516*1c3c4df0SMichael Walle
517*1c3c4df0SMichael Walle	edp_bridge_pins_default: edp-bridge-default-pins {
518*1c3c4df0SMichael Walle		pinctrl-single,pins = <
519*1c3c4df0SMichael Walle			J722S_IOPAD(0x098, PIN_OUTPUT, 7)	/* (V21) GPMC0_WAIT0.GPIO0_37 */
520*1c3c4df0SMichael Walle			J722S_IOPAD(0x09c, PIN_INPUT, 7)	/* (W26) GPMC0_WAIT1.GPIO0_38 */
521*1c3c4df0SMichael Walle		>;
522*1c3c4df0SMichael Walle	};
523*1c3c4df0SMichael Walle
524*1c3c4df0SMichael Walle	i2c_mux_pins_default: i2c-mux-default-pins {
525*1c3c4df0SMichael Walle		pinctrl-single,pins = <
526*1c3c4df0SMichael Walle			J722S_IOPAD(0x028, PIN_OUTPUT, 7)	/* (M27) OSPI0_D7.GPIO0_10 */
527*1c3c4df0SMichael Walle		>;
528*1c3c4df0SMichael Walle	};
529*1c3c4df0SMichael Walle
530*1c3c4df0SMichael Walle	lcd0_backlight_pins_default: lcd0-backlight-default-pins {
531*1c3c4df0SMichael Walle		pinctrl-single,pins = <
532*1c3c4df0SMichael Walle			J722S_IOPAD(0x074, PIN_OUTPUT, 7)	/* (V22) GPMC0_AD14.GPIO0_29 */
533*1c3c4df0SMichael Walle			J722S_IOPAD(0x110, PIN_OUTPUT, 4)	/* (G27) MMC2_DAT1.EHRPWM1_A */
534*1c3c4df0SMichael Walle		>;
535*1c3c4df0SMichael Walle	};
536*1c3c4df0SMichael Walle
537*1c3c4df0SMichael Walle	lcd1_backlight_pins_default: lcd1-backlight-default-pins {
538*1c3c4df0SMichael Walle		pinctrl-single,pins = <
539*1c3c4df0SMichael Walle			J722S_IOPAD(0x1c0, PIN_OUTPUT, 7)	/* (E19) SPI0_D0.GPIO1_18 */
540*1c3c4df0SMichael Walle			J722S_IOPAD(0x114, PIN_OUTPUT, 4)	/* (G26) MMC2_DAT0.EHRPWM1_B */
541*1c3c4df0SMichael Walle		>;
542*1c3c4df0SMichael Walle	};
543*1c3c4df0SMichael Walle
544*1c3c4df0SMichael Walle	main_i2c0_pins_default: main-i2c0-default-pins {
545*1c3c4df0SMichael Walle		pinctrl-single,pins = <
546*1c3c4df0SMichael Walle			J722S_IOPAD(0x1e0, PIN_INPUT, 0)	/* (D23) I2C0_SCL */
547*1c3c4df0SMichael Walle			J722S_IOPAD(0x1e4, PIN_INPUT, 0)	/* (B22) I2C0_SDA */
548*1c3c4df0SMichael Walle		>;
549*1c3c4df0SMichael Walle		bootph-all;
550*1c3c4df0SMichael Walle	};
551*1c3c4df0SMichael Walle
552*1c3c4df0SMichael Walle	main_i2c2_pins_default: main-i2c2-default-pins {
553*1c3c4df0SMichael Walle		pinctrl-single,pins = <
554*1c3c4df0SMichael Walle			J722S_IOPAD(0x0b0, PIN_INPUT, 1)	/* (P22) GPMC0_CSn2.I2C2_SCL */
555*1c3c4df0SMichael Walle			J722S_IOPAD(0x0b4, PIN_INPUT, 1)	/* (P23) GPMC0_CSn3.I2C2_SDA */
556*1c3c4df0SMichael Walle		>;
557*1c3c4df0SMichael Walle	};
558*1c3c4df0SMichael Walle
559*1c3c4df0SMichael Walle	main_i2c3_pins_default: main-i2c3-default-pins {
560*1c3c4df0SMichael Walle		pinctrl-single,pins = <
561*1c3c4df0SMichael Walle			J722S_IOPAD(0x1d0, PIN_INPUT, 2)	/* (E22) UART0_CTSn.I2C3_SCL */
562*1c3c4df0SMichael Walle			J722S_IOPAD(0x1d4, PIN_INPUT, 2)	/* (B21) UART0_RTSn.I2C3_SDA */
563*1c3c4df0SMichael Walle		>;
564*1c3c4df0SMichael Walle	};
565*1c3c4df0SMichael Walle
566*1c3c4df0SMichael Walle	main_i2c4_pins_default: main-i2c4-default-pins {
567*1c3c4df0SMichael Walle		pinctrl-single,pins = <
568*1c3c4df0SMichael Walle			J722S_IOPAD(0x0a8, PIN_INPUT, 1)	/* (R27) GPMC0_CSn0.I2C4_SCL */
569*1c3c4df0SMichael Walle			J722S_IOPAD(0x0ac, PIN_INPUT, 1)	/* (P21) GPMC0_CSn1.I2C4_SDA */
570*1c3c4df0SMichael Walle		>;
571*1c3c4df0SMichael Walle	};
572*1c3c4df0SMichael Walle
573*1c3c4df0SMichael Walle	main_uart0_pins_default: main-uart0-default-pins {
574*1c3c4df0SMichael Walle		pinctrl-single,pins = <
575*1c3c4df0SMichael Walle			J722S_IOPAD(0x1c8, PIN_INPUT, 0)	/* (F19) UART0_RXD */
576*1c3c4df0SMichael Walle			J722S_IOPAD(0x1cc, PIN_OUTPUT, 0)	/* (F20) UART0_TXD */
577*1c3c4df0SMichael Walle		>;
578*1c3c4df0SMichael Walle		bootph-all;
579*1c3c4df0SMichael Walle	};
580*1c3c4df0SMichael Walle
581*1c3c4df0SMichael Walle	main_uart5_pins_default: main-uart5-default-pins {
582*1c3c4df0SMichael Walle		pinctrl-single,pins = <
583*1c3c4df0SMichael Walle			J722S_IOPAD(0x108, PIN_INPUT, 3)	/* (J27) MMC2_DAT3.UART5_RXD */
584*1c3c4df0SMichael Walle			J722S_IOPAD(0x10c, PIN_OUTPUT, 3)	/* (H27) MMC2_DAT2.UART5_TXD */
585*1c3c4df0SMichael Walle			J722S_IOPAD(0x008, PIN_INPUT, 5)	/* (L22) OSPI0_DQS.UART5_CTSn */
586*1c3c4df0SMichael Walle			J722S_IOPAD(0x004, PIN_OUTPUT, 5)	/* (L23) OSPI0_LBCLKO.UART5_RTSn */
587*1c3c4df0SMichael Walle		>;
588*1c3c4df0SMichael Walle	};
589*1c3c4df0SMichael Walle
590*1c3c4df0SMichael Walle	mcasp0_pins_default: mcasp0-default-pins {
591*1c3c4df0SMichael Walle		pinctrl-single,pins = <
592*1c3c4df0SMichael Walle			J722S_IOPAD(0x1a4, PIN_INPUT, 0)	/* (D25) MCASP0_ACLKX */
593*1c3c4df0SMichael Walle			J722S_IOPAD(0x1a8, PIN_INPUT, 0)	/* (C26) MCASP0_AFSX */
594*1c3c4df0SMichael Walle			J722S_IOPAD(0x1a0, PIN_INPUT, 0)	/* (F23) MCASP0_AXR0 */
595*1c3c4df0SMichael Walle			J722S_IOPAD(0x19c, PIN_OUTPUT, 0)	/* (B25) MCASP0_AXR1 */
596*1c3c4df0SMichael Walle		>;
597*1c3c4df0SMichael Walle	};
598*1c3c4df0SMichael Walle
599*1c3c4df0SMichael Walle	mcasp2_pins_default: mcasp2-default-pins {
600*1c3c4df0SMichael Walle		pinctrl-single,pins = <
601*1c3c4df0SMichael Walle			J722S_IOPAD(0x070, PIN_INPUT, 3)	/* (V24) GPMC0_AD13.MCASP2_ACLKX */
602*1c3c4df0SMichael Walle			J722S_IOPAD(0x06c, PIN_INPUT, 3)	/* (V26) GPMC0_AD12.MCASP2_AFSX */
603*1c3c4df0SMichael Walle			J722S_IOPAD(0x05c, PIN_INPUT, 3)	/* (U27) GPMC0_AD8.MCASP2_AXR0 */
604*1c3c4df0SMichael Walle			J722S_IOPAD(0x060, PIN_OUTPUT, 3)	/* (U26) GPMC0_AD9.MCASP2_AXR1 */
605*1c3c4df0SMichael Walle		>;
606*1c3c4df0SMichael Walle	};
607*1c3c4df0SMichael Walle
608*1c3c4df0SMichael Walle	oldi0_pins_default: oldi0-default-pins {
609*1c3c4df0SMichael Walle		pinctrl-single,pins = <
610*1c3c4df0SMichael Walle			J722S_IOPAD(0x260, PIN_OUTPUT, 0)	/* (AF23) OLDI0_A0N */
611*1c3c4df0SMichael Walle			J722S_IOPAD(0x25c, PIN_OUTPUT, 0)	/* (AG24) OLDI0_A0P */
612*1c3c4df0SMichael Walle			J722S_IOPAD(0x268, PIN_OUTPUT, 0)	/* (AG22) OLDI0_A1N */
613*1c3c4df0SMichael Walle			J722S_IOPAD(0x264, PIN_OUTPUT, 0)	/* (AG23) OLDI0_A1P */
614*1c3c4df0SMichael Walle			J722S_IOPAD(0x270, PIN_OUTPUT, 0)	/* (AB20) OLDI0_A2N */
615*1c3c4df0SMichael Walle			J722S_IOPAD(0x26c, PIN_OUTPUT, 0)	/* (AB21) OLDI0_A2P */
616*1c3c4df0SMichael Walle			J722S_IOPAD(0x278, PIN_OUTPUT, 0)	/* (AG20) OLDI0_A3N */
617*1c3c4df0SMichael Walle			J722S_IOPAD(0x274, PIN_OUTPUT, 0)	/* (AG21) OLDI0_A3P */
618*1c3c4df0SMichael Walle			J722S_IOPAD(0x2a0, PIN_OUTPUT, 0)	/* (AF21) OLDI0_CLK0N */
619*1c3c4df0SMichael Walle			J722S_IOPAD(0x29c, PIN_OUTPUT, 0)	/* (AE20) OLDI0_CLK0P */
620*1c3c4df0SMichael Walle		>;
621*1c3c4df0SMichael Walle	};
622*1c3c4df0SMichael Walle
623*1c3c4df0SMichael Walle	oldi1_pins_default: oldi1-default-pins {
624*1c3c4df0SMichael Walle		pinctrl-single,pins = <
625*1c3c4df0SMichael Walle			J722S_IOPAD(0x280, PIN_OUTPUT, 0)	/* (AD21) OLDI0_A4N */
626*1c3c4df0SMichael Walle			J722S_IOPAD(0x27c, PIN_OUTPUT, 0)	/* (AC21) OLDI0_A4P */
627*1c3c4df0SMichael Walle			J722S_IOPAD(0x288, PIN_OUTPUT, 0)	/* (AF19) OLDI0_A5N */
628*1c3c4df0SMichael Walle			J722S_IOPAD(0x284, PIN_OUTPUT, 0)	/* (AF18) OLDI0_A5P */
629*1c3c4df0SMichael Walle			J722S_IOPAD(0x290, PIN_OUTPUT, 0)	/* (AG17) OLDI0_A6N */
630*1c3c4df0SMichael Walle			J722S_IOPAD(0x28c, PIN_OUTPUT, 0)	/* (AG18) OLDI0_A6P */
631*1c3c4df0SMichael Walle			J722S_IOPAD(0x298, PIN_OUTPUT, 0)	/* (AB19) OLDI0_A7N */
632*1c3c4df0SMichael Walle			J722S_IOPAD(0x294, PIN_OUTPUT, 0)	/* (AA20) OLDI0_A7P */
633*1c3c4df0SMichael Walle			J722S_IOPAD(0x2a8, PIN_OUTPUT, 0)	/* (AD20) OLDI0_CLK1N */
634*1c3c4df0SMichael Walle			J722S_IOPAD(0x2a4, PIN_OUTPUT, 0)	/* (AE19) OLDI0_CLK1P */
635*1c3c4df0SMichael Walle		>;
636*1c3c4df0SMichael Walle	};
637*1c3c4df0SMichael Walle
638*1c3c4df0SMichael Walle	ospi0_pins_default: ospi0-default-pins {
639*1c3c4df0SMichael Walle		pinctrl-single,pins = <
640*1c3c4df0SMichael Walle			J722S_IOPAD(0x000, PIN_OUTPUT, 0)	/* (L24) OSPI0_CLK */
641*1c3c4df0SMichael Walle			J722S_IOPAD(0x02c, PIN_OUTPUT, 0)	/* (K26) OSPI0_CSn0 */
642*1c3c4df0SMichael Walle			J722S_IOPAD(0x030, PIN_OUTPUT, 0)	/* (K23) OSPI0_CSn1 */
643*1c3c4df0SMichael Walle			J722S_IOPAD(0x034, PIN_OUTPUT, 0)	/* (K22) OSPI0_CSn2 */
644*1c3c4df0SMichael Walle			J722S_IOPAD(0x00c, PIN_INPUT, 0)	/* (K27) OSPI0_D0 */
645*1c3c4df0SMichael Walle			J722S_IOPAD(0x010, PIN_INPUT, 0)	/* (L27) OSPI0_D1 */
646*1c3c4df0SMichael Walle			J722S_IOPAD(0x014, PIN_INPUT, 0)	/* (L26) OSPI0_D2 */
647*1c3c4df0SMichael Walle			J722S_IOPAD(0x018, PIN_INPUT, 0)	/* (L25) OSPI0_D3 */
648*1c3c4df0SMichael Walle		>;
649*1c3c4df0SMichael Walle		bootph-all;
650*1c3c4df0SMichael Walle	};
651*1c3c4df0SMichael Walle
652*1c3c4df0SMichael Walle	pcie0_rc_pins_default: pcie0-rc-default-pins {
653*1c3c4df0SMichael Walle		pinctrl-single,pins = <
654*1c3c4df0SMichael Walle			J722S_IOPAD(0x2ac, PIN_OUTPUT, 0)	/* (F25) PCIE0_CLKREQn */
655*1c3c4df0SMichael Walle			J722S_IOPAD(0x1b4, PIN_OUTPUT, 7)	/* (B20) SPI0_CS0.GPIO1_15 */
656*1c3c4df0SMichael Walle		>;
657*1c3c4df0SMichael Walle	};
658*1c3c4df0SMichael Walle
659*1c3c4df0SMichael Walle	pmic_irq_pins_default: pmic-irq-default-pins {
660*1c3c4df0SMichael Walle		pinctrl-single,pins = <
661*1c3c4df0SMichael Walle			J722S_IOPAD(0x090, PIN_INPUT, 7)	/* (P27) GPMC0_BE0n_CLE.GPIO0_35 */
662*1c3c4df0SMichael Walle		>;
663*1c3c4df0SMichael Walle	};
664*1c3c4df0SMichael Walle
665*1c3c4df0SMichael Walle	rgmii1_pins_default: rgmii1-default-pins {
666*1c3c4df0SMichael Walle		pinctrl-single,pins = <
667*1c3c4df0SMichael Walle			J722S_IOPAD(0x14c, PIN_INPUT, 0)	/* (AC25) RGMII1_RD0 */
668*1c3c4df0SMichael Walle			J722S_IOPAD(0x150, PIN_INPUT, 0)	/* (AD27) RGMII1_RD1 */
669*1c3c4df0SMichael Walle			J722S_IOPAD(0x154, PIN_INPUT, 0)	/* (AE24) RGMII1_RD2 */
670*1c3c4df0SMichael Walle			J722S_IOPAD(0x158, PIN_INPUT, 0)	/* (AE26) RGMII1_RD3 */
671*1c3c4df0SMichael Walle			J722S_IOPAD(0x148, PIN_INPUT, 0)	/* (AE27) RGMII1_RXC */
672*1c3c4df0SMichael Walle			J722S_IOPAD(0x144, PIN_INPUT, 0)	/* (AD23) RGMII1_RX_CTL */
673*1c3c4df0SMichael Walle			J722S_IOPAD(0x134, PIN_OUTPUT, 0)	/* (AF27) RGMII1_TD0 */
674*1c3c4df0SMichael Walle			J722S_IOPAD(0x138, PIN_OUTPUT, 0)	/* (AE23) RGMII1_TD1 */
675*1c3c4df0SMichael Walle			J722S_IOPAD(0x13c, PIN_OUTPUT, 0)	/* (AG25) RGMII1_TD2 */
676*1c3c4df0SMichael Walle			J722S_IOPAD(0x140, PIN_OUTPUT, 0)	/* (AF24) RGMII1_TD3 */
677*1c3c4df0SMichael Walle			J722S_IOPAD(0x130, PIN_OUTPUT, 0)	/* (AG26) RGMII1_TXC */
678*1c3c4df0SMichael Walle			J722S_IOPAD(0x12c, PIN_OUTPUT, 0)	/* (AF25) RGMII1_TX_CTL */
679*1c3c4df0SMichael Walle		>;
680*1c3c4df0SMichael Walle	};
681*1c3c4df0SMichael Walle
682*1c3c4df0SMichael Walle	rgmii2_pins_default: rgmii2-default-pins {
683*1c3c4df0SMichael Walle		pinctrl-single,pins = <
684*1c3c4df0SMichael Walle			J722S_IOPAD(0x0f8, PIN_INPUT, 2)	/* (AB24) VOUT0_HSYNC.RGMII2_RD0 */
685*1c3c4df0SMichael Walle			J722S_IOPAD(0x0fc, PIN_INPUT, 2)	/* (AC27) VOUT0_DE.RGMII2_RD1 */
686*1c3c4df0SMichael Walle			J722S_IOPAD(0x100, PIN_INPUT, 2)	/* (AB23) VOUT0_VSYNC.RGMII2_RD2 */
687*1c3c4df0SMichael Walle			J722S_IOPAD(0x104, PIN_INPUT, 2)	/* (AC26) VOUT0_PCLK.RGMII2_RD3 */
688*1c3c4df0SMichael Walle			J722S_IOPAD(0x0f4, PIN_INPUT, 2)	/* (AB27) VOUT0_DATA15.RGMII2_RXC */
689*1c3c4df0SMichael Walle			J722S_IOPAD(0x0f0, PIN_INPUT, 2)	/* (AB26) VOUT0_DATA14.RGMII2_RX_CTL */
690*1c3c4df0SMichael Walle			J722S_IOPAD(0x0e0, PIN_OUTPUT, 2)	/* (AA25) VOUT0_DATA10.RGMII2_TD0 */
691*1c3c4df0SMichael Walle			J722S_IOPAD(0x0e4, PIN_OUTPUT, 2)	/* (AB25) VOUT0_DATA11.RGMII2_TD1 */
692*1c3c4df0SMichael Walle			J722S_IOPAD(0x0e8, PIN_OUTPUT, 2)	/* (AA23) VOUT0_DATA12.RGMII2_TD2 */
693*1c3c4df0SMichael Walle			J722S_IOPAD(0x0ec, PIN_OUTPUT, 2)	/* (AA22) VOUT0_DATA13.RGMII2_TD3 */
694*1c3c4df0SMichael Walle			J722S_IOPAD(0x0dc, PIN_OUTPUT, 2)	/* (AA27) VOUT0_DATA9.RGMII2_TXC */
695*1c3c4df0SMichael Walle			J722S_IOPAD(0x0d8, PIN_OUTPUT, 2)	/* (AA24) VOUT0_DATA8.RGMII2_TX_CTL */
696*1c3c4df0SMichael Walle		>;
697*1c3c4df0SMichael Walle	};
698*1c3c4df0SMichael Walle
699*1c3c4df0SMichael Walle	rtc_pins_default: rtc-default-pins {
700*1c3c4df0SMichael Walle		pinctrl-single,pins = <
701*1c3c4df0SMichael Walle			J722S_IOPAD(0x094, PIN_INPUT, 7)	/* (P26) GPMC0_BE1n.GPIO0_36 */
702*1c3c4df0SMichael Walle		>;
703*1c3c4df0SMichael Walle	};
704*1c3c4df0SMichael Walle
705*1c3c4df0SMichael Walle	sdhci1_pins_default: sdhci1-default-pins {
706*1c3c4df0SMichael Walle		pinctrl-single,pins = <
707*1c3c4df0SMichael Walle			J722S_IOPAD(0x23c, PIN_INPUT, 0)	/* (H22) MMC1_CMD */
708*1c3c4df0SMichael Walle			J722S_IOPAD(0x234, PIN_OUTPUT, 0)	/* (H24) MMC1_CLK */
709*1c3c4df0SMichael Walle			J722S_IOPAD(0x230, PIN_INPUT, 0)	/* (H23) MMC1_DAT0 */
710*1c3c4df0SMichael Walle			J722S_IOPAD(0x22c, PIN_INPUT, 0)	/* (H20) MMC1_DAT1 */
711*1c3c4df0SMichael Walle			J722S_IOPAD(0x228, PIN_INPUT, 0)	/* (J23) MMC1_DAT2 */
712*1c3c4df0SMichael Walle			J722S_IOPAD(0x224, PIN_INPUT, 0)	/* (H25) MMC1_DAT3 */
713*1c3c4df0SMichael Walle			J722S_IOPAD(0x240, PIN_INPUT, 0)	/* (B24) MMC1_SDCD */
714*1c3c4df0SMichael Walle			J722S_IOPAD(0x244, PIN_INPUT, 0)	/* (A24) MMC1_SDWP */
715*1c3c4df0SMichael Walle		>;
716*1c3c4df0SMichael Walle		bootph-all;
717*1c3c4df0SMichael Walle	};
718*1c3c4df0SMichael Walle
719*1c3c4df0SMichael Walle	usb0_connector_pins_default: usb0-connector-default-pins {
720*1c3c4df0SMichael Walle		pinctrl-single,pins = <
721*1c3c4df0SMichael Walle			J722S_IOPAD(0x08c, PIN_INPUT_PULLUP, 7)	/* (N23) GPMC0_WEn.GPIO0_34 */
722*1c3c4df0SMichael Walle		>;
723*1c3c4df0SMichael Walle	};
724*1c3c4df0SMichael Walle
725*1c3c4df0SMichael Walle	usb1_pins_default: usb1-default-pins {
726*1c3c4df0SMichael Walle		pinctrl-single,pins = <
727*1c3c4df0SMichael Walle			J722S_IOPAD(0x258, PIN_OUTPUT, 0)	/* (B27) USB1_DRVVBUS */
728*1c3c4df0SMichael Walle		>;
729*1c3c4df0SMichael Walle	};
730*1c3c4df0SMichael Walle
731*1c3c4df0SMichael Walle	vcc_3p3_sd_s0_pins_default: vcc-3p3-sd-s0-default-pins {
732*1c3c4df0SMichael Walle		pinctrl-single,pins = <
733*1c3c4df0SMichael Walle			J722S_IOPAD(0x01c, PIN_OUTPUT, 7)	/* (L21) OSPI0_D4.GPIO0_7 */
734*1c3c4df0SMichael Walle		>;
735*1c3c4df0SMichael Walle		bootph-all;
736*1c3c4df0SMichael Walle	};
737*1c3c4df0SMichael Walle
738*1c3c4df0SMichael Walle	vcc_3p3_sd_vio_s0_pins_default: vcc-3p3-sd-vio-s0-default-pins {
739*1c3c4df0SMichael Walle		pinctrl-single,pins = <
740*1c3c4df0SMichael Walle			J722S_IOPAD(0x020, PIN_OUTPUT, 7)	/* (M26) OSPI0_D5.GPIO0_8 */
741*1c3c4df0SMichael Walle		>;
742*1c3c4df0SMichael Walle		bootph-all;
743*1c3c4df0SMichael Walle	};
744*1c3c4df0SMichael Walle
745*1c3c4df0SMichael Walle	vcc_3p3_cam_s0_pins_default: vcc-3p3-cam-s0-default-pins {
746*1c3c4df0SMichael Walle		pinctrl-single,pins = <
747*1c3c4df0SMichael Walle			J722S_IOPAD(0x1f0, PIN_OUTPUT, 7)	/* (A23) EXT_REFCLK1.GPIO1_30 */
748*1c3c4df0SMichael Walle		>;
749*1c3c4df0SMichael Walle	};
750*1c3c4df0SMichael Walle
751*1c3c4df0SMichael Walle	vcc_lcd0_panel_pins_default: vcc-lcd0-panel-default-pins {
752*1c3c4df0SMichael Walle		pinctrl-single,pins = <
753*1c3c4df0SMichael Walle			J722S_IOPAD(0x078, PIN_OUTPUT, 7)	/* (V23) GPMC0_AD15.GPIO0_30 */
754*1c3c4df0SMichael Walle		>;
755*1c3c4df0SMichael Walle	};
756*1c3c4df0SMichael Walle
757*1c3c4df0SMichael Walle	vcc_lcd1_panel_pins_default: vcc-lcd1-panel-default-pins {
758*1c3c4df0SMichael Walle		pinctrl-single,pins = <
759*1c3c4df0SMichael Walle			J722S_IOPAD(0x1c4, PIN_OUTPUT, 7)	/* (E20) SPI0_D1.GPIO1_19 */
760*1c3c4df0SMichael Walle		>;
761*1c3c4df0SMichael Walle	};
762*1c3c4df0SMichael Walle
763*1c3c4df0SMichael Walle	vcc_usb0_vbus_pins_default: vcc-usb0-vbus-default-pins {
764*1c3c4df0SMichael Walle		pinctrl-single,pins = <
765*1c3c4df0SMichael Walle			J722S_IOPAD(0x254, PIN_OUTPUT, 7)	/* (E25) USB0_DRVVBUS.GPIO1_50 */
766*1c3c4df0SMichael Walle		>;
767*1c3c4df0SMichael Walle	};
768*1c3c4df0SMichael Walle};
769*1c3c4df0SMichael Walle
770*1c3c4df0SMichael Walle/* SER1 */
771*1c3c4df0SMichael Walle&main_uart0 {
772*1c3c4df0SMichael Walle	pinctrl-names = "default";
773*1c3c4df0SMichael Walle	pinctrl-0 = <&main_uart0_pins_default>;
774*1c3c4df0SMichael Walle	bootph-all;
775*1c3c4df0SMichael Walle	status = "okay";
776*1c3c4df0SMichael Walle};
777*1c3c4df0SMichael Walle
778*1c3c4df0SMichael Walle/* SER2 */
779*1c3c4df0SMichael Walle&main_uart5 {
780*1c3c4df0SMichael Walle	pinctrl-names = "default";
781*1c3c4df0SMichael Walle	pinctrl-0 = <&main_uart5_pins_default>;
782*1c3c4df0SMichael Walle	bootph-all;
783*1c3c4df0SMichael Walle	status = "okay";
784*1c3c4df0SMichael Walle};
785*1c3c4df0SMichael Walle
786*1c3c4df0SMichael Walle/* I2S0 */
787*1c3c4df0SMichael Walle&mcasp0 {
788*1c3c4df0SMichael Walle	#sound-dai-cells = <0>;
789*1c3c4df0SMichael Walle	pinctrl-names = "default";
790*1c3c4df0SMichael Walle	pinctrl-0 = <&mcasp0_pins_default>;
791*1c3c4df0SMichael Walle	op-mode = <0>; /* I2S */
792*1c3c4df0SMichael Walle	tdm-slots = <2>;
793*1c3c4df0SMichael Walle	serial-dir = <2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0>;
794*1c3c4df0SMichael Walle};
795*1c3c4df0SMichael Walle
796*1c3c4df0SMichael Walle/* I2S2 */
797*1c3c4df0SMichael Walle&mcasp2 {
798*1c3c4df0SMichael Walle	#sound-dai-cells = <0>;
799*1c3c4df0SMichael Walle	pinctrl-names = "default";
800*1c3c4df0SMichael Walle	pinctrl-0 = <&mcasp2_pins_default>;
801*1c3c4df0SMichael Walle	op-mode = <0>; /* I2S */
802*1c3c4df0SMichael Walle	tdm-slots = <2>;
803*1c3c4df0SMichael Walle	serial-dir = <2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0>;
804*1c3c4df0SMichael Walle};
805*1c3c4df0SMichael Walle
806*1c3c4df0SMichael Walle/* CAN0 */
807*1c3c4df0SMichael Walle&mcu_mcan0 {
808*1c3c4df0SMichael Walle	pinctrl-names = "default";
809*1c3c4df0SMichael Walle	pinctrl-0 = <&mcu_mcan0_pins_default>;
810*1c3c4df0SMichael Walle	status = "okay";
811*1c3c4df0SMichael Walle};
812*1c3c4df0SMichael Walle
813*1c3c4df0SMichael Walle/* CAN1 */
814*1c3c4df0SMichael Walle&mcu_mcan1 {
815*1c3c4df0SMichael Walle	pinctrl-names = "default";
816*1c3c4df0SMichael Walle	pinctrl-0 = <&mcu_mcan1_pins_default>;
817*1c3c4df0SMichael Walle	status = "okay";
818*1c3c4df0SMichael Walle};
819*1c3c4df0SMichael Walle
820*1c3c4df0SMichael Walle&mcu_gpio0 {
821*1c3c4df0SMichael Walle	gpio-line-names =
822*1c3c4df0SMichael Walle		"", "", "", "", "", "", "", "", "", "", "", /* 10 */ "GPIO12",
823*1c3c4df0SMichael Walle		"MCU_INT#", "", "", "", "", "", "", "", "", "", "", "GPIO13";
824*1c3c4df0SMichael Walle};
825*1c3c4df0SMichael Walle
826*1c3c4df0SMichael Walle/* I2C_GP */
827*1c3c4df0SMichael Walle&mcu_i2c0 {
828*1c3c4df0SMichael Walle	pinctrl-names = "default";
829*1c3c4df0SMichael Walle	pinctrl-0 = <&mcu_i2c0_pins_default>;
830*1c3c4df0SMichael Walle	clock-frequency = <100000>;
831*1c3c4df0SMichael Walle	status = "okay";
832*1c3c4df0SMichael Walle
833*1c3c4df0SMichael Walle	/* SMARC Module EEPROM */
834*1c3c4df0SMichael Walle	eeprom@50 {
835*1c3c4df0SMichael Walle		compatible = "atmel,24c32";
836*1c3c4df0SMichael Walle		reg = <0x50>;
837*1c3c4df0SMichael Walle		pagesize = <32>;
838*1c3c4df0SMichael Walle		vcc-supply = <&vcc_1p8_s0>;
839*1c3c4df0SMichael Walle	};
840*1c3c4df0SMichael Walle};
841*1c3c4df0SMichael Walle
842*1c3c4df0SMichael Walle&mcu_pmx0 {
843*1c3c4df0SMichael Walle	mcu_i2c0_pins_default: mcu-i2c0-default-pins {
844*1c3c4df0SMichael Walle		pinctrl-single,pins = <
845*1c3c4df0SMichael Walle			J722S_MCU_IOPAD(0x044, PIN_INPUT, 0)	/* (B13) MCU_I2C0_SCL */
846*1c3c4df0SMichael Walle			J722S_MCU_IOPAD(0x048, PIN_INPUT, 0)	/* (E11) MCU_I2C0_SDA */
847*1c3c4df0SMichael Walle		>;
848*1c3c4df0SMichael Walle	};
849*1c3c4df0SMichael Walle	mcu_mcan0_pins_default: mcu-mcan0-default-pins {
850*1c3c4df0SMichael Walle		pinctrl-single,pins = <
851*1c3c4df0SMichael Walle			J722S_MCU_IOPAD(0x038, PIN_INPUT, 0)	/* (D8) MCU_MCAN0_RX */
852*1c3c4df0SMichael Walle			J722S_MCU_IOPAD(0x034, PIN_OUTPUT, 0)	/* (B2) MCU_MCAN0_TX */
853*1c3c4df0SMichael Walle		>;
854*1c3c4df0SMichael Walle	};
855*1c3c4df0SMichael Walle
856*1c3c4df0SMichael Walle	mcu_mcan1_pins_default: mcu-mcan1-default-pins {
857*1c3c4df0SMichael Walle		pinctrl-single,pins = <
858*1c3c4df0SMichael Walle			J722S_MCU_IOPAD(0x040, PIN_INPUT, 0)	/* (B1) MCU_MCAN1_RX */
859*1c3c4df0SMichael Walle			J722S_MCU_IOPAD(0x03c, PIN_OUTPUT, 0)	/* (C1) MCU_MCAN1_TX */
860*1c3c4df0SMichael Walle		>;
861*1c3c4df0SMichael Walle	};
862*1c3c4df0SMichael Walle
863*1c3c4df0SMichael Walle	mcu_uart0_pins_default: mcu-uart0-default-pins {
864*1c3c4df0SMichael Walle		pinctrl-single,pins = <
865*1c3c4df0SMichael Walle			J722S_MCU_IOPAD(0x014, PIN_INPUT, 0)	/* (B8) MCU_UART0_RXD */
866*1c3c4df0SMichael Walle			J722S_MCU_IOPAD(0x018, PIN_OUTPUT, 0)	/* (B4) MCU_UART0_TXD */
867*1c3c4df0SMichael Walle			J722S_MCU_IOPAD(0x01c, PIN_INPUT, 0)	/* (B5) MCU_UART0_CTSn */
868*1c3c4df0SMichael Walle			J722S_MCU_IOPAD(0x020, PIN_OUTPUT, 0)	/* (C5) MCU_UART0_RTSn */
869*1c3c4df0SMichael Walle		>;
870*1c3c4df0SMichael Walle		bootph-all;
871*1c3c4df0SMichael Walle	};
872*1c3c4df0SMichael Walle
873*1c3c4df0SMichael Walle	mcu_spi0_pins_default: mcu-spi0-default-pins {
874*1c3c4df0SMichael Walle		pinctrl-single,pins = <
875*1c3c4df0SMichael Walle			J722S_MCU_IOPAD(0x008, PIN_OUTPUT, 0)	/* (A9) MCU_SPI0_CLK */
876*1c3c4df0SMichael Walle			J722S_MCU_IOPAD(0x000, PIN_OUTPUT, 0)	/* (C12) MCU_SPI0_CS0 */
877*1c3c4df0SMichael Walle			J722S_MCU_IOPAD(0x004, PIN_OUTPUT, 0)	/* (A10) MCU_SPI0_CS1 */
878*1c3c4df0SMichael Walle			J722S_MCU_IOPAD(0x00c, PIN_INPUT, 0)	/* (B12) MCU_SPI0_D0 */
879*1c3c4df0SMichael Walle			J722S_MCU_IOPAD(0x010, PIN_OUTPUT, 0)	/* (C11) MCU_SPI0_D1 */
880*1c3c4df0SMichael Walle		>;
881*1c3c4df0SMichael Walle	};
882*1c3c4df0SMichael Walle
883*1c3c4df0SMichael Walle	wkup_uart0_pins_default: wkup-uart0-default-pins {
884*1c3c4df0SMichael Walle		pinctrl-single,pins = <
885*1c3c4df0SMichael Walle			J722S_MCU_IOPAD(0x024, PIN_INPUT, 0)	/* (B3) WKUP_UART0_RXD */
886*1c3c4df0SMichael Walle			J722S_MCU_IOPAD(0x028, PIN_OUTPUT, 0)	/* (C8) WKUP_UART0_TXD */
887*1c3c4df0SMichael Walle		>;
888*1c3c4df0SMichael Walle		bootph-all;
889*1c3c4df0SMichael Walle	};
890*1c3c4df0SMichael Walle
891*1c3c4df0SMichael Walle	wkup_i2c0_pins_default: wkup-i2c0-default-pins {
892*1c3c4df0SMichael Walle		pinctrl-single,pins = <
893*1c3c4df0SMichael Walle			J722S_MCU_IOPAD(0x04c, PIN_INPUT, 0)	/* (B9) WKUP_I2C0_SCL */
894*1c3c4df0SMichael Walle			J722S_MCU_IOPAD(0x050, PIN_INPUT, 0)	/* (D11) WKUP_I2C0_SDA */
895*1c3c4df0SMichael Walle		>;
896*1c3c4df0SMichael Walle	};
897*1c3c4df0SMichael Walle};
898*1c3c4df0SMichael Walle
899*1c3c4df0SMichael Walle/* SPI0 */
900*1c3c4df0SMichael Walle&mcu_spi0 {
901*1c3c4df0SMichael Walle	pinctrl-names = "default";
902*1c3c4df0SMichael Walle	pinctrl-0 = <&mcu_spi0_pins_default>;
903*1c3c4df0SMichael Walle};
904*1c3c4df0SMichael Walle
905*1c3c4df0SMichael Walle/* SER0 */
906*1c3c4df0SMichael Walle&mcu_uart0 {
907*1c3c4df0SMichael Walle	pinctrl-names = "default";
908*1c3c4df0SMichael Walle	pinctrl-0 = <&mcu_uart0_pins_default>;
909*1c3c4df0SMichael Walle	bootph-all;
910*1c3c4df0SMichael Walle	status = "okay";
911*1c3c4df0SMichael Walle};
912*1c3c4df0SMichael Walle
913*1c3c4df0SMichael Walle/* QSPI0 */
914*1c3c4df0SMichael Walle&ospi0 {
915*1c3c4df0SMichael Walle	pinctrl-0 = <&ospi0_pins_default>;
916*1c3c4df0SMichael Walle	pinctrl-names = "default";
917*1c3c4df0SMichael Walle	status = "okay";
918*1c3c4df0SMichael Walle
919*1c3c4df0SMichael Walle	flash@0 {
920*1c3c4df0SMichael Walle		compatible = "jedec,spi-nor";
921*1c3c4df0SMichael Walle		reg = <0>;
922*1c3c4df0SMichael Walle		spi-max-frequency = <104000000>;
923*1c3c4df0SMichael Walle		spi-rx-bus-width = <2>;
924*1c3c4df0SMichael Walle		spi-tx-bus-width = <2>;
925*1c3c4df0SMichael Walle		m25p,fast-read;
926*1c3c4df0SMichael Walle		cdns,tshsl-ns = <60>;
927*1c3c4df0SMichael Walle		cdns,tsd2d-ns = <60>;
928*1c3c4df0SMichael Walle		cdns,tchsh-ns = <60>;
929*1c3c4df0SMichael Walle		cdns,tslch-ns = <60>;
930*1c3c4df0SMichael Walle		cdns,read-delay = <3>;
931*1c3c4df0SMichael Walle		vcc-supply = <&vcc_1p8_s0>;
932*1c3c4df0SMichael Walle		bootph-all;
933*1c3c4df0SMichael Walle
934*1c3c4df0SMichael Walle		partitions {
935*1c3c4df0SMichael Walle			compatible = "fixed-partitions";
936*1c3c4df0SMichael Walle			#address-cells = <1>;
937*1c3c4df0SMichael Walle			#size-cells = <1>;
938*1c3c4df0SMichael Walle
939*1c3c4df0SMichael Walle			partition@0 {
940*1c3c4df0SMichael Walle				reg = <0x000000 0x400000>;
941*1c3c4df0SMichael Walle				label = "failsafe bootloader";
942*1c3c4df0SMichael Walle				read-only;
943*1c3c4df0SMichael Walle			};
944*1c3c4df0SMichael Walle		};
945*1c3c4df0SMichael Walle
946*1c3c4df0SMichael Walle		otp-1 {
947*1c3c4df0SMichael Walle			compatible = "user-otp";
948*1c3c4df0SMichael Walle
949*1c3c4df0SMichael Walle			nvmem-layout {
950*1c3c4df0SMichael Walle				compatible = "kontron,sa67-vpd", "kontron,sl28-vpd";
951*1c3c4df0SMichael Walle
952*1c3c4df0SMichael Walle				serial_number: serial-number {
953*1c3c4df0SMichael Walle				};
954*1c3c4df0SMichael Walle
955*1c3c4df0SMichael Walle				base_mac_address: base-mac-address {
956*1c3c4df0SMichael Walle					#nvmem-cell-cells = <1>;
957*1c3c4df0SMichael Walle				};
958*1c3c4df0SMichael Walle			};
959*1c3c4df0SMichael Walle		};
960*1c3c4df0SMichael Walle	};
961*1c3c4df0SMichael Walle};
962*1c3c4df0SMichael Walle
963*1c3c4df0SMichael Walle&pcie0_rc {
964*1c3c4df0SMichael Walle	pinctrl-names = "default";
965*1c3c4df0SMichael Walle	pinctrl-0 = <&pcie0_rc_pins_default>;
966*1c3c4df0SMichael Walle
967*1c3c4df0SMichael Walle	/*
968*1c3c4df0SMichael Walle	 * This is low active, but the driver itself is broken and already
969*1c3c4df0SMichael Walle	 * inverts the logic.
970*1c3c4df0SMichael Walle	 */
971*1c3c4df0SMichael Walle	reset-gpios = <&main_gpio1 15 GPIO_ACTIVE_HIGH>;
972*1c3c4df0SMichael Walle	phys = <&serdes1_pcie>;
973*1c3c4df0SMichael Walle	phy-names = "pcie-phy";
974*1c3c4df0SMichael Walle	status = "okay";
975*1c3c4df0SMichael Walle};
976*1c3c4df0SMichael Walle
977*1c3c4df0SMichael Walle&sdhci0 {
978*1c3c4df0SMichael Walle	disable-wp;
979*1c3c4df0SMichael Walle	bootph-all;
980*1c3c4df0SMichael Walle	ti,driver-strength-ohm = <50>;
981*1c3c4df0SMichael Walle	status = "okay";
982*1c3c4df0SMichael Walle};
983*1c3c4df0SMichael Walle
984*1c3c4df0SMichael Walle/* SDIO */
985*1c3c4df0SMichael Walle&sdhci1 {
986*1c3c4df0SMichael Walle	pinctrl-names = "default";
987*1c3c4df0SMichael Walle	pinctrl-0 = <&sdhci1_pins_default>;
988*1c3c4df0SMichael Walle	vmmc-supply = <&vcc_3p3_sd_s0>;
989*1c3c4df0SMichael Walle	vqmmc-supply = <&vcc_3p3_sd_vio_s0>;
990*1c3c4df0SMichael Walle	bootph-all;
991*1c3c4df0SMichael Walle	cd-gpios = <&main_gpio1 48 GPIO_ACTIVE_LOW>;
992*1c3c4df0SMichael Walle	cd-debounce-delay-ms = <100>;
993*1c3c4df0SMichael Walle	ti,fails-without-test-cd;
994*1c3c4df0SMichael Walle	ti,driver-strength-ohm = <50>;
995*1c3c4df0SMichael Walle	status = "okay";
996*1c3c4df0SMichael Walle};
997*1c3c4df0SMichael Walle
998*1c3c4df0SMichael Walle&serdes_ln_ctrl {
999*1c3c4df0SMichael Walle	idle-states = <J722S_SERDES0_LANE0_USB>,
1000*1c3c4df0SMichael Walle		      <J722S_SERDES1_LANE0_PCIE0_LANE0>;
1001*1c3c4df0SMichael Walle};
1002*1c3c4df0SMichael Walle
1003*1c3c4df0SMichael Walle&serdes_wiz0 {
1004*1c3c4df0SMichael Walle	status = "okay";
1005*1c3c4df0SMichael Walle};
1006*1c3c4df0SMichael Walle
1007*1c3c4df0SMichael Walle&serdes_wiz1 {
1008*1c3c4df0SMichael Walle	status = "okay";
1009*1c3c4df0SMichael Walle};
1010*1c3c4df0SMichael Walle
1011*1c3c4df0SMichael Walle&serdes0 {
1012*1c3c4df0SMichael Walle	serdes0_usb3: phy@0 {
1013*1c3c4df0SMichael Walle		reg = <0>;
1014*1c3c4df0SMichael Walle		#phy-cells = <0>;
1015*1c3c4df0SMichael Walle		resets = <&serdes_wiz0 1>;
1016*1c3c4df0SMichael Walle		cdns,num-lanes = <1>;
1017*1c3c4df0SMichael Walle		cdns,phy-type = <PHY_TYPE_USB3>;
1018*1c3c4df0SMichael Walle	};
1019*1c3c4df0SMichael Walle};
1020*1c3c4df0SMichael Walle
1021*1c3c4df0SMichael Walle&serdes1 {
1022*1c3c4df0SMichael Walle	serdes1_pcie: phy@0 {
1023*1c3c4df0SMichael Walle		reg = <0>;
1024*1c3c4df0SMichael Walle		#phy-cells = <0>;
1025*1c3c4df0SMichael Walle		resets = <&serdes_wiz1 1>;
1026*1c3c4df0SMichael Walle		cdns,num-lanes = <1>;
1027*1c3c4df0SMichael Walle		cdns,phy-type = <PHY_TYPE_PCIE>;
1028*1c3c4df0SMichael Walle	};
1029*1c3c4df0SMichael Walle};
1030*1c3c4df0SMichael Walle
1031*1c3c4df0SMichael Walle&usb0 {
1032*1c3c4df0SMichael Walle	/* dual role is implemented but not a full featured OTG */
1033*1c3c4df0SMichael Walle	adp-disable;
1034*1c3c4df0SMichael Walle	hnp-disable;
1035*1c3c4df0SMichael Walle	srp-disable;
1036*1c3c4df0SMichael Walle	dr_mode = "otg";
1037*1c3c4df0SMichael Walle	usb-role-switch;
1038*1c3c4df0SMichael Walle	role-switch-default-mode = "peripheral";
1039*1c3c4df0SMichael Walle	status = "okay";
1040*1c3c4df0SMichael Walle
1041*1c3c4df0SMichael Walle	port {
1042*1c3c4df0SMichael Walle		usb0_hc: endpoint {
1043*1c3c4df0SMichael Walle			remote-endpoint = <&usb0_connector>;
1044*1c3c4df0SMichael Walle		};
1045*1c3c4df0SMichael Walle	};
1046*1c3c4df0SMichael Walle};
1047*1c3c4df0SMichael Walle
1048*1c3c4df0SMichael Walle&usb0_phy_ctrl {
1049*1c3c4df0SMichael Walle	/*
1050*1c3c4df0SMichael Walle	 * Keep this node in the SPL to be able to use the USB controller to
1051*1c3c4df0SMichael Walle	 * boot via DFU.
1052*1c3c4df0SMichael Walle	 */
1053*1c3c4df0SMichael Walle	bootph-all;
1054*1c3c4df0SMichael Walle};
1055*1c3c4df0SMichael Walle
1056*1c3c4df0SMichael Walle&usb1 {
1057*1c3c4df0SMichael Walle	pinctrl-names = "default";
1058*1c3c4df0SMichael Walle	pinctrl-0 = <&usb1_pins_default>;
1059*1c3c4df0SMichael Walle
1060*1c3c4df0SMichael Walle	dr_mode = "host";
1061*1c3c4df0SMichael Walle	maximum-speed = "super-speed";
1062*1c3c4df0SMichael Walle	phys = <&serdes0_usb3>;
1063*1c3c4df0SMichael Walle	phy-names = "cdns3,usb3-phy";
1064*1c3c4df0SMichael Walle};
1065*1c3c4df0SMichael Walle
1066*1c3c4df0SMichael Walle&usbss0 {
1067*1c3c4df0SMichael Walle	ti,vbus-divider;
1068*1c3c4df0SMichael Walle	status = "okay";
1069*1c3c4df0SMichael Walle};
1070*1c3c4df0SMichael Walle
1071*1c3c4df0SMichael Walle&usbss1 {
1072*1c3c4df0SMichael Walle	ti,vbus-divider;
1073*1c3c4df0SMichael Walle	status = "okay";
1074*1c3c4df0SMichael Walle};
1075*1c3c4df0SMichael Walle
1076*1c3c4df0SMichael Walle/* I2C_PM */
1077*1c3c4df0SMichael Walle&wkup_i2c0 {
1078*1c3c4df0SMichael Walle	pinctrl-names = "default";
1079*1c3c4df0SMichael Walle	pinctrl-0 = <&wkup_i2c0_pins_default>;
1080*1c3c4df0SMichael Walle	clock-frequency = <100000>;
1081*1c3c4df0SMichael Walle	status = "okay";
1082*1c3c4df0SMichael Walle};
1083*1c3c4df0SMichael Walle
1084*1c3c4df0SMichael Walle/* SER3 */
1085*1c3c4df0SMichael Walle&wkup_uart0 {
1086*1c3c4df0SMichael Walle	/* WKUP UART0 is used by Device Manager firmware */
1087*1c3c4df0SMichael Walle	pinctrl-names = "default";
1088*1c3c4df0SMichael Walle	pinctrl-0 = <&wkup_uart0_pins_default>;
1089*1c3c4df0SMichael Walle	bootph-all;
1090*1c3c4df0SMichael Walle	status = "reserved";
1091*1c3c4df0SMichael Walle};
1092