1*d4ab4a33SBeleswar Padhi// SPDX-License-Identifier: GPL-2.0-only OR MIT 2*d4ab4a33SBeleswar Padhi/** 3*d4ab4a33SBeleswar Padhi * Device Tree Source for enabling IPC using TI SDK firmware on AM62A SoCs 4*d4ab4a33SBeleswar Padhi * 5*d4ab4a33SBeleswar Padhi * Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ 6*d4ab4a33SBeleswar Padhi */ 7*d4ab4a33SBeleswar Padhi 8*d4ab4a33SBeleswar Padhi&reserved_memory { 9*d4ab4a33SBeleswar Padhi c7x_0_dma_memory_region: memory@99800000 { 10*d4ab4a33SBeleswar Padhi compatible = "shared-dma-pool"; 11*d4ab4a33SBeleswar Padhi reg = <0x00 0x99800000 0x00 0x100000>; 12*d4ab4a33SBeleswar Padhi no-map; 13*d4ab4a33SBeleswar Padhi }; 14*d4ab4a33SBeleswar Padhi 15*d4ab4a33SBeleswar Padhi c7x_0_memory_region: memory@99900000 { 16*d4ab4a33SBeleswar Padhi compatible = "shared-dma-pool"; 17*d4ab4a33SBeleswar Padhi reg = <0x00 0x99900000 0x00 0xf00000>; 18*d4ab4a33SBeleswar Padhi no-map; 19*d4ab4a33SBeleswar Padhi }; 20*d4ab4a33SBeleswar Padhi 21*d4ab4a33SBeleswar Padhi mcu_r5fss0_core0_dma_memory_region: memory@9b800000 { 22*d4ab4a33SBeleswar Padhi compatible = "shared-dma-pool"; 23*d4ab4a33SBeleswar Padhi reg = <0x00 0x9b800000 0x00 0x100000>; 24*d4ab4a33SBeleswar Padhi no-map; 25*d4ab4a33SBeleswar Padhi }; 26*d4ab4a33SBeleswar Padhi 27*d4ab4a33SBeleswar Padhi mcu_r5fss0_core0_memory_region: memory@9b900000 { 28*d4ab4a33SBeleswar Padhi compatible = "shared-dma-pool"; 29*d4ab4a33SBeleswar Padhi reg = <0x00 0x9b900000 0x00 0xf00000>; 30*d4ab4a33SBeleswar Padhi no-map; 31*d4ab4a33SBeleswar Padhi }; 32*d4ab4a33SBeleswar Padhi}; 33*d4ab4a33SBeleswar Padhi 34*d4ab4a33SBeleswar Padhi&mailbox0_cluster0 { 35*d4ab4a33SBeleswar Padhi status = "okay"; 36*d4ab4a33SBeleswar Padhi 37*d4ab4a33SBeleswar Padhi mbox_r5_0: mbox-r5-0 { 38*d4ab4a33SBeleswar Padhi ti,mbox-rx = <0 0 0>; 39*d4ab4a33SBeleswar Padhi ti,mbox-tx = <1 0 0>; 40*d4ab4a33SBeleswar Padhi }; 41*d4ab4a33SBeleswar Padhi}; 42*d4ab4a33SBeleswar Padhi 43*d4ab4a33SBeleswar Padhi&mailbox0_cluster1 { 44*d4ab4a33SBeleswar Padhi status = "okay"; 45*d4ab4a33SBeleswar Padhi 46*d4ab4a33SBeleswar Padhi mbox_c7x_0: mbox-c7x-0 { 47*d4ab4a33SBeleswar Padhi ti,mbox-rx = <0 0 0>; 48*d4ab4a33SBeleswar Padhi ti,mbox-tx = <1 0 0>; 49*d4ab4a33SBeleswar Padhi }; 50*d4ab4a33SBeleswar Padhi}; 51*d4ab4a33SBeleswar Padhi 52*d4ab4a33SBeleswar Padhi&mailbox0_cluster2 { 53*d4ab4a33SBeleswar Padhi status = "okay"; 54*d4ab4a33SBeleswar Padhi 55*d4ab4a33SBeleswar Padhi mbox_mcu_r5_0: mbox-mcu-r5-0 { 56*d4ab4a33SBeleswar Padhi ti,mbox-rx = <0 0 0>; 57*d4ab4a33SBeleswar Padhi ti,mbox-tx = <1 0 0>; 58*d4ab4a33SBeleswar Padhi }; 59*d4ab4a33SBeleswar Padhi}; 60*d4ab4a33SBeleswar Padhi 61*d4ab4a33SBeleswar Padhi&wkup_r5fss0 { 62*d4ab4a33SBeleswar Padhi status = "okay"; 63*d4ab4a33SBeleswar Padhi}; 64*d4ab4a33SBeleswar Padhi 65*d4ab4a33SBeleswar Padhi&wkup_r5fss0_core0 { 66*d4ab4a33SBeleswar Padhi mboxes = <&mailbox0_cluster0>, <&mbox_r5_0>; 67*d4ab4a33SBeleswar Padhi memory-region = <&wkup_r5fss0_core0_dma_memory_region>, 68*d4ab4a33SBeleswar Padhi <&wkup_r5fss0_core0_memory_region>; 69*d4ab4a33SBeleswar Padhi status = "okay"; 70*d4ab4a33SBeleswar Padhi}; 71*d4ab4a33SBeleswar Padhi 72*d4ab4a33SBeleswar Padhi&mcu_r5fss0 { 73*d4ab4a33SBeleswar Padhi status = "okay"; 74*d4ab4a33SBeleswar Padhi}; 75*d4ab4a33SBeleswar Padhi 76*d4ab4a33SBeleswar Padhi&mcu_r5fss0_core0 { 77*d4ab4a33SBeleswar Padhi mboxes = <&mailbox0_cluster2>, <&mbox_mcu_r5_0>; 78*d4ab4a33SBeleswar Padhi memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 79*d4ab4a33SBeleswar Padhi <&mcu_r5fss0_core0_memory_region>; 80*d4ab4a33SBeleswar Padhi status = "okay"; 81*d4ab4a33SBeleswar Padhi}; 82*d4ab4a33SBeleswar Padhi 83*d4ab4a33SBeleswar Padhi&c7x_0 { 84*d4ab4a33SBeleswar Padhi mboxes = <&mailbox0_cluster1>, <&mbox_c7x_0>; 85*d4ab4a33SBeleswar Padhi memory-region = <&c7x_0_dma_memory_region>, 86*d4ab4a33SBeleswar Padhi <&c7x_0_memory_region>; 87*d4ab4a33SBeleswar Padhi status = "okay"; 88*d4ab4a33SBeleswar Padhi}; 89*d4ab4a33SBeleswar Padhi 90*d4ab4a33SBeleswar Padhi/* main_rti4 is used by C7x DSP */ 91*d4ab4a33SBeleswar Padhi&main_rti4 { 92*d4ab4a33SBeleswar Padhi status = "reserved"; 93*d4ab4a33SBeleswar Padhi}; 94*d4ab4a33SBeleswar Padhi 95*d4ab4a33SBeleswar Padhi/* main_timer2 is used by C7x DSP */ 96*d4ab4a33SBeleswar Padhi&main_timer2 { 97*d4ab4a33SBeleswar Padhi status = "reserved"; 98*d4ab4a33SBeleswar Padhi}; 99