140658534SNiklas Cassel// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 240658534SNiklas Cassel/* 340658534SNiklas Cassel * DT-overlay to run the PCIe3_4L Dual Mode controller in Endpoint mode 440658534SNiklas Cassel * in the SRNS (Separate Reference Clock No Spread) configuration. 540658534SNiklas Cassel * 640658534SNiklas Cassel * NOTE: If using a setup with two ROCK 5B:s, with one board running in 740658534SNiklas Cassel * RC mode and the other board running in EP mode, see also the device 840658534SNiklas Cassel * tree overlay: rk3588-rock-5b-pcie-srns.dtso. 940658534SNiklas Cassel */ 1040658534SNiklas Cassel 1140658534SNiklas Cassel/dts-v1/; 1240658534SNiklas Cassel/plugin/; 1340658534SNiklas Cassel 1440658534SNiklas Cassel&pcie30phy { 1540658534SNiklas Cassel rockchip,rx-common-refclk-mode = <0 0 0 0>; 1640658534SNiklas Cassel}; 1740658534SNiklas Cassel 1840658534SNiklas Cassel&pcie3x4 { 1940658534SNiklas Cassel status = "disabled"; 2040658534SNiklas Cassel}; 2140658534SNiklas Cassel 2240658534SNiklas Cassel&pcie3x4_ep { 2340658534SNiklas Cassel vpcie3v3-supply = <&vcc3v3_pcie30>; 2440658534SNiklas Cassel status = "okay"; 2540658534SNiklas Cassel}; 26*7d1163fcSNiklas Cassel 27*7d1163fcSNiklas Cassel&mmu600_pcie { 28*7d1163fcSNiklas Cassel status = "disabled"; 29*7d1163fcSNiklas Cassel}; 30