1*9103e21eSFUKAUMI Naoki// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*9103e21eSFUKAUMI Naoki/* 3*9103e21eSFUKAUMI Naoki * Copyright (c) 2025 Radxa Computer (Shenzhen) Co., Ltd. 4*9103e21eSFUKAUMI Naoki */ 5*9103e21eSFUKAUMI Naoki 6*9103e21eSFUKAUMI Naoki#include <dt-bindings/leds/common.h> 7*9103e21eSFUKAUMI Naoki#include <dt-bindings/gpio/gpio.h> 8*9103e21eSFUKAUMI Naoki#include <dt-bindings/pinctrl/rockchip.h> 9*9103e21eSFUKAUMI Naoki#include <dt-bindings/soc/rockchip,vop2.h> 10*9103e21eSFUKAUMI Naoki#include "rk3568.dtsi" 11*9103e21eSFUKAUMI Naoki 12*9103e21eSFUKAUMI Naoki/ { 13*9103e21eSFUKAUMI Naoki aliases { 14*9103e21eSFUKAUMI Naoki mmc0 = &sdhci; 15*9103e21eSFUKAUMI Naoki mmc2 = &sdmmc2; 16*9103e21eSFUKAUMI Naoki }; 17*9103e21eSFUKAUMI Naoki 18*9103e21eSFUKAUMI Naoki gmac1_clkin: clock-125m { 19*9103e21eSFUKAUMI Naoki compatible = "fixed-clock"; 20*9103e21eSFUKAUMI Naoki clock-frequency = <125000000>; 21*9103e21eSFUKAUMI Naoki clock-output-names = "gmac1_clkin"; 22*9103e21eSFUKAUMI Naoki #clock-cells = <0>; 23*9103e21eSFUKAUMI Naoki }; 24*9103e21eSFUKAUMI Naoki 25*9103e21eSFUKAUMI Naoki leds-0 { 26*9103e21eSFUKAUMI Naoki compatible = "gpio-leds"; 27*9103e21eSFUKAUMI Naoki 28*9103e21eSFUKAUMI Naoki led-0 { 29*9103e21eSFUKAUMI Naoki color = <LED_COLOR_ID_GREEN>; 30*9103e21eSFUKAUMI Naoki default-state = "on"; 31*9103e21eSFUKAUMI Naoki function = LED_FUNCTION_POWER; 32*9103e21eSFUKAUMI Naoki gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; 33*9103e21eSFUKAUMI Naoki pinctrl-names = "default"; 34*9103e21eSFUKAUMI Naoki pinctrl-0 = <&gpio0_b4_led>; 35*9103e21eSFUKAUMI Naoki }; 36*9103e21eSFUKAUMI Naoki }; 37*9103e21eSFUKAUMI Naoki 38*9103e21eSFUKAUMI Naoki vcc3v3_sys: regulator-3v3-0 { 39*9103e21eSFUKAUMI Naoki compatible = "regulator-fixed"; 40*9103e21eSFUKAUMI Naoki regulator-name = "vcc3v3_sys"; 41*9103e21eSFUKAUMI Naoki regulator-always-on; 42*9103e21eSFUKAUMI Naoki regulator-boot-on; 43*9103e21eSFUKAUMI Naoki regulator-min-microvolt = <3300000>; 44*9103e21eSFUKAUMI Naoki regulator-max-microvolt = <3300000>; 45*9103e21eSFUKAUMI Naoki vin-supply = <&dc5v>; 46*9103e21eSFUKAUMI Naoki }; 47*9103e21eSFUKAUMI Naoki 48*9103e21eSFUKAUMI Naoki vcc_3v3_1: regulator-3v3-1 { 49*9103e21eSFUKAUMI Naoki compatible = "regulator-fixed"; 50*9103e21eSFUKAUMI Naoki regulator-name = "vcc_3v3_1"; 51*9103e21eSFUKAUMI Naoki regulator-always-on; 52*9103e21eSFUKAUMI Naoki regulator-boot-on; 53*9103e21eSFUKAUMI Naoki regulator-min-microvolt = <3300000>; 54*9103e21eSFUKAUMI Naoki regulator-max-microvolt = <3300000>; 55*9103e21eSFUKAUMI Naoki vin-supply = <&vcc3v3_sys>; 56*9103e21eSFUKAUMI Naoki }; 57*9103e21eSFUKAUMI Naoki 58*9103e21eSFUKAUMI Naoki sdio_pwrseq: sdio-pwrseq { 59*9103e21eSFUKAUMI Naoki compatible = "mmc-pwrseq-simple"; 60*9103e21eSFUKAUMI Naoki clocks = <&rk809 1>; 61*9103e21eSFUKAUMI Naoki clock-names = "ext_clock"; 62*9103e21eSFUKAUMI Naoki pinctrl-names = "default"; 63*9103e21eSFUKAUMI Naoki pinctrl-0 = <&wifi_reg_on_h_gpio3_d4>; 64*9103e21eSFUKAUMI Naoki reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; 65*9103e21eSFUKAUMI Naoki }; 66*9103e21eSFUKAUMI Naoki}; 67*9103e21eSFUKAUMI Naoki 68*9103e21eSFUKAUMI Naoki&cpu0 { 69*9103e21eSFUKAUMI Naoki cpu-supply = <&vdd_cpu>; 70*9103e21eSFUKAUMI Naoki}; 71*9103e21eSFUKAUMI Naoki 72*9103e21eSFUKAUMI Naoki&cpu1 { 73*9103e21eSFUKAUMI Naoki cpu-supply = <&vdd_cpu>; 74*9103e21eSFUKAUMI Naoki}; 75*9103e21eSFUKAUMI Naoki 76*9103e21eSFUKAUMI Naoki&cpu2 { 77*9103e21eSFUKAUMI Naoki cpu-supply = <&vdd_cpu>; 78*9103e21eSFUKAUMI Naoki}; 79*9103e21eSFUKAUMI Naoki 80*9103e21eSFUKAUMI Naoki&cpu3 { 81*9103e21eSFUKAUMI Naoki cpu-supply = <&vdd_cpu>; 82*9103e21eSFUKAUMI Naoki}; 83*9103e21eSFUKAUMI Naoki 84*9103e21eSFUKAUMI Naoki&gmac1 { 85*9103e21eSFUKAUMI Naoki assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; 86*9103e21eSFUKAUMI Naoki assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>; 87*9103e21eSFUKAUMI Naoki clock_in_out = "input"; 88*9103e21eSFUKAUMI Naoki phy-handle = <&rgmii_phy1>; 89*9103e21eSFUKAUMI Naoki phy-mode = "rgmii-id"; 90*9103e21eSFUKAUMI Naoki phy-supply = <&vcc_3v3_1>; 91*9103e21eSFUKAUMI Naoki pinctrl-names = "default"; 92*9103e21eSFUKAUMI Naoki pinctrl-0 = <&gmac1m1_miim 93*9103e21eSFUKAUMI Naoki &gmac1m1_clkinout 94*9103e21eSFUKAUMI Naoki &gmac1m1_rx_bus2 95*9103e21eSFUKAUMI Naoki &gmac1m1_tx_bus2 96*9103e21eSFUKAUMI Naoki &gmac1m1_rgmii_clk 97*9103e21eSFUKAUMI Naoki &gmac1m1_rgmii_bus>; 98*9103e21eSFUKAUMI Naoki}; 99*9103e21eSFUKAUMI Naoki 100*9103e21eSFUKAUMI Naoki&gpu { 101*9103e21eSFUKAUMI Naoki mali-supply = <&vdd_gpu>; 102*9103e21eSFUKAUMI Naoki status = "okay"; 103*9103e21eSFUKAUMI Naoki}; 104*9103e21eSFUKAUMI Naoki 105*9103e21eSFUKAUMI Naoki&hdmi { 106*9103e21eSFUKAUMI Naoki avdd-0v9-supply = <&vdda0v9_image>; 107*9103e21eSFUKAUMI Naoki avdd-1v8-supply = <&vcca1v8_image>; 108*9103e21eSFUKAUMI Naoki}; 109*9103e21eSFUKAUMI Naoki 110*9103e21eSFUKAUMI Naoki&hdmi_in { 111*9103e21eSFUKAUMI Naoki hdmi_in_vp0: endpoint { 112*9103e21eSFUKAUMI Naoki remote-endpoint = <&vp0_out_hdmi>; 113*9103e21eSFUKAUMI Naoki }; 114*9103e21eSFUKAUMI Naoki}; 115*9103e21eSFUKAUMI Naoki 116*9103e21eSFUKAUMI Naoki&hdmi_out { 117*9103e21eSFUKAUMI Naoki hdmi_out_con: endpoint { 118*9103e21eSFUKAUMI Naoki remote-endpoint = <&hdmi_con_in>; 119*9103e21eSFUKAUMI Naoki }; 120*9103e21eSFUKAUMI Naoki}; 121*9103e21eSFUKAUMI Naoki 122*9103e21eSFUKAUMI Naoki&i2c0 { 123*9103e21eSFUKAUMI Naoki status = "okay"; 124*9103e21eSFUKAUMI Naoki 125*9103e21eSFUKAUMI Naoki rk809: pmic@20 { 126*9103e21eSFUKAUMI Naoki compatible = "rockchip,rk809"; 127*9103e21eSFUKAUMI Naoki reg = <0x20>; 128*9103e21eSFUKAUMI Naoki #clock-cells = <1>; 129*9103e21eSFUKAUMI Naoki clock-output-names = "rk809-clkout1", "rk809-clkout2"; 130*9103e21eSFUKAUMI Naoki interrupt-parent = <&gpio0>; 131*9103e21eSFUKAUMI Naoki interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; 132*9103e21eSFUKAUMI Naoki pinctrl-names = "default"; 133*9103e21eSFUKAUMI Naoki pinctrl-0 = <&pmic_int_l>; 134*9103e21eSFUKAUMI Naoki system-power-controller; 135*9103e21eSFUKAUMI Naoki vcc1-supply = <&vcc3v3_sys>; 136*9103e21eSFUKAUMI Naoki vcc2-supply = <&vcc3v3_sys>; 137*9103e21eSFUKAUMI Naoki vcc3-supply = <&vcc3v3_sys>; 138*9103e21eSFUKAUMI Naoki vcc4-supply = <&vcc3v3_sys>; 139*9103e21eSFUKAUMI Naoki vcc5-supply = <&vcc3v3_sys>; 140*9103e21eSFUKAUMI Naoki vcc6-supply = <&vcc3v3_sys>; 141*9103e21eSFUKAUMI Naoki vcc7-supply = <&vcc3v3_sys>; 142*9103e21eSFUKAUMI Naoki vcc8-supply = <&vcc3v3_sys>; 143*9103e21eSFUKAUMI Naoki vcc9-supply = <&vcc3v3_sys>; 144*9103e21eSFUKAUMI Naoki wakeup-source; 145*9103e21eSFUKAUMI Naoki 146*9103e21eSFUKAUMI Naoki regulators { 147*9103e21eSFUKAUMI Naoki vdd_logic: DCDC_REG1 { 148*9103e21eSFUKAUMI Naoki regulator-name = "vdd_logic"; 149*9103e21eSFUKAUMI Naoki regulator-always-on; 150*9103e21eSFUKAUMI Naoki regulator-boot-on; 151*9103e21eSFUKAUMI Naoki regulator-initial-mode = <0x2>; 152*9103e21eSFUKAUMI Naoki regulator-min-microvolt = <500000>; 153*9103e21eSFUKAUMI Naoki regulator-max-microvolt = <1350000>; 154*9103e21eSFUKAUMI Naoki regulator-ramp-delay = <6001>; 155*9103e21eSFUKAUMI Naoki 156*9103e21eSFUKAUMI Naoki regulator-state-mem { 157*9103e21eSFUKAUMI Naoki regulator-off-in-suspend; 158*9103e21eSFUKAUMI Naoki }; 159*9103e21eSFUKAUMI Naoki }; 160*9103e21eSFUKAUMI Naoki 161*9103e21eSFUKAUMI Naoki vdd_gpu: DCDC_REG2 { 162*9103e21eSFUKAUMI Naoki regulator-name = "vdd_gpu"; 163*9103e21eSFUKAUMI Naoki regulator-initial-mode = <0x2>; 164*9103e21eSFUKAUMI Naoki regulator-min-microvolt = <500000>; 165*9103e21eSFUKAUMI Naoki regulator-max-microvolt = <1350000>; 166*9103e21eSFUKAUMI Naoki regulator-ramp-delay = <6001>; 167*9103e21eSFUKAUMI Naoki 168*9103e21eSFUKAUMI Naoki regulator-state-mem { 169*9103e21eSFUKAUMI Naoki regulator-off-in-suspend; 170*9103e21eSFUKAUMI Naoki }; 171*9103e21eSFUKAUMI Naoki }; 172*9103e21eSFUKAUMI Naoki 173*9103e21eSFUKAUMI Naoki vcc_ddr: DCDC_REG3 { 174*9103e21eSFUKAUMI Naoki regulator-name = "vcc_ddr"; 175*9103e21eSFUKAUMI Naoki regulator-always-on; 176*9103e21eSFUKAUMI Naoki regulator-boot-on; 177*9103e21eSFUKAUMI Naoki regulator-initial-mode = <0x2>; 178*9103e21eSFUKAUMI Naoki 179*9103e21eSFUKAUMI Naoki regulator-state-mem { 180*9103e21eSFUKAUMI Naoki regulator-on-in-suspend; 181*9103e21eSFUKAUMI Naoki }; 182*9103e21eSFUKAUMI Naoki }; 183*9103e21eSFUKAUMI Naoki 184*9103e21eSFUKAUMI Naoki vdd_npu: DCDC_REG4 { 185*9103e21eSFUKAUMI Naoki regulator-name = "vdd_npu"; 186*9103e21eSFUKAUMI Naoki regulator-initial-mode = <0x2>; 187*9103e21eSFUKAUMI Naoki regulator-min-microvolt = <500000>; 188*9103e21eSFUKAUMI Naoki regulator-max-microvolt = <1350000>; 189*9103e21eSFUKAUMI Naoki regulator-ramp-delay = <6001>; 190*9103e21eSFUKAUMI Naoki 191*9103e21eSFUKAUMI Naoki regulator-state-mem { 192*9103e21eSFUKAUMI Naoki regulator-off-in-suspend; 193*9103e21eSFUKAUMI Naoki }; 194*9103e21eSFUKAUMI Naoki }; 195*9103e21eSFUKAUMI Naoki 196*9103e21eSFUKAUMI Naoki dc1v8: vccio_flash: vcc_1v8: DCDC_REG5 { 197*9103e21eSFUKAUMI Naoki regulator-name = "vcc_1v8"; 198*9103e21eSFUKAUMI Naoki regulator-always-on; 199*9103e21eSFUKAUMI Naoki regulator-boot-on; 200*9103e21eSFUKAUMI Naoki regulator-min-microvolt = <1800000>; 201*9103e21eSFUKAUMI Naoki regulator-max-microvolt = <1800000>; 202*9103e21eSFUKAUMI Naoki 203*9103e21eSFUKAUMI Naoki regulator-state-mem { 204*9103e21eSFUKAUMI Naoki regulator-off-in-suspend; 205*9103e21eSFUKAUMI Naoki }; 206*9103e21eSFUKAUMI Naoki }; 207*9103e21eSFUKAUMI Naoki 208*9103e21eSFUKAUMI Naoki vdda0v9_image: LDO_REG1 { 209*9103e21eSFUKAUMI Naoki regulator-name = "vdda0v9_image"; 210*9103e21eSFUKAUMI Naoki regulator-min-microvolt = <900000>; 211*9103e21eSFUKAUMI Naoki regulator-max-microvolt = <900000>; 212*9103e21eSFUKAUMI Naoki 213*9103e21eSFUKAUMI Naoki regulator-state-mem { 214*9103e21eSFUKAUMI Naoki regulator-off-in-suspend; 215*9103e21eSFUKAUMI Naoki }; 216*9103e21eSFUKAUMI Naoki }; 217*9103e21eSFUKAUMI Naoki 218*9103e21eSFUKAUMI Naoki vdda_0v9: LDO_REG2 { 219*9103e21eSFUKAUMI Naoki regulator-name = "vdda_0v9"; 220*9103e21eSFUKAUMI Naoki regulator-always-on; 221*9103e21eSFUKAUMI Naoki regulator-boot-on; 222*9103e21eSFUKAUMI Naoki regulator-min-microvolt = <900000>; 223*9103e21eSFUKAUMI Naoki regulator-max-microvolt = <900000>; 224*9103e21eSFUKAUMI Naoki 225*9103e21eSFUKAUMI Naoki regulator-state-mem { 226*9103e21eSFUKAUMI Naoki regulator-off-in-suspend; 227*9103e21eSFUKAUMI Naoki }; 228*9103e21eSFUKAUMI Naoki }; 229*9103e21eSFUKAUMI Naoki 230*9103e21eSFUKAUMI Naoki vdda0v9_pmu: LDO_REG3 { 231*9103e21eSFUKAUMI Naoki regulator-name = "vdda0v9_pmu"; 232*9103e21eSFUKAUMI Naoki regulator-always-on; 233*9103e21eSFUKAUMI Naoki regulator-boot-on; 234*9103e21eSFUKAUMI Naoki regulator-min-microvolt = <900000>; 235*9103e21eSFUKAUMI Naoki regulator-max-microvolt = <900000>; 236*9103e21eSFUKAUMI Naoki 237*9103e21eSFUKAUMI Naoki regulator-state-mem { 238*9103e21eSFUKAUMI Naoki regulator-on-in-suspend; 239*9103e21eSFUKAUMI Naoki regulator-suspend-microvolt = <900000>; 240*9103e21eSFUKAUMI Naoki }; 241*9103e21eSFUKAUMI Naoki }; 242*9103e21eSFUKAUMI Naoki 243*9103e21eSFUKAUMI Naoki vccio_acodec: LDO_REG4 { 244*9103e21eSFUKAUMI Naoki regulator-name = "vccio_acodec"; 245*9103e21eSFUKAUMI Naoki regulator-min-microvolt = <3300000>; 246*9103e21eSFUKAUMI Naoki regulator-max-microvolt = <3300000>; 247*9103e21eSFUKAUMI Naoki 248*9103e21eSFUKAUMI Naoki regulator-state-mem { 249*9103e21eSFUKAUMI Naoki regulator-off-in-suspend; 250*9103e21eSFUKAUMI Naoki }; 251*9103e21eSFUKAUMI Naoki }; 252*9103e21eSFUKAUMI Naoki 253*9103e21eSFUKAUMI Naoki vccio_sd: LDO_REG5 { 254*9103e21eSFUKAUMI Naoki regulator-name = "vccio_sd"; 255*9103e21eSFUKAUMI Naoki regulator-always-on; 256*9103e21eSFUKAUMI Naoki regulator-boot-on; 257*9103e21eSFUKAUMI Naoki regulator-min-microvolt = <1800000>; 258*9103e21eSFUKAUMI Naoki regulator-max-microvolt = <3300000>; 259*9103e21eSFUKAUMI Naoki 260*9103e21eSFUKAUMI Naoki regulator-state-mem { 261*9103e21eSFUKAUMI Naoki regulator-off-in-suspend; 262*9103e21eSFUKAUMI Naoki }; 263*9103e21eSFUKAUMI Naoki }; 264*9103e21eSFUKAUMI Naoki 265*9103e21eSFUKAUMI Naoki vcc3v3_pmu: LDO_REG6 { 266*9103e21eSFUKAUMI Naoki regulator-name = "vcc3v3_pmu"; 267*9103e21eSFUKAUMI Naoki regulator-always-on; 268*9103e21eSFUKAUMI Naoki regulator-boot-on; 269*9103e21eSFUKAUMI Naoki regulator-min-microvolt = <3300000>; 270*9103e21eSFUKAUMI Naoki regulator-max-microvolt = <3300000>; 271*9103e21eSFUKAUMI Naoki 272*9103e21eSFUKAUMI Naoki regulator-state-mem { 273*9103e21eSFUKAUMI Naoki regulator-on-in-suspend; 274*9103e21eSFUKAUMI Naoki regulator-suspend-microvolt = <3300000>; 275*9103e21eSFUKAUMI Naoki }; 276*9103e21eSFUKAUMI Naoki }; 277*9103e21eSFUKAUMI Naoki 278*9103e21eSFUKAUMI Naoki vcca_1v8: LDO_REG7 { 279*9103e21eSFUKAUMI Naoki regulator-name = "vcca_1v8"; 280*9103e21eSFUKAUMI Naoki regulator-always-on; 281*9103e21eSFUKAUMI Naoki regulator-boot-on; 282*9103e21eSFUKAUMI Naoki regulator-min-microvolt = <1800000>; 283*9103e21eSFUKAUMI Naoki regulator-max-microvolt = <1800000>; 284*9103e21eSFUKAUMI Naoki 285*9103e21eSFUKAUMI Naoki regulator-state-mem { 286*9103e21eSFUKAUMI Naoki regulator-off-in-suspend; 287*9103e21eSFUKAUMI Naoki }; 288*9103e21eSFUKAUMI Naoki }; 289*9103e21eSFUKAUMI Naoki 290*9103e21eSFUKAUMI Naoki vcca1v8_pmu: LDO_REG8 { 291*9103e21eSFUKAUMI Naoki regulator-name = "vcca1v8_pmu"; 292*9103e21eSFUKAUMI Naoki regulator-always-on; 293*9103e21eSFUKAUMI Naoki regulator-boot-on; 294*9103e21eSFUKAUMI Naoki regulator-min-microvolt = <1800000>; 295*9103e21eSFUKAUMI Naoki regulator-max-microvolt = <1800000>; 296*9103e21eSFUKAUMI Naoki 297*9103e21eSFUKAUMI Naoki regulator-state-mem { 298*9103e21eSFUKAUMI Naoki regulator-on-in-suspend; 299*9103e21eSFUKAUMI Naoki regulator-suspend-microvolt = <1800000>; 300*9103e21eSFUKAUMI Naoki }; 301*9103e21eSFUKAUMI Naoki }; 302*9103e21eSFUKAUMI Naoki 303*9103e21eSFUKAUMI Naoki vcca1v8_image: LDO_REG9 { 304*9103e21eSFUKAUMI Naoki regulator-name = "vcca1v8_image"; 305*9103e21eSFUKAUMI Naoki regulator-min-microvolt = <1800000>; 306*9103e21eSFUKAUMI Naoki regulator-max-microvolt = <1800000>; 307*9103e21eSFUKAUMI Naoki 308*9103e21eSFUKAUMI Naoki regulator-state-mem { 309*9103e21eSFUKAUMI Naoki regulator-off-in-suspend; 310*9103e21eSFUKAUMI Naoki }; 311*9103e21eSFUKAUMI Naoki }; 312*9103e21eSFUKAUMI Naoki 313*9103e21eSFUKAUMI Naoki dc3v3: vcc_3v3: SWITCH_REG1 { 314*9103e21eSFUKAUMI Naoki regulator-name = "vcc_3v3"; 315*9103e21eSFUKAUMI Naoki regulator-always-on; 316*9103e21eSFUKAUMI Naoki regulator-boot-on; 317*9103e21eSFUKAUMI Naoki 318*9103e21eSFUKAUMI Naoki regulator-state-mem { 319*9103e21eSFUKAUMI Naoki regulator-off-in-suspend; 320*9103e21eSFUKAUMI Naoki }; 321*9103e21eSFUKAUMI Naoki }; 322*9103e21eSFUKAUMI Naoki 323*9103e21eSFUKAUMI Naoki vcc3v3_sd: SWITCH_REG2 { 324*9103e21eSFUKAUMI Naoki regulator-name = "vcc3v3_sd"; 325*9103e21eSFUKAUMI Naoki regulator-always-on; 326*9103e21eSFUKAUMI Naoki regulator-boot-on; 327*9103e21eSFUKAUMI Naoki 328*9103e21eSFUKAUMI Naoki regulator-state-mem { 329*9103e21eSFUKAUMI Naoki regulator-off-in-suspend; 330*9103e21eSFUKAUMI Naoki }; 331*9103e21eSFUKAUMI Naoki }; 332*9103e21eSFUKAUMI Naoki }; 333*9103e21eSFUKAUMI Naoki }; 334*9103e21eSFUKAUMI Naoki 335*9103e21eSFUKAUMI Naoki vdd_cpu: regulator@40 { 336*9103e21eSFUKAUMI Naoki compatible = "silergy,syr827"; 337*9103e21eSFUKAUMI Naoki reg = <0x40>; 338*9103e21eSFUKAUMI Naoki fcs,suspend-voltage-selector = <1>; 339*9103e21eSFUKAUMI Naoki regulator-name = "vdd_cpu"; 340*9103e21eSFUKAUMI Naoki regulator-always-on; 341*9103e21eSFUKAUMI Naoki regulator-boot-on; 342*9103e21eSFUKAUMI Naoki regulator-min-microvolt = <712500>; 343*9103e21eSFUKAUMI Naoki regulator-max-microvolt = <1390000>; 344*9103e21eSFUKAUMI Naoki regulator-ramp-delay = <2300>; 345*9103e21eSFUKAUMI Naoki vin-supply = <&dc5v>; 346*9103e21eSFUKAUMI Naoki }; 347*9103e21eSFUKAUMI Naoki}; 348*9103e21eSFUKAUMI Naoki 349*9103e21eSFUKAUMI Naoki&i2c2 { 350*9103e21eSFUKAUMI Naoki status = "okay"; 351*9103e21eSFUKAUMI Naoki 352*9103e21eSFUKAUMI Naoki eeprom@50 { 353*9103e21eSFUKAUMI Naoki compatible = "belling,bl24c16a", "atmel,24c16"; 354*9103e21eSFUKAUMI Naoki reg = <0x50>; 355*9103e21eSFUKAUMI Naoki pagesize = <16>; 356*9103e21eSFUKAUMI Naoki read-only; 357*9103e21eSFUKAUMI Naoki vcc-supply = <&gpio_vref>; 358*9103e21eSFUKAUMI Naoki }; 359*9103e21eSFUKAUMI Naoki}; 360*9103e21eSFUKAUMI Naoki 361*9103e21eSFUKAUMI Naoki&mdio1 { 362*9103e21eSFUKAUMI Naoki rgmii_phy1: ethernet-phy@0 { 363*9103e21eSFUKAUMI Naoki compatible = "ethernet-phy-id001c.c916"; 364*9103e21eSFUKAUMI Naoki reg = <0x0>; 365*9103e21eSFUKAUMI Naoki pinctrl-names = "default"; 366*9103e21eSFUKAUMI Naoki pinctrl-0 = <&gmac1_rstn_gpio3_b0>; // GPIO4_C3 367*9103e21eSFUKAUMI Naoki reset-assert-us = <20000>; 368*9103e21eSFUKAUMI Naoki reset-deassert-us = <100000>; 369*9103e21eSFUKAUMI Naoki reset-gpios = <&gpio4 RK_PC3 GPIO_ACTIVE_LOW>; 370*9103e21eSFUKAUMI Naoki }; 371*9103e21eSFUKAUMI Naoki}; 372*9103e21eSFUKAUMI Naoki 373*9103e21eSFUKAUMI Naoki&pinctrl { 374*9103e21eSFUKAUMI Naoki bluetooth { 375*9103e21eSFUKAUMI Naoki bt_reg_on_h_gpio4_b2: bt-reg-on-h-gpio4-b2 { 376*9103e21eSFUKAUMI Naoki rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 377*9103e21eSFUKAUMI Naoki }; 378*9103e21eSFUKAUMI Naoki 379*9103e21eSFUKAUMI Naoki bt_wake_host_h_gpio4_b4: bt-wake-host-h-gpio4-b4 { 380*9103e21eSFUKAUMI Naoki rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; 381*9103e21eSFUKAUMI Naoki }; 382*9103e21eSFUKAUMI Naoki 383*9103e21eSFUKAUMI Naoki host_wake_bt_h_gpio4_b5: host-wake-bt-h-gpio4-b5 { 384*9103e21eSFUKAUMI Naoki rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 385*9103e21eSFUKAUMI Naoki }; 386*9103e21eSFUKAUMI Naoki }; 387*9103e21eSFUKAUMI Naoki 388*9103e21eSFUKAUMI Naoki ethernet { 389*9103e21eSFUKAUMI Naoki gmac1_rstn_gpio3_b0: gmac1-rstn-gpio3-b0 { 390*9103e21eSFUKAUMI Naoki rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 391*9103e21eSFUKAUMI Naoki }; 392*9103e21eSFUKAUMI Naoki }; 393*9103e21eSFUKAUMI Naoki 394*9103e21eSFUKAUMI Naoki leds { 395*9103e21eSFUKAUMI Naoki gpio0_b4_led: gpio0-b4-led { 396*9103e21eSFUKAUMI Naoki rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; 397*9103e21eSFUKAUMI Naoki }; 398*9103e21eSFUKAUMI Naoki }; 399*9103e21eSFUKAUMI Naoki 400*9103e21eSFUKAUMI Naoki pcie { 401*9103e21eSFUKAUMI Naoki pcie20_clkreqnm2: pcie20_clkreqnm2 { 402*9103e21eSFUKAUMI Naoki rockchip,pins = <1 RK_PB0 4 &pcfg_pull_none>; 403*9103e21eSFUKAUMI Naoki }; 404*9103e21eSFUKAUMI Naoki 405*9103e21eSFUKAUMI Naoki pcie_nrst: pcie-nrst { 406*9103e21eSFUKAUMI Naoki rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 407*9103e21eSFUKAUMI Naoki }; 408*9103e21eSFUKAUMI Naoki }; 409*9103e21eSFUKAUMI Naoki 410*9103e21eSFUKAUMI Naoki pmic { 411*9103e21eSFUKAUMI Naoki pmic_int_l: pmic-int-l { 412*9103e21eSFUKAUMI Naoki rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; 413*9103e21eSFUKAUMI Naoki }; 414*9103e21eSFUKAUMI Naoki }; 415*9103e21eSFUKAUMI Naoki 416*9103e21eSFUKAUMI Naoki wifi { 417*9103e21eSFUKAUMI Naoki wifi_reg_on_h_gpio3_d4: wifi-reg-on-h-gpio3-d4 { 418*9103e21eSFUKAUMI Naoki rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; 419*9103e21eSFUKAUMI Naoki }; 420*9103e21eSFUKAUMI Naoki }; 421*9103e21eSFUKAUMI Naoki}; 422*9103e21eSFUKAUMI Naoki 423*9103e21eSFUKAUMI Naoki&pcie2x1 { 424*9103e21eSFUKAUMI Naoki pinctrl-names = "default"; 425*9103e21eSFUKAUMI Naoki pinctrl-0 = <&pcie20_clkreqnm2 &pcie_nrst>; 426*9103e21eSFUKAUMI Naoki reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; 427*9103e21eSFUKAUMI Naoki supports-clkreq; 428*9103e21eSFUKAUMI Naoki}; 429*9103e21eSFUKAUMI Naoki 430*9103e21eSFUKAUMI Naoki&pmu_io_domains { 431*9103e21eSFUKAUMI Naoki pmuio1-supply = <&vcc3v3_pmu>; 432*9103e21eSFUKAUMI Naoki pmuio2-supply = <&vcc_3v3>; 433*9103e21eSFUKAUMI Naoki vccio1-supply = <&vccio_acodec>; 434*9103e21eSFUKAUMI Naoki vccio2-supply = <&vccio_flash>; 435*9103e21eSFUKAUMI Naoki vccio3-supply = <&vccio_sd>; 436*9103e21eSFUKAUMI Naoki vccio4-supply = <&vcc_1v8>; 437*9103e21eSFUKAUMI Naoki vccio5-supply = <&vcc_3v3>; 438*9103e21eSFUKAUMI Naoki vccio6-supply = <&vcc_1v8>; 439*9103e21eSFUKAUMI Naoki vccio7-supply = <&vcc_3v3>; 440*9103e21eSFUKAUMI Naoki status = "okay"; 441*9103e21eSFUKAUMI Naoki}; 442*9103e21eSFUKAUMI Naoki 443*9103e21eSFUKAUMI Naoki&saradc { 444*9103e21eSFUKAUMI Naoki vref-supply = <&vcca_1v8>; 445*9103e21eSFUKAUMI Naoki status = "okay"; 446*9103e21eSFUKAUMI Naoki}; 447*9103e21eSFUKAUMI Naoki 448*9103e21eSFUKAUMI Naoki&sdhci { 449*9103e21eSFUKAUMI Naoki bus-width = <8>; 450*9103e21eSFUKAUMI Naoki cap-mmc-highspeed; 451*9103e21eSFUKAUMI Naoki mmc-hs200-1_8v; 452*9103e21eSFUKAUMI Naoki max-frequency = <200000000>; 453*9103e21eSFUKAUMI Naoki no-sd; 454*9103e21eSFUKAUMI Naoki no-sdio; 455*9103e21eSFUKAUMI Naoki non-removable; 456*9103e21eSFUKAUMI Naoki pinctrl-names = "default"; 457*9103e21eSFUKAUMI Naoki pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; 458*9103e21eSFUKAUMI Naoki vmmc-supply = <&vcc_3v3>; 459*9103e21eSFUKAUMI Naoki vqmmc-supply = <&vccio_flash>; 460*9103e21eSFUKAUMI Naoki status = "okay"; 461*9103e21eSFUKAUMI Naoki}; 462*9103e21eSFUKAUMI Naoki 463*9103e21eSFUKAUMI Naoki&sdmmc2 { 464*9103e21eSFUKAUMI Naoki #address-cells = <1>; 465*9103e21eSFUKAUMI Naoki bus-width = <4>; 466*9103e21eSFUKAUMI Naoki cap-sd-highspeed; 467*9103e21eSFUKAUMI Naoki cap-sdio-irq; 468*9103e21eSFUKAUMI Naoki disable-wp; 469*9103e21eSFUKAUMI Naoki keep-power-in-suspend; 470*9103e21eSFUKAUMI Naoki max-frequency = <200000000>; 471*9103e21eSFUKAUMI Naoki mmc-pwrseq = <&sdio_pwrseq>; 472*9103e21eSFUKAUMI Naoki no-mmc; 473*9103e21eSFUKAUMI Naoki no-sd; 474*9103e21eSFUKAUMI Naoki non-removable; 475*9103e21eSFUKAUMI Naoki pinctrl-names = "default"; 476*9103e21eSFUKAUMI Naoki pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_clk &sdmmc2m0_cmd>; 477*9103e21eSFUKAUMI Naoki sd-uhs-sdr104; 478*9103e21eSFUKAUMI Naoki #size-cells = <0>; 479*9103e21eSFUKAUMI Naoki status = "okay"; 480*9103e21eSFUKAUMI Naoki 481*9103e21eSFUKAUMI Naoki wifi@1 { 482*9103e21eSFUKAUMI Naoki compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac"; 483*9103e21eSFUKAUMI Naoki reg = <1>; 484*9103e21eSFUKAUMI Naoki }; 485*9103e21eSFUKAUMI Naoki}; 486*9103e21eSFUKAUMI Naoki 487*9103e21eSFUKAUMI Naoki&sfc { 488*9103e21eSFUKAUMI Naoki #address-cells = <1>; 489*9103e21eSFUKAUMI Naoki #size-cells = <0>; 490*9103e21eSFUKAUMI Naoki status = "okay"; 491*9103e21eSFUKAUMI Naoki 492*9103e21eSFUKAUMI Naoki flash@0 { 493*9103e21eSFUKAUMI Naoki compatible = "jedec,spi-nor"; 494*9103e21eSFUKAUMI Naoki reg = <0>; 495*9103e21eSFUKAUMI Naoki spi-max-frequency = <104000000>; 496*9103e21eSFUKAUMI Naoki spi-rx-bus-width = <4>; 497*9103e21eSFUKAUMI Naoki spi-tx-bus-width = <1>; 498*9103e21eSFUKAUMI Naoki vcc-supply = <&vccio_flash>; 499*9103e21eSFUKAUMI Naoki }; 500*9103e21eSFUKAUMI Naoki}; 501*9103e21eSFUKAUMI Naoki 502*9103e21eSFUKAUMI Naoki&tsadc { 503*9103e21eSFUKAUMI Naoki rockchip,hw-tshut-mode = <1>; 504*9103e21eSFUKAUMI Naoki rockchip,hw-tshut-polarity = <0>; 505*9103e21eSFUKAUMI Naoki status = "okay"; 506*9103e21eSFUKAUMI Naoki}; 507*9103e21eSFUKAUMI Naoki 508*9103e21eSFUKAUMI Naoki&uart2 { 509*9103e21eSFUKAUMI Naoki status = "okay"; 510*9103e21eSFUKAUMI Naoki}; 511*9103e21eSFUKAUMI Naoki 512*9103e21eSFUKAUMI Naoki&uart8 { 513*9103e21eSFUKAUMI Naoki dma-names = "tx", "rx"; 514*9103e21eSFUKAUMI Naoki pinctrl-names = "default"; 515*9103e21eSFUKAUMI Naoki pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn &uart8m0_rtsn>; 516*9103e21eSFUKAUMI Naoki uart-has-rtscts; 517*9103e21eSFUKAUMI Naoki status = "okay"; 518*9103e21eSFUKAUMI Naoki 519*9103e21eSFUKAUMI Naoki bluetooth { 520*9103e21eSFUKAUMI Naoki compatible = "brcm,bcm4345c5"; 521*9103e21eSFUKAUMI Naoki clocks = <&rk809 1>; 522*9103e21eSFUKAUMI Naoki clock-names = "lpo"; 523*9103e21eSFUKAUMI Naoki device-wakeup-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; 524*9103e21eSFUKAUMI Naoki host-wakeup-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; 525*9103e21eSFUKAUMI Naoki max-speed = <1500000>; 526*9103e21eSFUKAUMI Naoki pinctrl-names = "default"; 527*9103e21eSFUKAUMI Naoki pinctrl-0 = <&bt_reg_on_h_gpio4_b2 528*9103e21eSFUKAUMI Naoki &bt_wake_host_h_gpio4_b4 529*9103e21eSFUKAUMI Naoki &host_wake_bt_h_gpio4_b5>; 530*9103e21eSFUKAUMI Naoki shutdown-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; 531*9103e21eSFUKAUMI Naoki vbat-supply = <&vcc_3v3_1>; 532*9103e21eSFUKAUMI Naoki vddio-supply = <&vcc_1v8>; 533*9103e21eSFUKAUMI Naoki }; 534*9103e21eSFUKAUMI Naoki}; 535*9103e21eSFUKAUMI Naoki 536*9103e21eSFUKAUMI Naoki&usb_host0_xhci { 537*9103e21eSFUKAUMI Naoki extcon = <&usb2phy0>; 538*9103e21eSFUKAUMI Naoki maximum-speed = "high-speed"; 539*9103e21eSFUKAUMI Naoki phys = <&usb2phy0_otg>; 540*9103e21eSFUKAUMI Naoki phy-names = "usb2-phy"; 541*9103e21eSFUKAUMI Naoki}; 542*9103e21eSFUKAUMI Naoki 543*9103e21eSFUKAUMI Naoki&vop { 544*9103e21eSFUKAUMI Naoki assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; 545*9103e21eSFUKAUMI Naoki assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; 546*9103e21eSFUKAUMI Naoki status = "okay"; 547*9103e21eSFUKAUMI Naoki}; 548*9103e21eSFUKAUMI Naoki 549*9103e21eSFUKAUMI Naoki&vop_mmu { 550*9103e21eSFUKAUMI Naoki status = "okay"; 551*9103e21eSFUKAUMI Naoki}; 552*9103e21eSFUKAUMI Naoki 553*9103e21eSFUKAUMI Naoki&vp0 { 554*9103e21eSFUKAUMI Naoki vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { 555*9103e21eSFUKAUMI Naoki reg = <ROCKCHIP_VOP2_EP_HDMI0>; 556*9103e21eSFUKAUMI Naoki remote-endpoint = <&hdmi_in_vp0>; 557*9103e21eSFUKAUMI Naoki }; 558*9103e21eSFUKAUMI Naoki}; 559