1/* 2 * Device Tree Source for the Kingfisher (ULCB extension) board 3 * 4 * Copyright (C) 2017 Renesas Electronics Corp. 5 * Copyright (C) 2017 Cogent Embedded, Inc. 6 * 7 * This file is licensed under the terms of the GNU General Public License 8 * version 2. This program is licensed "as is" without any warranty of any 9 * kind, whether express or implied. 10 */ 11 12/ { 13 aliases { 14 serial1 = &hscif0; 15 serial2 = &scif1; 16 }; 17}; 18 19&can0 { 20 pinctrl-0 = <&can0_pins>; 21 pinctrl-names = "default"; 22 status = "okay"; 23}; 24 25&can1 { 26 pinctrl-0 = <&can1_pins>; 27 pinctrl-names = "default"; 28 status = "okay"; 29}; 30 31&ehci0 { 32 status = "okay"; 33}; 34 35&hscif0 { 36 pinctrl-0 = <&hscif0_pins>; 37 pinctrl-names = "default"; 38 uart-has-rtscts; 39 40 status = "okay"; 41}; 42 43&hsusb { 44 status = "okay"; 45}; 46 47&i2c2 { 48 gpio_exp_74: gpio@74 { 49 compatible = "ti,tca9539"; 50 reg = <0x74>; 51 gpio-controller; 52 #gpio-cells = <2>; 53 interrupt-controller; 54 interrupt-parent = <&gpio6>; 55 interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 56 }; 57 58 gpio_exp_75: gpio@75 { 59 compatible = "ti,tca9539"; 60 reg = <0x75>; 61 gpio-controller; 62 #gpio-cells = <2>; 63 interrupt-controller; 64 interrupt-parent = <&gpio6>; 65 interrupts = <4 IRQ_TYPE_EDGE_FALLING>; 66 }; 67 68 i2cswitch2: i2c-switch@71 { 69 compatible = "nxp,pca9548"; 70 #address-cells = <1>; 71 #size-cells = <0>; 72 reg = <0x71>; 73 reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; 74 }; 75}; 76 77&i2c4 { 78 gpio_exp_76: gpio@76 { 79 compatible = "ti,tca9539"; 80 reg = <0x76>; 81 gpio-controller; 82 #gpio-cells = <2>; 83 interrupt-controller; 84 interrupt-parent = <&gpio7>; 85 interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 86 }; 87 88 gpio_exp_77: gpio@77 { 89 compatible = "ti,tca9539"; 90 reg = <0x77>; 91 gpio-controller; 92 #gpio-cells = <2>; 93 interrupt-controller; 94 interrupt-parent = <&gpio5>; 95 interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 96 }; 97 98 i2cswitch4: i2c-switch@71 { 99 compatible = "nxp,pca9548"; 100 #address-cells = <1>; 101 #size-cells = <0>; 102 reg = <0x71>; 103 reset-gpios= <&gpio3 15 GPIO_ACTIVE_LOW>; 104 }; 105}; 106 107&ohci0 { 108 status = "okay"; 109}; 110 111&pcie_bus_clk { 112 clock-frequency = <100000000>; 113}; 114 115&pciec0 { 116 status = "okay"; 117}; 118 119&pciec1 { 120 status = "okay"; 121}; 122 123&pfc { 124 can0_pins: can0 { 125 groups = "can0_data_a"; 126 function = "can0"; 127 }; 128 129 can1_pins: can1 { 130 groups = "can1_data"; 131 function = "can1"; 132 }; 133 134 hscif0_pins: hscif0 { 135 groups = "hscif0_data", "hscif0_ctrl"; 136 function = "hscif0"; 137 }; 138 139 scif1_pins: scif1 { 140 groups = "scif1_data_b", "scif1_ctrl"; 141 function = "scif1"; 142 }; 143}; 144 145&scif1 { 146 pinctrl-0 = <&scif1_pins>; 147 pinctrl-names = "default"; 148 uart-has-rtscts; 149 150 status = "okay"; 151}; 152 153&xhci0 { 154 status = "okay"; 155}; 156