1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G2LC SMARC EVK parts 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 10 11/* 12 * DIP-Switch SW1 setting on SoM 13 * 1 : High; 0: Low 14 * SW1-2 : SW_SD0_DEV_SEL (1: eMMC; 0: uSD) 15 * SW1-3 : SW_SCIF_CAN (1: CAN1; 0: SCIF1) 16 * SW1-4 : SW_RSPI_CAN (1: CAN1; 0: RSPI1) 17 * SW1-5 : SW_I2S0_I2S1 (1: I2S2 (HDMI audio); 0: I2S0) 18 * Please change below macros according to SW1 setting 19 */ 20 21#define SW_SD0_DEV_SEL 1 22 23#define SW_SCIF_CAN 0 24#if (SW_SCIF_CAN) 25/* Due to HW routing, SW_RSPI_CAN is always 0 when SW_SCIF_CAN is set to 1 */ 26#define SW_RSPI_CAN 0 27#else 28/* Please set SW_RSPI_CAN. Default value is 1 */ 29#define SW_RSPI_CAN 1 30#endif 31 32#if (SW_SCIF_CAN & SW_RSPI_CAN) 33#error "Can not set 1 to both SW_SCIF_CAN and SW_RSPI_CAN due to HW routing" 34#endif 35 36#include "rzg2lc-smarc-som.dtsi" 37#include "rzg2lc-smarc-pinfunction.dtsi" 38#include "rz-smarc-common.dtsi" 39 40/* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */ 41#define PMOD1_SER0 1 42 43/ { 44 aliases { 45 serial1 = &scif1; 46 }; 47}; 48 49#if (SW_SCIF_CAN || SW_RSPI_CAN) 50&canfd { 51 pinctrl-0 = <&can1_pins>; 52 /delete-node/ channel@0; 53}; 54#else 55&canfd { 56 /delete-property/ pinctrl-0; 57 /delete-property/ pinctrl-names; 58 status = "disabled"; 59}; 60#endif 61 62/* 63 * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board 64 * SW1 should be at position 2->3 so that SER0_CTS# line is activated 65 * SW2 should be at position 2->3 so that SER0_TX line is activated 66 * SW3 should be at position 2->3 so that SER0_RX line is activated 67 * SW4 should be at position 2->3 so that SER0_RTS# line is activated 68 */ 69#if (!SW_SCIF_CAN && PMOD1_SER0) 70&scif1 { 71 pinctrl-0 = <&scif1_pins>; 72 pinctrl-names = "default"; 73 74 uart-has-rtscts; 75 status = "okay"; 76}; 77#endif 78