1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G2LC SMARC EVK parts 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 10 11#include "rzg2lc-smarc-pinfunction.dtsi" 12#include "rz-smarc-common.dtsi" 13 14 15/ { 16 aliases { 17 serial1 = &scif1; 18 i2c2 = &i2c2; 19 }; 20}; 21 22#if (SW_SCIF_CAN || SW_RSPI_CAN) 23&canfd { 24 pinctrl-0 = <&can1_pins>; 25 /delete-node/ channel@0; 26}; 27#else 28&canfd { 29 /delete-property/ pinctrl-0; 30 /delete-property/ pinctrl-names; 31 status = "disabled"; 32}; 33#endif 34 35&cpu_dai { 36 sound-dai = <&ssi0>; 37}; 38 39&i2c2 { 40 pinctrl-0 = <&i2c2_pins>; 41 pinctrl-names = "default"; 42 clock-frequency = <400000>; 43 44 status = "okay"; 45 46 wm8978: codec@1a { 47 compatible = "wlf,wm8978"; 48 #sound-dai-cells = <0>; 49 reg = <0x1a>; 50 }; 51}; 52 53/* 54 * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board 55 * SW1 should be at position 2->3 so that SER0_CTS# line is activated 56 * SW2 should be at position 2->3 so that SER0_TX line is activated 57 * SW3 should be at position 2->3 so that SER0_RX line is activated 58 * SW4 should be at position 2->3 so that SER0_RTS# line is activated 59 */ 60#if (!SW_SCIF_CAN && PMOD1_SER0) 61&scif1 { 62 pinctrl-0 = <&scif1_pins>; 63 pinctrl-names = "default"; 64 65 uart-has-rtscts; 66 status = "okay"; 67}; 68#endif 69 70&ssi0 { 71 pinctrl-0 = <&ssi0_pins>; 72 pinctrl-names = "default"; 73 74 status = "okay"; 75}; 76 77#if (SW_RSPI_CAN) 78&spi1 { 79 /delete-property/ pinctrl-0; 80 /delete-property/ pinctrl-names; 81 status = "disabled"; 82}; 83#endif 84 85&vccq_sdhi1 { 86 gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>; 87}; 88