1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G2LC SMARC SOM common parts 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/irqc-rzg2l.h> 10#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 11 12/ { 13 aliases { 14 ethernet0 = ð0; 15 }; 16 17 chosen { 18 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; 19 }; 20 21 memory@48000000 { 22 device_type = "memory"; 23 /* first 128MB is reserved for secure area. */ 24 reg = <0x0 0x48000000 0x0 0x38000000>; 25 }; 26 27 reg_1p8v: regulator-1p8v { 28 compatible = "regulator-fixed"; 29 regulator-name = "fixed-1.8V"; 30 regulator-min-microvolt = <1800000>; 31 regulator-max-microvolt = <1800000>; 32 regulator-boot-on; 33 regulator-always-on; 34 }; 35 36 reg_3p3v: regulator-3p3v { 37 compatible = "regulator-fixed"; 38 regulator-name = "fixed-3.3V"; 39 regulator-min-microvolt = <3300000>; 40 regulator-max-microvolt = <3300000>; 41 regulator-boot-on; 42 regulator-always-on; 43 }; 44 45 reg_1p1v: regulator-vdd-core { 46 compatible = "regulator-fixed"; 47 regulator-name = "fixed-1.1V"; 48 regulator-min-microvolt = <1100000>; 49 regulator-max-microvolt = <1100000>; 50 regulator-boot-on; 51 regulator-always-on; 52 }; 53 54 vccq_sdhi0: regulator-vccq-sdhi0 { 55 compatible = "regulator-gpio"; 56 57 regulator-name = "SDHI0 VccQ"; 58 regulator-min-microvolt = <1800000>; 59 regulator-max-microvolt = <3300000>; 60 states = <3300000 1>, <1800000 0>; 61 regulator-boot-on; 62 gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>; 63 regulator-always-on; 64 }; 65 66 /* 32.768kHz crystal */ 67 x2: x2-clock { 68 compatible = "fixed-clock"; 69 #clock-cells = <0>; 70 clock-frequency = <32768>; 71 }; 72}; 73 74ð0 { 75 pinctrl-0 = <ð0_pins>; 76 pinctrl-names = "default"; 77 phy-handle = <&phy0>; 78 phy-mode = "rgmii-id"; 79 status = "okay"; 80 81 phy0: ethernet-phy@7 { 82 compatible = "ethernet-phy-id0022.1640", 83 "ethernet-phy-ieee802.3-c22"; 84 reg = <7>; 85 interrupt-parent = <&irqc>; 86 interrupts = <RZG2L_IRQ0 IRQ_TYPE_LEVEL_LOW>; 87 rxc-skew-psec = <2400>; 88 txc-skew-psec = <2400>; 89 rxdv-skew-psec = <0>; 90 txen-skew-psec = <0>; 91 rxd0-skew-psec = <0>; 92 rxd1-skew-psec = <0>; 93 rxd2-skew-psec = <0>; 94 rxd3-skew-psec = <0>; 95 txd0-skew-psec = <0>; 96 txd1-skew-psec = <0>; 97 txd2-skew-psec = <0>; 98 txd3-skew-psec = <0>; 99 }; 100}; 101 102&extal_clk { 103 clock-frequency = <24000000>; 104}; 105 106&gpu { 107 mali-supply = <®_1p1v>; 108}; 109 110&i2c2 { 111 raa215300: pmic@12 { 112 compatible = "renesas,raa215300"; 113 reg = <0x12>, <0x6f>; 114 reg-names = "main", "rtc"; 115 116 clocks = <&x2>; 117 clock-names = "xin"; 118 }; 119}; 120 121&ostm1 { 122 status = "okay"; 123}; 124 125&ostm2 { 126 status = "okay"; 127}; 128 129&pinctrl { 130 eth0_pins: eth0 { 131 pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */ 132 <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */ 133 <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */ 134 <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */ 135 <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */ 136 <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */ 137 <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */ 138 <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */ 139 <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */ 140 <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */ 141 <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */ 142 <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */ 143 <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */ 144 <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */ 145 <RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */ 146 <RZG2L_PORT_PINMUX(0, 0, 1)>; /* IRQ0 */ 147 }; 148 149 gpio-sd0-pwr-en-hog { 150 gpio-hog; 151 gpios = <RZG2L_GPIO(18, 1) GPIO_ACTIVE_HIGH>; 152 output-high; 153 line-name = "gpio_sd0_pwr_en"; 154 }; 155 156 qspi0_pins: qspi0 { 157 qspi0-data { 158 pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3"; 159 power-source = <1800>; 160 }; 161 162 qspi0-ctrl { 163 pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#"; 164 power-source = <1800>; 165 }; 166 }; 167 168 /* 169 * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2] 170 * The below switch logic can be used to select the device between 171 * eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT. 172 * SW1[2] should be at OFF position to enable 64 GB eMMC 173 * SW1[2] should be at position ON to enable uSD card CN3 174 */ 175 gpio-sd0-dev-sel-hog { 176 gpio-hog; 177 gpios = <RZG2L_GPIO(40, 2) GPIO_ACTIVE_HIGH>; 178 output-high; 179 line-name = "gpio_sd0_dev_sel"; 180 }; 181 182 sdhi0_emmc_pins: sd0emmc { 183 sd0_emmc_data { 184 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", 185 "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7"; 186 power-source = <1800>; 187 }; 188 189 sd0_emmc_ctrl { 190 pins = "SD0_CLK", "SD0_CMD"; 191 power-source = <1800>; 192 }; 193 194 sd0_emmc_rst { 195 pins = "SD0_RST#"; 196 power-source = <1800>; 197 }; 198 }; 199 200 sdhi0_pins: sd0 { 201 sd0_data { 202 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; 203 power-source = <3300>; 204 }; 205 206 sd0_ctrl { 207 pins = "SD0_CLK", "SD0_CMD"; 208 power-source = <3300>; 209 }; 210 211 sd0_mux { 212 pinmux = <RZG2L_PORT_PINMUX(18, 0, 1)>; /* SD0_CD */ 213 }; 214 }; 215 216 sdhi0_pins_uhs: sd0_uhs { 217 sd0_data_uhs { 218 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; 219 power-source = <1800>; 220 }; 221 222 sd0_ctrl_uhs { 223 pins = "SD0_CLK", "SD0_CMD"; 224 power-source = <1800>; 225 }; 226 227 sd0_mux_uhs { 228 pinmux = <RZG2L_PORT_PINMUX(18, 0, 1)>; /* SD0_CD */ 229 }; 230 }; 231}; 232 233&sbc { 234 pinctrl-0 = <&qspi0_pins>; 235 pinctrl-names = "default"; 236 status = "okay"; 237 238 flash@0 { 239 compatible = "micron,mt25qu512a", "jedec,spi-nor"; 240 reg = <0>; 241 m25p,fast-read; 242 spi-max-frequency = <50000000>; 243 spi-rx-bus-width = <4>; 244 245 partitions { 246 compatible = "fixed-partitions"; 247 #address-cells = <1>; 248 #size-cells = <1>; 249 250 boot@0 { 251 reg = <0x00000000 0x2000000>; 252 read-only; 253 }; 254 user@2000000 { 255 reg = <0x2000000 0x2000000>; 256 }; 257 }; 258 }; 259}; 260 261#if (!SW_SD0_DEV_SEL) 262&sdhi0 { 263 pinctrl-0 = <&sdhi0_pins>; 264 pinctrl-1 = <&sdhi0_pins_uhs>; 265 pinctrl-names = "default", "state_uhs"; 266 267 vmmc-supply = <®_3p3v>; 268 vqmmc-supply = <&vccq_sdhi0>; 269 bus-width = <4>; 270 sd-uhs-sdr50; 271 sd-uhs-sdr104; 272 status = "okay"; 273}; 274#endif 275 276#if SW_SD0_DEV_SEL 277&sdhi0 { 278 pinctrl-0 = <&sdhi0_emmc_pins>; 279 pinctrl-1 = <&sdhi0_emmc_pins>; 280 pinctrl-names = "default", "state_uhs"; 281 282 vmmc-supply = <®_3p3v>; 283 vqmmc-supply = <®_1p8v>; 284 bus-width = <8>; 285 mmc-hs200-1_8v; 286 non-removable; 287 fixed-emmc-driver-type = <1>; 288 status = "okay"; 289}; 290#endif 291 292&wdt0 { 293 status = "okay"; 294 timeout-sec = <60>; 295}; 296 297&wdt1 { 298 status = "okay"; 299 timeout-sec = <60>; 300}; 301