xref: /linux/scripts/dtc/include-prefixes/arm64/renesas/rzg2lc-smarc-som.dtsi (revision 0c436dfe5c25d0931b164b944165259f95e5281f) 
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2LC SMARC SOM common parts
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
10#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
11
12/ {
13	aliases {
14		ethernet0 = &eth0;
15	};
16
17	chosen {
18		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
19	};
20
21	memory@48000000 {
22		device_type = "memory";
23		/* first 128MB is reserved for secure area. */
24		reg = <0x0 0x48000000 0x0 0x38000000>;
25	};
26
27	reg_1p8v: regulator-1p8v {
28		compatible = "regulator-fixed";
29		regulator-name = "fixed-1.8V";
30		regulator-min-microvolt = <1800000>;
31		regulator-max-microvolt = <1800000>;
32		regulator-boot-on;
33		regulator-always-on;
34	};
35
36	reg_3p3v: regulator-3p3v {
37		compatible = "regulator-fixed";
38		regulator-name = "fixed-3.3V";
39		regulator-min-microvolt = <3300000>;
40		regulator-max-microvolt = <3300000>;
41		regulator-boot-on;
42		regulator-always-on;
43	};
44
45	reg_1p1v: regulator-vdd-core {
46		compatible = "regulator-fixed";
47		regulator-name = "fixed-1.1V";
48		regulator-min-microvolt = <1100000>;
49		regulator-max-microvolt = <1100000>;
50		regulator-boot-on;
51		regulator-always-on;
52	};
53
54	vccq_sdhi0: regulator-vccq-sdhi0 {
55		compatible = "regulator-gpio";
56
57		regulator-name = "SDHI0 VccQ";
58		regulator-min-microvolt = <1800000>;
59		regulator-max-microvolt = <3300000>;
60		states = <3300000 1>, <1800000 0>;
61		regulator-boot-on;
62		gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
63		regulator-always-on;
64	};
65
66	/* 32.768kHz crystal */
67	x2: x2-clock {
68		compatible = "fixed-clock";
69		#clock-cells = <0>;
70		clock-frequency = <32768>;
71	};
72};
73
74&eth0 {
75	pinctrl-0 = <&eth0_pins>;
76	pinctrl-names = "default";
77	phy-handle = <&phy0>;
78	phy-mode = "rgmii-id";
79	status = "okay";
80
81	phy0: ethernet-phy@7 {
82		compatible = "ethernet-phy-id0022.1640",
83			     "ethernet-phy-ieee802.3-c22";
84		reg = <7>;
85		interrupt-parent = <&irqc>;
86		interrupts = <RZG2L_IRQ0 IRQ_TYPE_LEVEL_LOW>;
87		rxc-skew-psec = <2400>;
88		txc-skew-psec = <2400>;
89		rxdv-skew-psec = <0>;
90		txen-skew-psec = <0>;
91		rxd0-skew-psec = <0>;
92		rxd1-skew-psec = <0>;
93		rxd2-skew-psec = <0>;
94		rxd3-skew-psec = <0>;
95		txd0-skew-psec = <0>;
96		txd1-skew-psec = <0>;
97		txd2-skew-psec = <0>;
98		txd3-skew-psec = <0>;
99	};
100};
101
102&extal_clk {
103	clock-frequency = <24000000>;
104};
105
106&gpu {
107	mali-supply = <&reg_1p1v>;
108};
109
110&i2c2 {
111	raa215300: pmic@12 {
112		compatible = "renesas,raa215300";
113		reg = <0x12>, <0x6f>;
114		reg-names = "main", "rtc";
115
116		clocks = <&x2>;
117		clock-names = "xin";
118	};
119};
120
121&ostm1 {
122	status = "okay";
123};
124
125&ostm2 {
126	status = "okay";
127};
128
129&pinctrl {
130	eth0_pins: eth0 {
131		txc {
132			pinmux = <RZG2L_PORT_PINMUX(20, 0, 1)>; /* ET0_TXC */
133			power-source = <1800>;
134			output-enable;
135		};
136
137		mux {
138			pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
139				 <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
140				 <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
141				 <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
142				 <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
143				 <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
144				 <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
145				 <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
146				 <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
147				 <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
148				 <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
149				 <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
150				 <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
151				 <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
152			power-source = <1800>;
153		};
154
155		irq {
156			pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>;  /* IRQ0 */
157		};
158	};
159
160	gpio-sd0-pwr-en-hog {
161		gpio-hog;
162		gpios = <RZG2L_GPIO(18, 1) GPIO_ACTIVE_HIGH>;
163		output-high;
164		line-name = "gpio_sd0_pwr_en";
165	};
166
167	qspi0_pins: qspi0 {
168		qspi0-data {
169			pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3";
170			power-source = <1800>;
171		};
172
173		qspi0-ctrl {
174			pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#";
175			power-source = <1800>;
176		};
177	};
178
179	/*
180	 * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
181	 * The below switch logic can be used to select the device between
182	 * eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT.
183	 * SW1[2] should be at OFF position to enable 64 GB eMMC
184	 * SW1[2] should be at position ON to enable uSD card CN3
185	 */
186	gpio-sd0-dev-sel-hog {
187		gpio-hog;
188		gpios = <RZG2L_GPIO(40, 2) GPIO_ACTIVE_HIGH>;
189		output-high;
190		line-name = "gpio_sd0_dev_sel";
191	};
192
193	sdhi0_emmc_pins: sd0emmc {
194		sd0_emmc_data {
195			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
196			       "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
197			power-source = <1800>;
198		};
199
200		sd0_emmc_ctrl {
201			pins = "SD0_CLK", "SD0_CMD";
202			power-source = <1800>;
203		};
204
205		sd0_emmc_rst {
206			pins = "SD0_RST#";
207			power-source = <1800>;
208		};
209	};
210
211	sdhi0_pins: sd0 {
212		sd0_data {
213			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
214			power-source = <3300>;
215		};
216
217		sd0_ctrl {
218			pins = "SD0_CLK", "SD0_CMD";
219			power-source = <3300>;
220		};
221
222		sd0_mux {
223			pinmux = <RZG2L_PORT_PINMUX(18, 0, 1)>; /* SD0_CD */
224		};
225	};
226
227	sdhi0_pins_uhs: sd0_uhs {
228		sd0_data_uhs {
229			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
230			power-source = <1800>;
231		};
232
233		sd0_ctrl_uhs {
234			pins = "SD0_CLK", "SD0_CMD";
235			power-source = <1800>;
236		};
237
238		sd0_mux_uhs {
239			pinmux = <RZG2L_PORT_PINMUX(18, 0, 1)>; /* SD0_CD */
240		};
241	};
242};
243
244&sbc {
245	pinctrl-0 = <&qspi0_pins>;
246	pinctrl-names = "default";
247	status = "okay";
248
249	flash@0 {
250		compatible = "micron,mt25qu512a", "jedec,spi-nor";
251		reg = <0>;
252		m25p,fast-read;
253		spi-max-frequency = <50000000>;
254		spi-rx-bus-width = <4>;
255		spi-tx-bus-width = <4>;
256
257		partitions {
258			compatible = "fixed-partitions";
259			#address-cells = <1>;
260			#size-cells = <1>;
261
262			boot@0 {
263				reg = <0x00000000 0x2000000>;
264				read-only;
265			};
266			user@2000000 {
267				reg = <0x2000000 0x2000000>;
268			};
269		};
270	};
271};
272
273#if (!SW_SD0_DEV_SEL)
274&sdhi0 {
275	pinctrl-0 = <&sdhi0_pins>;
276	pinctrl-1 = <&sdhi0_pins_uhs>;
277	pinctrl-names = "default", "state_uhs";
278
279	vmmc-supply = <&reg_3p3v>;
280	vqmmc-supply = <&vccq_sdhi0>;
281	bus-width = <4>;
282	sd-uhs-sdr50;
283	sd-uhs-sdr104;
284	status = "okay";
285};
286#endif
287
288#if SW_SD0_DEV_SEL
289&sdhi0 {
290	pinctrl-0 = <&sdhi0_emmc_pins>;
291	pinctrl-1 = <&sdhi0_emmc_pins>;
292	pinctrl-names = "default", "state_uhs";
293
294	vmmc-supply = <&reg_3p3v>;
295	vqmmc-supply = <&reg_1p8v>;
296	bus-width = <8>;
297	mmc-hs200-1_8v;
298	non-removable;
299	fixed-emmc-driver-type = <1>;
300	status = "okay";
301};
302#endif
303
304&wdt0 {
305	status = "okay";
306	timeout-sec = <60>;
307};
308
309&wdt1 {
310	status = "okay";
311	timeout-sec = <60>;
312};
313