1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G2L SMARC SOM common parts 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 10 11/* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */ 12#define EMMC 1 13 14/* 15 * To enable uSD card on CN3, 16 * SW1[2] should be at position 3/ON. 17 * Disable eMMC by setting "#define EMMC 0" above. 18 */ 19#define SDHI (!EMMC) 20 21/ { 22 aliases { 23 ethernet0 = ð0; 24 ethernet1 = ð1; 25 }; 26 27 chosen { 28 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; 29 }; 30 31 memory@48000000 { 32 device_type = "memory"; 33 /* first 128MB is reserved for secure area. */ 34 reg = <0x0 0x48000000 0x0 0x78000000>; 35 }; 36 37 reg_1p8v: regulator0 { 38 compatible = "regulator-fixed"; 39 regulator-name = "fixed-1.8V"; 40 regulator-min-microvolt = <1800000>; 41 regulator-max-microvolt = <1800000>; 42 regulator-boot-on; 43 regulator-always-on; 44 }; 45 46 reg_3p3v: regulator1 { 47 compatible = "regulator-fixed"; 48 regulator-name = "fixed-3.3V"; 49 regulator-min-microvolt = <3300000>; 50 regulator-max-microvolt = <3300000>; 51 regulator-boot-on; 52 regulator-always-on; 53 }; 54 55 vccq_sdhi0: regulator-vccq-sdhi0 { 56 compatible = "regulator-gpio"; 57 58 regulator-name = "SDHI0 VccQ"; 59 regulator-min-microvolt = <1800000>; 60 regulator-max-microvolt = <3300000>; 61 states = <3300000 1>, <1800000 0>; 62 regulator-boot-on; 63 gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>; 64 regulator-always-on; 65 }; 66}; 67 68&adc { 69 pinctrl-0 = <&adc_pins>; 70 pinctrl-names = "default"; 71 status = "okay"; 72 73 /delete-node/ channel@6; 74 /delete-node/ channel@7; 75}; 76 77ð0 { 78 pinctrl-0 = <ð0_pins>; 79 pinctrl-names = "default"; 80 phy-handle = <&phy0>; 81 phy-mode = "rgmii-id"; 82 status = "okay"; 83 84 phy0: ethernet-phy@7 { 85 compatible = "ethernet-phy-id0022.1640", 86 "ethernet-phy-ieee802.3-c22"; 87 reg = <7>; 88 rxc-skew-psec = <2400>; 89 txc-skew-psec = <2400>; 90 rxdv-skew-psec = <0>; 91 txdv-skew-psec = <0>; 92 rxd0-skew-psec = <0>; 93 rxd1-skew-psec = <0>; 94 rxd2-skew-psec = <0>; 95 rxd3-skew-psec = <0>; 96 txd0-skew-psec = <0>; 97 txd1-skew-psec = <0>; 98 txd2-skew-psec = <0>; 99 txd3-skew-psec = <0>; 100 }; 101}; 102 103ð1 { 104 pinctrl-0 = <ð1_pins>; 105 pinctrl-names = "default"; 106 phy-handle = <&phy1>; 107 phy-mode = "rgmii-id"; 108 status = "okay"; 109 110 phy1: ethernet-phy@7 { 111 compatible = "ethernet-phy-id0022.1640", 112 "ethernet-phy-ieee802.3-c22"; 113 reg = <7>; 114 rxc-skew-psec = <2400>; 115 txc-skew-psec = <2400>; 116 rxdv-skew-psec = <0>; 117 txdv-skew-psec = <0>; 118 rxd0-skew-psec = <0>; 119 rxd1-skew-psec = <0>; 120 rxd2-skew-psec = <0>; 121 rxd3-skew-psec = <0>; 122 txd0-skew-psec = <0>; 123 txd1-skew-psec = <0>; 124 txd2-skew-psec = <0>; 125 txd3-skew-psec = <0>; 126 }; 127}; 128 129&extal_clk { 130 clock-frequency = <24000000>; 131}; 132 133&pinctrl { 134 adc_pins: adc { 135 pinmux = <RZG2L_PORT_PINMUX(9, 0, 2)>; /* ADC_TRG */ 136 }; 137 138 eth0_pins: eth0 { 139 pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */ 140 <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */ 141 <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */ 142 <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */ 143 <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */ 144 <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */ 145 <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */ 146 <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */ 147 <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */ 148 <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */ 149 <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */ 150 <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */ 151 <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */ 152 <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */ 153 <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */ 154 }; 155 156 eth1_pins: eth1 { 157 pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */ 158 <RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */ 159 <RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */ 160 <RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */ 161 <RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */ 162 <RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */ 163 <RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */ 164 <RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */ 165 <RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */ 166 <RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */ 167 <RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */ 168 <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */ 169 <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */ 170 <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */ 171 <RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */ 172 }; 173 174 gpio-sd0-pwr-en-hog { 175 gpio-hog; 176 gpios = <RZG2L_GPIO(4, 1) GPIO_ACTIVE_HIGH>; 177 output-high; 178 line-name = "gpio_sd0_pwr_en"; 179 }; 180 181 /* 182 * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2] 183 * The below switch logic can be used to select the device between 184 * eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT. 185 * SW1[2] should be at position 2/OFF to enable 64 GB eMMC 186 * SW1[2] should be at position 3/ON to enable uSD card CN3 187 */ 188 sd0-dev-sel-hog { 189 gpio-hog; 190 gpios = <RZG2L_GPIO(41, 1) GPIO_ACTIVE_HIGH>; 191 output-high; 192 line-name = "sd0_dev_sel"; 193 }; 194 195 sdhi0_emmc_pins: sd0emmc { 196 sd0_emmc_data { 197 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", 198 "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7"; 199 power-source = <1800>; 200 }; 201 202 sd0_emmc_ctrl { 203 pins = "SD0_CLK", "SD0_CMD"; 204 power-source = <1800>; 205 }; 206 207 sd0_emmc_rst { 208 pins = "SD0_RST#"; 209 power-source = <1800>; 210 }; 211 }; 212 213 sdhi0_pins: sd0 { 214 sd0_data { 215 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; 216 power-source = <3300>; 217 }; 218 219 sd0_ctrl { 220 pins = "SD0_CLK", "SD0_CMD"; 221 power-source = <3300>; 222 }; 223 224 sd0_mux { 225 pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */ 226 }; 227 }; 228 229 sdhi0_pins_uhs: sd0_uhs { 230 sd0_data_uhs { 231 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; 232 power-source = <1800>; 233 }; 234 235 sd0_ctrl_uhs { 236 pins = "SD0_CLK", "SD0_CMD"; 237 power-source = <1800>; 238 }; 239 240 sd0_mux_uhs { 241 pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */ 242 }; 243 }; 244}; 245 246#if SDHI 247&sdhi0 { 248 pinctrl-0 = <&sdhi0_pins>; 249 pinctrl-1 = <&sdhi0_pins_uhs>; 250 pinctrl-names = "default", "state_uhs"; 251 252 vmmc-supply = <®_3p3v>; 253 vqmmc-supply = <&vccq_sdhi0>; 254 bus-width = <4>; 255 sd-uhs-sdr50; 256 sd-uhs-sdr104; 257 status = "okay"; 258}; 259#endif 260 261#if EMMC 262&sdhi0 { 263 pinctrl-0 = <&sdhi0_emmc_pins>; 264 pinctrl-1 = <&sdhi0_emmc_pins>; 265 pinctrl-names = "default", "state_uhs"; 266 267 vmmc-supply = <®_3p3v>; 268 vqmmc-supply = <®_1p8v>; 269 bus-width = <8>; 270 mmc-hs200-1_8v; 271 non-removable; 272 fixed-emmc-driver-type = <1>; 273 status = "okay"; 274}; 275#endif 276