xref: /linux/scripts/dtc/include-prefixes/arm64/renesas/rzg2l-smarc-som.dtsi (revision 00d071e23c61b1be528227427da3f805feddef19) 
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2L SMARC SOM common parts
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
10
11/* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */
12#define EMMC	1
13
14/*
15 * To enable uSD card on CN3,
16 * SW1[2] should be at position 3/ON.
17 * Disable eMMC by setting "#define EMMC	0" above.
18 */
19#define SDHI	(!EMMC)
20
21/ {
22	aliases {
23		ethernet0 = &eth0;
24		ethernet1 = &eth1;
25	};
26
27	chosen {
28		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
29	};
30
31	memory@48000000 {
32		device_type = "memory";
33		/* first 128MB is reserved for secure area. */
34		reg = <0x0 0x48000000 0x0 0x78000000>;
35	};
36
37	reg_1p8v: regulator0 {
38		compatible = "regulator-fixed";
39		regulator-name = "fixed-1.8V";
40		regulator-min-microvolt = <1800000>;
41		regulator-max-microvolt = <1800000>;
42		regulator-boot-on;
43		regulator-always-on;
44	};
45
46	reg_3p3v: regulator1 {
47		compatible = "regulator-fixed";
48		regulator-name = "fixed-3.3V";
49		regulator-min-microvolt = <3300000>;
50		regulator-max-microvolt = <3300000>;
51		regulator-boot-on;
52		regulator-always-on;
53	};
54
55	vccq_sdhi0: regulator-vccq-sdhi0 {
56		compatible = "regulator-gpio";
57
58		regulator-name = "SDHI0 VccQ";
59		regulator-min-microvolt = <1800000>;
60		regulator-max-microvolt = <3300000>;
61		states = <3300000 1>, <1800000 0>;
62		regulator-boot-on;
63		gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
64		regulator-always-on;
65	};
66};
67
68&adc {
69	pinctrl-0 = <&adc_pins>;
70	pinctrl-names = "default";
71	status = "okay";
72
73	/delete-node/ channel@6;
74	/delete-node/ channel@7;
75};
76
77&eth0 {
78	pinctrl-0 = <&eth0_pins>;
79	pinctrl-names = "default";
80	phy-handle = <&phy0>;
81	phy-mode = "rgmii-id";
82	status = "okay";
83
84	phy0: ethernet-phy@7 {
85		compatible = "ethernet-phy-id0022.1640",
86			     "ethernet-phy-ieee802.3-c22";
87		reg = <7>;
88		rxc-skew-psec = <2400>;
89		txc-skew-psec = <2400>;
90		rxdv-skew-psec = <0>;
91		txdv-skew-psec = <0>;
92		rxd0-skew-psec = <0>;
93		rxd1-skew-psec = <0>;
94		rxd2-skew-psec = <0>;
95		rxd3-skew-psec = <0>;
96		txd0-skew-psec = <0>;
97		txd1-skew-psec = <0>;
98		txd2-skew-psec = <0>;
99		txd3-skew-psec = <0>;
100	};
101};
102
103&eth1 {
104	pinctrl-0 = <&eth1_pins>;
105	pinctrl-names = "default";
106	phy-handle = <&phy1>;
107	phy-mode = "rgmii-id";
108	status = "okay";
109
110	phy1: ethernet-phy@7 {
111		compatible = "ethernet-phy-id0022.1640",
112			     "ethernet-phy-ieee802.3-c22";
113		reg = <7>;
114		rxc-skew-psec = <2400>;
115		txc-skew-psec = <2400>;
116		rxdv-skew-psec = <0>;
117		txdv-skew-psec = <0>;
118		rxd0-skew-psec = <0>;
119		rxd1-skew-psec = <0>;
120		rxd2-skew-psec = <0>;
121		rxd3-skew-psec = <0>;
122		txd0-skew-psec = <0>;
123		txd1-skew-psec = <0>;
124		txd2-skew-psec = <0>;
125		txd3-skew-psec = <0>;
126	};
127};
128
129&extal_clk {
130	clock-frequency = <24000000>;
131};
132
133&ostm1 {
134	status = "okay";
135};
136
137&ostm2 {
138	status = "okay";
139};
140
141&pinctrl {
142	adc_pins: adc {
143		pinmux = <RZG2L_PORT_PINMUX(9, 0, 2)>; /* ADC_TRG */
144	};
145
146	eth0_pins: eth0 {
147		pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
148			 <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
149			 <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
150			 <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
151			 <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
152			 <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
153			 <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
154			 <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
155			 <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
156			 <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
157			 <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
158			 <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
159			 <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
160			 <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
161			 <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
162	};
163
164	eth1_pins: eth1 {
165		pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */
166			 <RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */
167			 <RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */
168			 <RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */
169			 <RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */
170			 <RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */
171			 <RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */
172			 <RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */
173			 <RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */
174			 <RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */
175			 <RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */
176			 <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
177			 <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
178			 <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
179			 <RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */
180	};
181
182	gpio-sd0-pwr-en-hog {
183		gpio-hog;
184		gpios = <RZG2L_GPIO(4, 1) GPIO_ACTIVE_HIGH>;
185		output-high;
186		line-name = "gpio_sd0_pwr_en";
187	};
188
189	/*
190	 * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
191	 * The below switch logic can be used to select the device between
192	 * eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT.
193	 * SW1[2] should be at position 2/OFF to enable 64 GB eMMC
194	 * SW1[2] should be at position 3/ON to enable uSD card CN3
195	 */
196	sd0-dev-sel-hog {
197		gpio-hog;
198		gpios = <RZG2L_GPIO(41, 1) GPIO_ACTIVE_HIGH>;
199		output-high;
200		line-name = "sd0_dev_sel";
201	};
202
203	sdhi0_emmc_pins: sd0emmc {
204		sd0_emmc_data {
205			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
206			       "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
207			power-source = <1800>;
208		};
209
210		sd0_emmc_ctrl {
211			pins = "SD0_CLK", "SD0_CMD";
212			power-source = <1800>;
213		};
214
215		sd0_emmc_rst {
216			pins = "SD0_RST#";
217			power-source = <1800>;
218		};
219	};
220
221	sdhi0_pins: sd0 {
222		sd0_data {
223			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
224			power-source = <3300>;
225		};
226
227		sd0_ctrl {
228			pins = "SD0_CLK", "SD0_CMD";
229			power-source = <3300>;
230		};
231
232		sd0_mux {
233			pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
234		};
235	};
236
237	sdhi0_pins_uhs: sd0_uhs {
238		sd0_data_uhs {
239			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
240			power-source = <1800>;
241		};
242
243		sd0_ctrl_uhs {
244			pins = "SD0_CLK", "SD0_CMD";
245			power-source = <1800>;
246		};
247
248		sd0_mux_uhs {
249			pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
250		};
251	};
252};
253
254#if SDHI
255&sdhi0 {
256	pinctrl-0 = <&sdhi0_pins>;
257	pinctrl-1 = <&sdhi0_pins_uhs>;
258	pinctrl-names = "default", "state_uhs";
259
260	vmmc-supply = <&reg_3p3v>;
261	vqmmc-supply = <&vccq_sdhi0>;
262	bus-width = <4>;
263	sd-uhs-sdr50;
264	sd-uhs-sdr104;
265	status = "okay";
266};
267#endif
268
269#if EMMC
270&sdhi0 {
271	pinctrl-0 = <&sdhi0_emmc_pins>;
272	pinctrl-1 = <&sdhi0_emmc_pins>;
273	pinctrl-names = "default", "state_uhs";
274
275	vmmc-supply = <&reg_3p3v>;
276	vqmmc-supply = <&reg_1p8v>;
277	bus-width = <8>;
278	mmc-hs200-1_8v;
279	non-removable;
280	fixed-emmc-driver-type = <1>;
281	status = "okay";
282};
283#endif
284