xref: /linux/scripts/dtc/include-prefixes/arm64/renesas/r9a09g077.dtsi (revision 0f048c878ee32a4259dbf28e0ad8fd0b71ee0085)

// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
 * Device Tree Source for the RZ/T2H SoC
 *
 * Copyright (C) 2025 Renesas Electronics Corp.
 */

#include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "renesas,r9a09g077";
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a55";
			reg = <0>;
			device_type = "cpu";
			next-level-cache = <&L3_CA55>;
			enable-method = "psci";
		};

		cpu1: cpu@100 {
			compatible = "arm,cortex-a55";
			reg = <0x100>;
			device_type = "cpu";
			next-level-cache = <&L3_CA55>;
			enable-method = "psci";
		};

		cpu2: cpu@200 {
			compatible = "arm,cortex-a55";
			reg = <0x200>;
			device_type = "cpu";
			next-level-cache = <&L3_CA55>;
			enable-method = "psci";
		};

		cpu3: cpu@300 {
			compatible = "arm,cortex-a55";
			reg = <0x300>;
			device_type = "cpu";
			next-level-cache = <&L3_CA55>;
			enable-method = "psci";
		};

		L3_CA55: cache-controller-0 {
			compatible = "cache";
			cache-unified;
			cache-size = <0x100000>;
			cache-level = <3>;
		};
	};

	extal_clk: extal {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by the board */
		clock-frequency = <0>;
	};

	psci {
		compatible = "arm,psci-1.0", "arm,psci-0.2";
		method = "smc";
	};

	soc: soc {
		compatible = "simple-bus";
		interrupt-parent = <&gic>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		sci0: serial@80005000 {
			compatible = "renesas,r9a09g077-rsci";
			reg = <0 0x80005000 0 0x400>;
			interrupts = <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 591 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 592 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "eri", "rxi", "txi", "tei";
			clocks = <&cpg CPG_MOD 8>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
			clock-names = "operation", "bus";
			power-domains = <&cpg>;
			status = "disabled";
		};

		sci1: serial@80005400 {
			compatible = "renesas,r9a09g077-rsci";
			reg = <0 0x80005400 0 0x400>;
			interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 595 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 596 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "eri", "rxi", "txi", "tei";
			clocks = <&cpg CPG_MOD 9>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
			clock-names = "operation", "bus";
			power-domains = <&cpg>;
			status = "disabled";
		};

		sci2: serial@80005800 {
			compatible = "renesas,r9a09g077-rsci";
			reg = <0 0x80005800 0 0x400>;
			interrupts = <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 599 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 600 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "eri", "rxi", "txi", "tei";
			clocks = <&cpg CPG_MOD 10>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
			clock-names = "operation", "bus";
			power-domains = <&cpg>;
			status = "disabled";
		};

		sci3: serial@80005c00 {
			compatible = "renesas,r9a09g077-rsci";
			reg = <0 0x80005c00 0 0x400>;
			interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "eri", "rxi", "txi", "tei";
			clocks = <&cpg CPG_MOD 11>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
			clock-names = "operation", "bus";
			power-domains = <&cpg>;
			status = "disabled";
		};

		sci4: serial@80006000 {
			compatible = "renesas,r9a09g077-rsci";
			reg = <0 0x80006000 0 0x400>;
			interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 607 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 608 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "eri", "rxi", "txi", "tei";
			clocks = <&cpg CPG_MOD 12>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
			clock-names = "operation", "bus";
			power-domains = <&cpg>;
			status = "disabled";
		};

		sci5: serial@81005000 {
			compatible = "renesas,r9a09g077-rsci";
			reg = <0 0x81005000 0 0x400>;
			interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 611 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 612 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "eri", "rxi", "txi", "tei";
			clocks = <&cpg CPG_MOD 600>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
			clock-names = "operation", "bus";
			power-domains = <&cpg>;
			status = "disabled";
		};

		wdt0: watchdog@80082000 {
			compatible = "renesas,r9a09g077-wdt";
			reg = <0 0x80082000 0 0x400>,
			      <0 0x81295100 0 0x04>;
			clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>;
			clock-names = "pclk";
			power-domains = <&cpg>;
			status = "disabled";
		};

		wdt1: watchdog@80082400 {
			compatible = "renesas,r9a09g077-wdt";
			reg = <0 0x80082400 0 0x400>,
			      <0 0x81295104 0 0x04>;
			clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>;
			clock-names = "pclk";
			power-domains = <&cpg>;
			status = "disabled";
		};

		wdt2: watchdog@80082800 {
			compatible = "renesas,r9a09g077-wdt";
			reg = <0 0x80082800 0 0x400>,
			      <0 0x81295108 0 0x04>;
			clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>;
			clock-names = "pclk";
			power-domains = <&cpg>;
			status = "disabled";
		};

		wdt3: watchdog@80082c00 {
			compatible = "renesas,r9a09g077-wdt";
			reg = <0 0x80082c00 0 0x400>,
			      <0 0x8129510c 0 0x04>;
			clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>;
			clock-names = "pclk";
			power-domains = <&cpg>;
			status = "disabled";
		};

		wdt4: watchdog@80083000 {
			compatible = "renesas,r9a09g077-wdt";
			reg = <0 0x80083000 0 0x400>,
			      <0 0x81295110 0 0x04>;
			clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>;
			clock-names = "pclk";
			power-domains = <&cpg>;
			status = "disabled";
		};

		wdt5: watchdog@80083400 {
			compatible = "renesas,r9a09g077-wdt";
			reg = <0 0x80083400 0 0x400>,
			      <0 0x81295114 0 0x04>;
			clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>;
			clock-names = "pclk";
			power-domains = <&cpg>;
			status = "disabled";
		};

		i2c0: i2c@80088000 {
			compatible = "renesas,riic-r9a09g077";
			reg = <0 0x80088000 0 0x400>;
			interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 615 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 616 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "eei", "rxi", "txi", "tei";
			clocks = <&cpg CPG_MOD 100>;
			power-domains = <&cpg>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c1: i2c@80088400 {
			compatible = "renesas,riic-r9a09g077";
			reg = <0 0x80088400 0 0x400>;
			interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 619 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 620 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "eei", "rxi", "txi", "tei";
			clocks = <&cpg CPG_MOD 101>;
			power-domains = <&cpg>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c2: i2c@81008000 {
			compatible = "renesas,riic-r9a09g077";
			reg = <0 0x81008000 0 0x400>;
			interrupts = <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 623 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 624 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "eei", "rxi", "txi", "tei";
			clocks = <&cpg CPG_MOD 601>;
			power-domains = <&cpg>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		cpg: clock-controller@80280000 {
			compatible = "renesas,r9a09g077-cpg-mssr";
			reg = <0 0x80280000 0 0x1000>,
			      <0 0x81280000 0 0x9000>;
			clocks = <&extal_clk>;
			clock-names = "extal";
			#clock-cells = <2>;
			#reset-cells = <1>;
			#power-domain-cells = <0>;
		};

		pinctrl: pinctrl@802c0000 {
			compatible = "renesas,r9a09g077-pinctrl";
			reg = <0 0x802c0000 0 0x10000>,
			      <0 0x812c0000 0 0x10000>,
			      <0 0x802b0000 0 0x10000>;
			reg-names = "nsr", "srs", "srn";
			clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 0 288>;
			power-domains = <&cpg>;
		};

		gic: interrupt-controller@83000000 {
			compatible = "arm,gic-v3";
			reg = <0x0 0x83000000 0 0x40000>,
			      <0x0 0x83040000 0 0x160000>;
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
		};

		ohci: usb@92040000 {
			compatible = "generic-ohci";
			reg = <0 0x92040000 0 0x100>;
			interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 408>;
			phys = <&usb2_phy 1>;
			phy-names = "usb";
			power-domains = <&cpg>;
			status = "disabled";
		};

		ehci: usb@92040100 {
			compatible = "generic-ehci";
			reg = <0 0x92040100 0 0x100>;
			interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 408>;
			phys = <&usb2_phy 2>;
			phy-names = "usb";
			companion = <&ohci>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		usb2_phy: usb-phy@92040200 {
			compatible = "renesas,usb2-phy-r9a09g077";
			reg = <0 0x92040200 0 0x700>;
			interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 408>,
				 <&cpg CPG_CORE R9A09G077_USB_CLK>;
			#phy-cells = <1>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		hsusb: usb@92041000 {
			compatible = "renesas,usbhs-r9a09g077";
			reg = <0 0x92041000 0 0x1000>;
			interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 408>;
			phys = <&usb2_phy 3>;
			phy-names = "usb";
			power-domains = <&cpg>;
			status = "disabled";
		};

		sdhi0: mmc@92080000  {
			compatible = "renesas,sdhi-r9a09g077",
				     "renesas,sdhi-r9a09g057";
			reg = <0x0 0x92080000 0 0x10000>;
			interrupts = <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 1212>,
				 <&cpg CPG_CORE R9A09G077_SDHI_CLKHS>;
			clock-names = "aclk", "clkh";
			power-domains = <&cpg>;
			status = "disabled";

			sdhi0_vqmmc: vqmmc-regulator {
				regulator-name = "SDHI0-VQMMC";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				status = "disabled";
			};
		};

		sdhi1: mmc@92090000 {
			compatible = "renesas,sdhi-r9a09g077",
				     "renesas,sdhi-r9a09g057";
			reg = <0x0 0x92090000 0 0x10000>;
			interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 1213>,
				 <&cpg CPG_CORE R9A09G077_SDHI_CLKHS>;
			clock-names = "aclk", "clkh";
			power-domains = <&cpg>;
			status = "disabled";

			sdhi1_vqmmc: vqmmc-regulator {
				regulator-name = "SDHI1-VQMMC";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				status = "disabled";
			};
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
				      <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
				      <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
				      <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
				      <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
	};
};