1*2fddca72SLad Prabhakar// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*2fddca72SLad Prabhakar/* 3*2fddca72SLad Prabhakar * Device Tree Source for the RZ/V2H EVK board 4*2fddca72SLad Prabhakar * 5*2fddca72SLad Prabhakar * Copyright (C) 2024 Renesas Electronics Corp. 6*2fddca72SLad Prabhakar */ 7*2fddca72SLad Prabhakar 8*2fddca72SLad Prabhakar/dts-v1/; 9*2fddca72SLad Prabhakar 10*2fddca72SLad Prabhakar#include "r9a09g057.dtsi" 11*2fddca72SLad Prabhakar 12*2fddca72SLad Prabhakar/ { 13*2fddca72SLad Prabhakar model = "Renesas RZ/V2H EVK Board based on r9a09g057h44"; 14*2fddca72SLad Prabhakar compatible = "renesas,rzv2h-evk", "renesas,r9a09g057h44", "renesas,r9a09g057"; 15*2fddca72SLad Prabhakar 16*2fddca72SLad Prabhakar aliases { 17*2fddca72SLad Prabhakar serial0 = &scif; 18*2fddca72SLad Prabhakar }; 19*2fddca72SLad Prabhakar 20*2fddca72SLad Prabhakar chosen { 21*2fddca72SLad Prabhakar bootargs = "ignore_loglevel"; 22*2fddca72SLad Prabhakar stdout-path = "serial0:115200n8"; 23*2fddca72SLad Prabhakar }; 24*2fddca72SLad Prabhakar 25*2fddca72SLad Prabhakar memory@48000000 { 26*2fddca72SLad Prabhakar device_type = "memory"; 27*2fddca72SLad Prabhakar /* first 128MB is reserved for secure area. */ 28*2fddca72SLad Prabhakar reg = <0x0 0x48000000 0x1 0xF8000000>; 29*2fddca72SLad Prabhakar }; 30*2fddca72SLad Prabhakar 31*2fddca72SLad Prabhakar memory@240000000 { 32*2fddca72SLad Prabhakar device_type = "memory"; 33*2fddca72SLad Prabhakar reg = <0x2 0x40000000 0x2 0x00000000>; 34*2fddca72SLad Prabhakar }; 35*2fddca72SLad Prabhakar}; 36*2fddca72SLad Prabhakar 37*2fddca72SLad Prabhakar&audio_extal_clk { 38*2fddca72SLad Prabhakar clock-frequency = <22579200>; 39*2fddca72SLad Prabhakar}; 40*2fddca72SLad Prabhakar 41*2fddca72SLad Prabhakar&pinctrl { 42*2fddca72SLad Prabhakar scif_pins: scif { 43*2fddca72SLad Prabhakar pins = "SCIF_TXD", "SCIF_RXD"; 44*2fddca72SLad Prabhakar renesas,output-impedance = <1>; 45*2fddca72SLad Prabhakar }; 46*2fddca72SLad Prabhakar}; 47*2fddca72SLad Prabhakar 48*2fddca72SLad Prabhakar&qextal_clk { 49*2fddca72SLad Prabhakar clock-frequency = <24000000>; 50*2fddca72SLad Prabhakar}; 51*2fddca72SLad Prabhakar 52*2fddca72SLad Prabhakar&rtxin_clk { 53*2fddca72SLad Prabhakar clock-frequency = <32768>; 54*2fddca72SLad Prabhakar}; 55*2fddca72SLad Prabhakar 56*2fddca72SLad Prabhakar&scif { 57*2fddca72SLad Prabhakar pinctrl-0 = <&scif_pins>; 58*2fddca72SLad Prabhakar pinctrl-names = "default"; 59*2fddca72SLad Prabhakar 60*2fddca72SLad Prabhakar status = "okay"; 61*2fddca72SLad Prabhakar}; 62