1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/V2H(P) SoC 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas,r9a09g057-cpg.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "renesas,r9a09g057"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 audio_extal_clk: audio-clk { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 /* This value must be overridden by the board */ 20 clock-frequency = <0>; 21 }; 22 23 cpus { 24 #address-cells = <1>; 25 #size-cells = <0>; 26 27 cpu0: cpu@0 { 28 compatible = "arm,cortex-a55"; 29 reg = <0>; 30 device_type = "cpu"; 31 next-level-cache = <&L3_CA55>; 32 enable-method = "psci"; 33 }; 34 35 cpu1: cpu@100 { 36 compatible = "arm,cortex-a55"; 37 reg = <0x100>; 38 device_type = "cpu"; 39 next-level-cache = <&L3_CA55>; 40 enable-method = "psci"; 41 }; 42 43 cpu2: cpu@200 { 44 compatible = "arm,cortex-a55"; 45 reg = <0x200>; 46 device_type = "cpu"; 47 next-level-cache = <&L3_CA55>; 48 enable-method = "psci"; 49 }; 50 51 cpu3: cpu@300 { 52 compatible = "arm,cortex-a55"; 53 reg = <0x300>; 54 device_type = "cpu"; 55 next-level-cache = <&L3_CA55>; 56 enable-method = "psci"; 57 }; 58 59 L3_CA55: cache-controller-0 { 60 compatible = "cache"; 61 cache-unified; 62 cache-size = <0x100000>; 63 cache-level = <3>; 64 }; 65 }; 66 67 psci { 68 compatible = "arm,psci-1.0", "arm,psci-0.2"; 69 method = "smc"; 70 }; 71 72 qextal_clk: qextal-clk { 73 compatible = "fixed-clock"; 74 #clock-cells = <0>; 75 /* This value must be overridden by the board */ 76 clock-frequency = <0>; 77 }; 78 79 rtxin_clk: rtxin-clk { 80 compatible = "fixed-clock"; 81 #clock-cells = <0>; 82 /* This value must be overridden by the board */ 83 clock-frequency = <0>; 84 }; 85 86 soc: soc { 87 compatible = "simple-bus"; 88 interrupt-parent = <&gic>; 89 #address-cells = <2>; 90 #size-cells = <2>; 91 ranges; 92 93 pinctrl: pinctrl@10410000 { 94 compatible = "renesas,r9a09g057-pinctrl"; 95 reg = <0 0x10410000 0 0x10000>; 96 clocks = <&cpg CPG_CORE R9A09G057_IOTOP_0_SHCLK>; 97 gpio-controller; 98 #gpio-cells = <2>; 99 gpio-ranges = <&pinctrl 0 0 96>; 100 #interrupt-cells = <2>; 101 interrupt-controller; 102 power-domains = <&cpg>; 103 resets = <&cpg 0xa5>, <&cpg 0xa6>; 104 }; 105 106 cpg: clock-controller@10420000 { 107 compatible = "renesas,r9a09g057-cpg"; 108 reg = <0 0x10420000 0 0x10000>; 109 clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; 110 clock-names = "audio_extal", "rtxin", "qextal"; 111 #clock-cells = <2>; 112 #reset-cells = <1>; 113 #power-domain-cells = <0>; 114 }; 115 116 sys: system-controller@10430000 { 117 compatible = "renesas,r9a09g057-sys"; 118 reg = <0 0x10430000 0 0x10000>; 119 clocks = <&cpg CPG_CORE R9A09G057_SYS_0_PCLK>; 120 resets = <&cpg 0x30>; 121 status = "disabled"; 122 }; 123 124 scif: serial@11c01400 { 125 compatible = "renesas,scif-r9a09g057"; 126 reg = <0 0x11c01400 0 0x400>; 127 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 129 <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, 130 <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 131 <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>, 135 <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>; 136 interrupt-names = "eri", "rxi", "txi", "bri", "dri", 137 "tei", "tei-dri", "rxi-edge", "txi-edge"; 138 clocks = <&cpg CPG_MOD 0x8f>; 139 clock-names = "fck"; 140 power-domains = <&cpg>; 141 resets = <&cpg 0x95>; 142 status = "disabled"; 143 }; 144 145 gic: interrupt-controller@14900000 { 146 compatible = "arm,gic-v3"; 147 reg = <0x0 0x14900000 0 0x20000>, 148 <0x0 0x14940000 0 0x80000>; 149 #interrupt-cells = <3>; 150 #address-cells = <0>; 151 interrupt-controller; 152 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 153 }; 154 }; 155 156 timer { 157 compatible = "arm,armv8-timer"; 158 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 159 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 160 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 161 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 162 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 163 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 164 }; 165}; 166