1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/V2H(P) SoC 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas,r9a09g057-cpg.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "renesas,r9a09g057"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 audio_extal_clk: audio-clk { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 /* This value must be overridden by the board */ 20 clock-frequency = <0>; 21 }; 22 23 cpus { 24 #address-cells = <1>; 25 #size-cells = <0>; 26 27 cpu0: cpu@0 { 28 compatible = "arm,cortex-a55"; 29 reg = <0>; 30 device_type = "cpu"; 31 next-level-cache = <&L3_CA55>; 32 enable-method = "psci"; 33 }; 34 35 cpu1: cpu@100 { 36 compatible = "arm,cortex-a55"; 37 reg = <0x100>; 38 device_type = "cpu"; 39 next-level-cache = <&L3_CA55>; 40 enable-method = "psci"; 41 }; 42 43 cpu2: cpu@200 { 44 compatible = "arm,cortex-a55"; 45 reg = <0x200>; 46 device_type = "cpu"; 47 next-level-cache = <&L3_CA55>; 48 enable-method = "psci"; 49 }; 50 51 cpu3: cpu@300 { 52 compatible = "arm,cortex-a55"; 53 reg = <0x300>; 54 device_type = "cpu"; 55 next-level-cache = <&L3_CA55>; 56 enable-method = "psci"; 57 }; 58 59 L3_CA55: cache-controller-0 { 60 compatible = "cache"; 61 cache-unified; 62 cache-size = <0x100000>; 63 cache-level = <3>; 64 }; 65 }; 66 67 psci { 68 compatible = "arm,psci-1.0", "arm,psci-0.2"; 69 method = "smc"; 70 }; 71 72 qextal_clk: qextal-clk { 73 compatible = "fixed-clock"; 74 #clock-cells = <0>; 75 /* This value must be overridden by the board */ 76 clock-frequency = <0>; 77 }; 78 79 rtxin_clk: rtxin-clk { 80 compatible = "fixed-clock"; 81 #clock-cells = <0>; 82 /* This value must be overridden by the board */ 83 clock-frequency = <0>; 84 }; 85 86 soc: soc { 87 compatible = "simple-bus"; 88 interrupt-parent = <&gic>; 89 #address-cells = <2>; 90 #size-cells = <2>; 91 ranges; 92 93 pinctrl: pinctrl@10410000 { 94 compatible = "renesas,r9a09g057-pinctrl"; 95 reg = <0 0x10410000 0 0x10000>; 96 clocks = <&cpg CPG_CORE R9A09G057_IOTOP_0_SHCLK>; 97 gpio-controller; 98 #gpio-cells = <2>; 99 gpio-ranges = <&pinctrl 0 0 96>; 100 #interrupt-cells = <2>; 101 interrupt-controller; 102 power-domains = <&cpg>; 103 resets = <&cpg 0xa5>, <&cpg 0xa6>; 104 }; 105 106 cpg: clock-controller@10420000 { 107 compatible = "renesas,r9a09g057-cpg"; 108 reg = <0 0x10420000 0 0x10000>; 109 clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; 110 clock-names = "audio_extal", "rtxin", "qextal"; 111 #clock-cells = <2>; 112 #reset-cells = <1>; 113 #power-domain-cells = <0>; 114 }; 115 116 sys: system-controller@10430000 { 117 compatible = "renesas,r9a09g057-sys"; 118 reg = <0 0x10430000 0 0x10000>; 119 clocks = <&cpg CPG_CORE R9A09G057_SYS_0_PCLK>; 120 resets = <&cpg 0x30>; 121 status = "disabled"; 122 }; 123 124 ostm0: timer@11800000 { 125 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 126 reg = <0x0 0x11800000 0x0 0x1000>; 127 interrupts = <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>; 128 clocks = <&cpg CPG_MOD 0x43>; 129 resets = <&cpg 0x6d>; 130 power-domains = <&cpg>; 131 status = "disabled"; 132 }; 133 134 ostm1: timer@11801000 { 135 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 136 reg = <0x0 0x11801000 0x0 0x1000>; 137 interrupts = <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>; 138 clocks = <&cpg CPG_MOD 0x44>; 139 resets = <&cpg 0x6e>; 140 power-domains = <&cpg>; 141 status = "disabled"; 142 }; 143 144 ostm2: timer@14000000 { 145 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 146 reg = <0x0 0x14000000 0x0 0x1000>; 147 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>; 148 clocks = <&cpg CPG_MOD 0x45>; 149 resets = <&cpg 0x6f>; 150 power-domains = <&cpg>; 151 status = "disabled"; 152 }; 153 154 ostm3: timer@14001000 { 155 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 156 reg = <0x0 0x14001000 0x0 0x1000>; 157 interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>; 158 clocks = <&cpg CPG_MOD 0x46>; 159 resets = <&cpg 0x70>; 160 power-domains = <&cpg>; 161 status = "disabled"; 162 }; 163 164 ostm4: timer@12c00000 { 165 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 166 reg = <0x0 0x12c00000 0x0 0x1000>; 167 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 168 clocks = <&cpg CPG_MOD 0x47>; 169 resets = <&cpg 0x71>; 170 power-domains = <&cpg>; 171 status = "disabled"; 172 }; 173 174 ostm5: timer@12c01000 { 175 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 176 reg = <0x0 0x12c01000 0x0 0x1000>; 177 interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 178 clocks = <&cpg CPG_MOD 0x48>; 179 resets = <&cpg 0x72>; 180 power-domains = <&cpg>; 181 status = "disabled"; 182 }; 183 184 ostm6: timer@12c02000 { 185 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 186 reg = <0x0 0x12c02000 0x0 0x1000>; 187 interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>; 188 clocks = <&cpg CPG_MOD 0x49>; 189 resets = <&cpg 0x73>; 190 power-domains = <&cpg>; 191 status = "disabled"; 192 }; 193 194 ostm7: timer@12c03000 { 195 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 196 reg = <0x0 0x12c03000 0x0 0x1000>; 197 interrupts = <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>; 198 clocks = <&cpg CPG_MOD 0x4a>; 199 resets = <&cpg 0x74>; 200 power-domains = <&cpg>; 201 status = "disabled"; 202 }; 203 204 scif: serial@11c01400 { 205 compatible = "renesas,scif-r9a09g057"; 206 reg = <0 0x11c01400 0 0x400>; 207 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>, 215 <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>; 216 interrupt-names = "eri", "rxi", "txi", "bri", "dri", 217 "tei", "tei-dri", "rxi-edge", "txi-edge"; 218 clocks = <&cpg CPG_MOD 0x8f>; 219 clock-names = "fck"; 220 power-domains = <&cpg>; 221 resets = <&cpg 0x95>; 222 status = "disabled"; 223 }; 224 225 i2c0: i2c@14400400 { 226 compatible = "renesas,riic-r9a09g057"; 227 reg = <0 0x14400400 0 0x400>; 228 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 507 IRQ_TYPE_EDGE_RISING>, 230 <GIC_SPI 506 IRQ_TYPE_EDGE_RISING>, 231 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 236 interrupt-names = "tei", "ri", "ti", "spi", "sti", 237 "naki", "ali", "tmoi"; 238 clocks = <&cpg CPG_MOD 0x94>; 239 resets = <&cpg 0x98>; 240 power-domains = <&cpg>; 241 #address-cells = <1>; 242 #size-cells = <0>; 243 status = "disabled"; 244 }; 245 246 i2c1: i2c@14400800 { 247 compatible = "renesas,riic-r9a09g057"; 248 reg = <0 0x14400800 0 0x400>; 249 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 509 IRQ_TYPE_EDGE_RISING>, 251 <GIC_SPI 508 IRQ_TYPE_EDGE_RISING>, 252 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 257 interrupt-names = "tei", "ri", "ti", "spi", "sti", 258 "naki", "ali", "tmoi"; 259 clocks = <&cpg CPG_MOD 0x95>; 260 resets = <&cpg 0x99>; 261 power-domains = <&cpg>; 262 #address-cells = <1>; 263 #size-cells = <0>; 264 status = "disabled"; 265 }; 266 267 i2c2: i2c@14400c00 { 268 compatible = "renesas,riic-r9a09g057"; 269 reg = <0 0x14400c00 0 0x400>; 270 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 511 IRQ_TYPE_EDGE_RISING>, 272 <GIC_SPI 510 IRQ_TYPE_EDGE_RISING>, 273 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 274 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 278 interrupt-names = "tei", "ri", "ti", "spi", "sti", 279 "naki", "ali", "tmoi"; 280 clocks = <&cpg CPG_MOD 0x96>; 281 resets = <&cpg 0x9a>; 282 power-domains = <&cpg>; 283 #address-cells = <1>; 284 #size-cells = <0>; 285 status = "disabled"; 286 }; 287 288 i2c3: i2c@14401000 { 289 compatible = "renesas,riic-r9a09g057"; 290 reg = <0 0x14401000 0 0x400>; 291 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>, 293 <GIC_SPI 512 IRQ_TYPE_EDGE_RISING>, 294 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 299 interrupt-names = "tei", "ri", "ti", "spi", "sti", 300 "naki", "ali", "tmoi"; 301 clocks = <&cpg CPG_MOD 0x97>; 302 resets = <&cpg 0x9b>; 303 power-domains = <&cpg>; 304 #address-cells = <1>; 305 #size-cells = <0>; 306 status = "disabled"; 307 }; 308 309 i2c4: i2c@14401400 { 310 compatible = "renesas,riic-r9a09g057"; 311 reg = <0 0x14401400 0 0x400>; 312 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 313 <GIC_SPI 515 IRQ_TYPE_EDGE_RISING>, 314 <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>, 315 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 316 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 317 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 320 interrupt-names = "tei", "ri", "ti", "spi", "sti", 321 "naki", "ali", "tmoi"; 322 clocks = <&cpg CPG_MOD 0x98>; 323 resets = <&cpg 0x9c>; 324 power-domains = <&cpg>; 325 #address-cells = <1>; 326 #size-cells = <0>; 327 status = "disabled"; 328 }; 329 330 i2c5: i2c@14401800 { 331 compatible = "renesas,riic-r9a09g057"; 332 reg = <0 0x14401800 0 0x400>; 333 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 334 <GIC_SPI 517 IRQ_TYPE_EDGE_RISING>, 335 <GIC_SPI 516 IRQ_TYPE_EDGE_RISING>, 336 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 340 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 341 interrupt-names = "tei", "ri", "ti", "spi", "sti", 342 "naki", "ali", "tmoi"; 343 clocks = <&cpg CPG_MOD 0x99>; 344 resets = <&cpg 0x9d>; 345 power-domains = <&cpg>; 346 #address-cells = <1>; 347 #size-cells = <0>; 348 status = "disabled"; 349 }; 350 351 i2c6: i2c@14401c00 { 352 compatible = "renesas,riic-r9a09g057"; 353 reg = <0 0x14401c00 0 0x400>; 354 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_SPI 519 IRQ_TYPE_EDGE_RISING>, 356 <GIC_SPI 518 IRQ_TYPE_EDGE_RISING>, 357 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 362 interrupt-names = "tei", "ri", "ti", "spi", "sti", 363 "naki", "ali", "tmoi"; 364 clocks = <&cpg CPG_MOD 0x9a>; 365 resets = <&cpg 0x9e>; 366 power-domains = <&cpg>; 367 #address-cells = <1>; 368 #size-cells = <0>; 369 status = "disabled"; 370 }; 371 372 i2c7: i2c@14402000 { 373 compatible = "renesas,riic-r9a09g057"; 374 reg = <0 0x14402000 0 0x400>; 375 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 521 IRQ_TYPE_EDGE_RISING>, 377 <GIC_SPI 520 IRQ_TYPE_EDGE_RISING>, 378 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 381 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 382 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 383 interrupt-names = "tei", "ri", "ti", "spi", "sti", 384 "naki", "ali", "tmoi"; 385 clocks = <&cpg CPG_MOD 0x9b>; 386 resets = <&cpg 0x9f>; 387 power-domains = <&cpg>; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 status = "disabled"; 391 }; 392 393 i2c8: i2c@11c01000 { 394 compatible = "renesas,riic-r9a09g057"; 395 reg = <0 0x11c01000 0 0x400>; 396 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 397 <GIC_SPI 523 IRQ_TYPE_EDGE_RISING>, 398 <GIC_SPI 522 IRQ_TYPE_EDGE_RISING>, 399 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 403 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 404 interrupt-names = "tei", "ri", "ti", "spi", "sti", 405 "naki", "ali", "tmoi"; 406 clocks = <&cpg CPG_MOD 0x93>; 407 resets = <&cpg 0xa0>; 408 power-domains = <&cpg>; 409 #address-cells = <1>; 410 #size-cells = <0>; 411 status = "disabled"; 412 }; 413 414 gic: interrupt-controller@14900000 { 415 compatible = "arm,gic-v3"; 416 reg = <0x0 0x14900000 0 0x20000>, 417 <0x0 0x14940000 0 0x80000>; 418 #interrupt-cells = <3>; 419 #address-cells = <0>; 420 interrupt-controller; 421 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 422 }; 423 }; 424 425 timer { 426 compatible = "arm,armv8-timer"; 427 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 428 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 429 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 430 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 431 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 432 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 433 }; 434}; 435