1*ad142a4eSHai Pham// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*ad142a4eSHai Pham/* 3*ad142a4eSHai Pham * Device Tree Source for the Ironhide board 4*ad142a4eSHai Pham * 5*ad142a4eSHai Pham * Copyright (C) 2025 Renesas Electronics Corp. 6*ad142a4eSHai Pham */ 7*ad142a4eSHai Pham 8*ad142a4eSHai Pham/dts-v1/; 9*ad142a4eSHai Pham#include "r8a78000.dtsi" 10*ad142a4eSHai Pham 11*ad142a4eSHai Pham/ { 12*ad142a4eSHai Pham model = "Renesas Ironhide board based on r8a78000"; 13*ad142a4eSHai Pham compatible = "renesas,ironhide", "renesas,r8a78000"; 14*ad142a4eSHai Pham 15*ad142a4eSHai Pham aliases { 16*ad142a4eSHai Pham serial0 = &hscif0; 17*ad142a4eSHai Pham }; 18*ad142a4eSHai Pham 19*ad142a4eSHai Pham chosen { 20*ad142a4eSHai Pham stdout-path = "serial0:1843200n8"; 21*ad142a4eSHai Pham }; 22*ad142a4eSHai Pham 23*ad142a4eSHai Pham memory@60600000 { 24*ad142a4eSHai Pham device_type = "memory"; 25*ad142a4eSHai Pham /* first 518MiB is reserved for other purposes. */ 26*ad142a4eSHai Pham reg = <0x0 0x60600000 0x0 0x5fa00000>; 27*ad142a4eSHai Pham }; 28*ad142a4eSHai Pham 29*ad142a4eSHai Pham memory@1080000000 { 30*ad142a4eSHai Pham device_type = "memory"; 31*ad142a4eSHai Pham reg = <0x10 0x80000000 0x0 0x80000000>; 32*ad142a4eSHai Pham }; 33*ad142a4eSHai Pham 34*ad142a4eSHai Pham memory@1200000000 { 35*ad142a4eSHai Pham device_type = "memory"; 36*ad142a4eSHai Pham reg = <0x12 0x00000000 0x1 0x00000000>; 37*ad142a4eSHai Pham }; 38*ad142a4eSHai Pham 39*ad142a4eSHai Pham memory@1400000000 { 40*ad142a4eSHai Pham device_type = "memory"; 41*ad142a4eSHai Pham reg = <0x14 0x00000000 0x1 0x00000000>; 42*ad142a4eSHai Pham }; 43*ad142a4eSHai Pham 44*ad142a4eSHai Pham memory@1600000000 { 45*ad142a4eSHai Pham device_type = "memory"; 46*ad142a4eSHai Pham reg = <0x16 0x00000000 0x1 0x00000000>; 47*ad142a4eSHai Pham }; 48*ad142a4eSHai Pham 49*ad142a4eSHai Pham memory@1800000000 { 50*ad142a4eSHai Pham device_type = "memory"; 51*ad142a4eSHai Pham reg = <0x18 0x00000000 0x1 0x00000000>; 52*ad142a4eSHai Pham }; 53*ad142a4eSHai Pham 54*ad142a4eSHai Pham memory@1a00000000 { 55*ad142a4eSHai Pham device_type = "memory"; 56*ad142a4eSHai Pham reg = <0x1a 0x00000000 0x1 0x00000000>; 57*ad142a4eSHai Pham }; 58*ad142a4eSHai Pham 59*ad142a4eSHai Pham memory@1c00000000 { 60*ad142a4eSHai Pham device_type = "memory"; 61*ad142a4eSHai Pham reg = <0x1c 0x00000000 0x1 0x00000000>; 62*ad142a4eSHai Pham }; 63*ad142a4eSHai Pham 64*ad142a4eSHai Pham memory@1e00000000 { 65*ad142a4eSHai Pham device_type = "memory"; 66*ad142a4eSHai Pham reg = <0x1e 0x00000000 0x1 0x00000000>; 67*ad142a4eSHai Pham }; 68*ad142a4eSHai Pham}; 69*ad142a4eSHai Pham 70*ad142a4eSHai Pham&extal_clk { 71*ad142a4eSHai Pham clock-frequency = <16666600>; 72*ad142a4eSHai Pham}; 73*ad142a4eSHai Pham 74*ad142a4eSHai Pham&extalr_clk { 75*ad142a4eSHai Pham clock-frequency = <32768>; 76*ad142a4eSHai Pham}; 77*ad142a4eSHai Pham 78*ad142a4eSHai Pham&hscif0 { 79*ad142a4eSHai Pham uart-has-rtscts; 80*ad142a4eSHai Pham status = "okay"; 81*ad142a4eSHai Pham}; 82*ad142a4eSHai Pham 83*ad142a4eSHai Pham&scif_clk { 84*ad142a4eSHai Pham clock-frequency = <26000000>; 85*ad142a4eSHai Pham}; 86