1// SPDX-License-Identifier: (GPL-2.0 or MIT) 2/* 3 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a779f0-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a779f0-sysc.h> 11 12/ { 13 compatible = "renesas,r8a779f0"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 cpu-map { 22 cluster0 { 23 core0 { 24 cpu = <&a55_0>; 25 }; 26 core1 { 27 cpu = <&a55_1>; 28 }; 29 }; 30 31 cluster1 { 32 core0 { 33 cpu = <&a55_2>; 34 }; 35 core1 { 36 cpu = <&a55_3>; 37 }; 38 }; 39 40 cluster2 { 41 core0 { 42 cpu = <&a55_4>; 43 }; 44 core1 { 45 cpu = <&a55_5>; 46 }; 47 }; 48 49 cluster3 { 50 core0 { 51 cpu = <&a55_6>; 52 }; 53 core1 { 54 cpu = <&a55_7>; 55 }; 56 }; 57 }; 58 59 a55_0: cpu@0 { 60 compatible = "arm,cortex-a55"; 61 reg = <0>; 62 device_type = "cpu"; 63 power-domains = <&sysc R8A779F0_PD_A1E0D0C0>; 64 next-level-cache = <&L3_CA55_0>; 65 enable-method = "psci"; 66 cpu-idle-states = <&CPU_SLEEP_0>; 67 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; 68 }; 69 70 a55_1: cpu@100 { 71 compatible = "arm,cortex-a55"; 72 reg = <0x100>; 73 device_type = "cpu"; 74 power-domains = <&sysc R8A779F0_PD_A1E0D0C1>; 75 next-level-cache = <&L3_CA55_0>; 76 enable-method = "psci"; 77 cpu-idle-states = <&CPU_SLEEP_0>; 78 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; 79 }; 80 81 a55_2: cpu@10000 { 82 compatible = "arm,cortex-a55"; 83 reg = <0x10000>; 84 device_type = "cpu"; 85 power-domains = <&sysc R8A779F0_PD_A1E0D1C0>; 86 next-level-cache = <&L3_CA55_1>; 87 enable-method = "psci"; 88 cpu-idle-states = <&CPU_SLEEP_0>; 89 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; 90 }; 91 92 a55_3: cpu@10100 { 93 compatible = "arm,cortex-a55"; 94 reg = <0x10100>; 95 device_type = "cpu"; 96 power-domains = <&sysc R8A779F0_PD_A1E0D1C1>; 97 next-level-cache = <&L3_CA55_1>; 98 enable-method = "psci"; 99 cpu-idle-states = <&CPU_SLEEP_0>; 100 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; 101 }; 102 103 a55_4: cpu@20000 { 104 compatible = "arm,cortex-a55"; 105 reg = <0x20000>; 106 device_type = "cpu"; 107 power-domains = <&sysc R8A779F0_PD_A1E1D0C0>; 108 next-level-cache = <&L3_CA55_2>; 109 enable-method = "psci"; 110 cpu-idle-states = <&CPU_SLEEP_0>; 111 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; 112 }; 113 114 a55_5: cpu@20100 { 115 compatible = "arm,cortex-a55"; 116 reg = <0x20100>; 117 device_type = "cpu"; 118 power-domains = <&sysc R8A779F0_PD_A1E1D0C1>; 119 next-level-cache = <&L3_CA55_2>; 120 enable-method = "psci"; 121 cpu-idle-states = <&CPU_SLEEP_0>; 122 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; 123 }; 124 125 a55_6: cpu@30000 { 126 compatible = "arm,cortex-a55"; 127 reg = <0x30000>; 128 device_type = "cpu"; 129 power-domains = <&sysc R8A779F0_PD_A1E1D1C0>; 130 next-level-cache = <&L3_CA55_3>; 131 enable-method = "psci"; 132 cpu-idle-states = <&CPU_SLEEP_0>; 133 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; 134 }; 135 136 a55_7: cpu@30100 { 137 compatible = "arm,cortex-a55"; 138 reg = <0x30100>; 139 device_type = "cpu"; 140 power-domains = <&sysc R8A779F0_PD_A1E1D1C1>; 141 next-level-cache = <&L3_CA55_3>; 142 enable-method = "psci"; 143 cpu-idle-states = <&CPU_SLEEP_0>; 144 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; 145 }; 146 147 L3_CA55_0: cache-controller-0 { 148 compatible = "cache"; 149 power-domains = <&sysc R8A779F0_PD_A2E0D0>; 150 cache-unified; 151 cache-level = <3>; 152 }; 153 154 L3_CA55_1: cache-controller-1 { 155 compatible = "cache"; 156 power-domains = <&sysc R8A779F0_PD_A2E0D1>; 157 cache-unified; 158 cache-level = <3>; 159 }; 160 161 L3_CA55_2: cache-controller-2 { 162 compatible = "cache"; 163 power-domains = <&sysc R8A779F0_PD_A2E1D0>; 164 cache-unified; 165 cache-level = <3>; 166 }; 167 168 L3_CA55_3: cache-controller-3 { 169 compatible = "cache"; 170 power-domains = <&sysc R8A779F0_PD_A2E1D1>; 171 cache-unified; 172 cache-level = <3>; 173 }; 174 175 idle-states { 176 entry-method = "psci"; 177 178 CPU_SLEEP_0: cpu-sleep-0 { 179 compatible = "arm,idle-state"; 180 arm,psci-suspend-param = <0x0010000>; 181 local-timer-stop; 182 entry-latency-us = <400>; 183 exit-latency-us = <500>; 184 min-residency-us = <4000>; 185 }; 186 }; 187 }; 188 189 extal_clk: extal { 190 compatible = "fixed-clock"; 191 #clock-cells = <0>; 192 /* This value must be overridden by the board */ 193 clock-frequency = <0>; 194 }; 195 196 extalr_clk: extalr { 197 compatible = "fixed-clock"; 198 #clock-cells = <0>; 199 /* This value must be overridden by the board */ 200 clock-frequency = <0>; 201 }; 202 203 pmu_a55 { 204 compatible = "arm,cortex-a55-pmu"; 205 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 206 }; 207 208 psci { 209 compatible = "arm,psci-1.0", "arm,psci-0.2"; 210 method = "smc"; 211 }; 212 213 /* External SCIF clock - to be overridden by boards that provide it */ 214 scif_clk: scif { 215 compatible = "fixed-clock"; 216 #clock-cells = <0>; 217 clock-frequency = <0>; 218 }; 219 220 soc: soc { 221 compatible = "simple-bus"; 222 interrupt-parent = <&gic>; 223 #address-cells = <2>; 224 #size-cells = <2>; 225 ranges; 226 227 rwdt: watchdog@e6020000 { 228 compatible = "renesas,r8a779f0-wdt", 229 "renesas,rcar-gen4-wdt"; 230 reg = <0 0xe6020000 0 0x0c>; 231 interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>; 232 clocks = <&cpg CPG_MOD 907>; 233 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 234 resets = <&cpg 907>; 235 status = "disabled"; 236 }; 237 238 pfc: pinctrl@e6050000 { 239 compatible = "renesas,pfc-r8a779f0"; 240 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, 241 <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>; 242 }; 243 244 gpio0: gpio@e6050180 { 245 compatible = "renesas,gpio-r8a779f0", 246 "renesas,rcar-gen4-gpio"; 247 reg = <0 0xe6050180 0 0x54>; 248 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; 249 clocks = <&cpg CPG_MOD 915>; 250 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 251 resets = <&cpg 915>; 252 gpio-controller; 253 #gpio-cells = <2>; 254 gpio-ranges = <&pfc 0 0 21>; 255 interrupt-controller; 256 #interrupt-cells = <2>; 257 }; 258 259 gpio1: gpio@e6050980 { 260 compatible = "renesas,gpio-r8a779f0", 261 "renesas,rcar-gen4-gpio"; 262 reg = <0 0xe6050980 0 0x54>; 263 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; 264 clocks = <&cpg CPG_MOD 915>; 265 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 266 resets = <&cpg 915>; 267 gpio-controller; 268 #gpio-cells = <2>; 269 gpio-ranges = <&pfc 0 32 25>; 270 interrupt-controller; 271 #interrupt-cells = <2>; 272 }; 273 274 gpio2: gpio@e6051180 { 275 compatible = "renesas,gpio-r8a779f0", 276 "renesas,rcar-gen4-gpio"; 277 reg = <0 0xe6051180 0 0x54>; 278 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&cpg CPG_MOD 915>; 280 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 281 resets = <&cpg 915>; 282 gpio-controller; 283 #gpio-cells = <2>; 284 gpio-ranges = <&pfc 0 64 17>; 285 interrupt-controller; 286 #interrupt-cells = <2>; 287 }; 288 289 gpio3: gpio@e6051980 { 290 compatible = "renesas,gpio-r8a779f0", 291 "renesas,rcar-gen4-gpio"; 292 reg = <0 0xe6051980 0 0x54>; 293 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&cpg CPG_MOD 915>; 295 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 296 resets = <&cpg 915>; 297 gpio-controller; 298 #gpio-cells = <2>; 299 gpio-ranges = <&pfc 0 96 19>; 300 interrupt-controller; 301 #interrupt-cells = <2>; 302 }; 303 304 cmt0: timer@e60f0000 { 305 compatible = "renesas,r8a779f0-cmt0", 306 "renesas,rcar-gen4-cmt0"; 307 reg = <0 0xe60f0000 0 0x1004>; 308 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&cpg CPG_MOD 910>; 311 clock-names = "fck"; 312 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 313 resets = <&cpg 910>; 314 status = "disabled"; 315 }; 316 317 cmt1: timer@e6130000 { 318 compatible = "renesas,r8a779f0-cmt1", 319 "renesas,rcar-gen4-cmt1"; 320 reg = <0 0xe6130000 0 0x1004>; 321 interrupts = <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, 328 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>; 329 clocks = <&cpg CPG_MOD 911>; 330 clock-names = "fck"; 331 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 332 resets = <&cpg 911>; 333 status = "disabled"; 334 }; 335 336 cmt2: timer@e6140000 { 337 compatible = "renesas,r8a779f0-cmt1", 338 "renesas,rcar-gen4-cmt1"; 339 reg = <0 0xe6140000 0 0x1004>; 340 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 341 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 342 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 343 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 346 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 347 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&cpg CPG_MOD 912>; 349 clock-names = "fck"; 350 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 351 resets = <&cpg 912>; 352 status = "disabled"; 353 }; 354 355 cmt3: timer@e6148000 { 356 compatible = "renesas,r8a779f0-cmt1", 357 "renesas,rcar-gen4-cmt1"; 358 reg = <0 0xe6148000 0 0x1004>; 359 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 365 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 366 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 367 clocks = <&cpg CPG_MOD 913>; 368 clock-names = "fck"; 369 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 370 resets = <&cpg 913>; 371 status = "disabled"; 372 }; 373 374 cpg: clock-controller@e6150000 { 375 compatible = "renesas,r8a779f0-cpg-mssr"; 376 reg = <0 0xe6150000 0 0x4000>; 377 clocks = <&extal_clk>, <&extalr_clk>; 378 clock-names = "extal", "extalr"; 379 #clock-cells = <2>; 380 #power-domain-cells = <0>; 381 #reset-cells = <1>; 382 }; 383 384 rst: reset-controller@e6160000 { 385 compatible = "renesas,r8a779f0-rst"; 386 reg = <0 0xe6160000 0 0x4000>; 387 }; 388 389 sysc: system-controller@e6180000 { 390 compatible = "renesas,r8a779f0-sysc"; 391 reg = <0 0xe6180000 0 0x4000>; 392 #power-domain-cells = <1>; 393 }; 394 395 tsc: thermal@e6198000 { 396 compatible = "renesas,r8a779f0-thermal"; 397 /* The 4th sensor is in control domain and not for Linux */ 398 reg = <0 0xe6198000 0 0x200>, 399 <0 0xe61a0000 0 0x200>, 400 <0 0xe61a8000 0 0x200>; 401 clocks = <&cpg CPG_MOD 919>; 402 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 403 resets = <&cpg 919>; 404 #thermal-sensor-cells = <1>; 405 }; 406 407 i2c0: i2c@e6500000 { 408 compatible = "renesas,i2c-r8a779f0", 409 "renesas,rcar-gen4-i2c"; 410 reg = <0 0xe6500000 0 0x40>; 411 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 412 clocks = <&cpg CPG_MOD 518>; 413 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 414 resets = <&cpg 518>; 415 dmas = <&dmac0 0x91>, <&dmac0 0x90>, 416 <&dmac1 0x91>, <&dmac1 0x90>; 417 dma-names = "tx", "rx", "tx", "rx"; 418 i2c-scl-internal-delay-ns = <110>; 419 #address-cells = <1>; 420 #size-cells = <0>; 421 status = "disabled"; 422 }; 423 424 i2c1: i2c@e6508000 { 425 compatible = "renesas,i2c-r8a779f0", 426 "renesas,rcar-gen4-i2c"; 427 reg = <0 0xe6508000 0 0x40>; 428 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 429 clocks = <&cpg CPG_MOD 519>; 430 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 431 resets = <&cpg 519>; 432 dmas = <&dmac0 0x93>, <&dmac0 0x92>, 433 <&dmac1 0x93>, <&dmac1 0x92>; 434 dma-names = "tx", "rx", "tx", "rx"; 435 i2c-scl-internal-delay-ns = <110>; 436 #address-cells = <1>; 437 #size-cells = <0>; 438 status = "disabled"; 439 }; 440 441 i2c2: i2c@e6510000 { 442 compatible = "renesas,i2c-r8a779f0", 443 "renesas,rcar-gen4-i2c"; 444 reg = <0 0xe6510000 0 0x40>; 445 interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>; 446 clocks = <&cpg CPG_MOD 520>; 447 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 448 resets = <&cpg 520>; 449 dmas = <&dmac0 0x95>, <&dmac0 0x94>, 450 <&dmac1 0x95>, <&dmac1 0x94>; 451 dma-names = "tx", "rx", "tx", "rx"; 452 i2c-scl-internal-delay-ns = <110>; 453 #address-cells = <1>; 454 #size-cells = <0>; 455 status = "disabled"; 456 }; 457 458 i2c3: i2c@e66d0000 { 459 compatible = "renesas,i2c-r8a779f0", 460 "renesas,rcar-gen4-i2c"; 461 reg = <0 0xe66d0000 0 0x40>; 462 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&cpg CPG_MOD 521>; 464 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 465 resets = <&cpg 521>; 466 dmas = <&dmac0 0x97>, <&dmac0 0x96>, 467 <&dmac1 0x97>, <&dmac1 0x96>; 468 dma-names = "tx", "rx", "tx", "rx"; 469 i2c-scl-internal-delay-ns = <110>; 470 #address-cells = <1>; 471 #size-cells = <0>; 472 status = "disabled"; 473 }; 474 475 i2c4: i2c@e66d8000 { 476 compatible = "renesas,i2c-r8a779f0", 477 "renesas,rcar-gen4-i2c"; 478 reg = <0 0xe66d8000 0 0x40>; 479 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&cpg CPG_MOD 522>; 481 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 482 resets = <&cpg 522>; 483 dmas = <&dmac0 0x99>, <&dmac0 0x98>, 484 <&dmac1 0x99>, <&dmac1 0x98>; 485 dma-names = "tx", "rx", "tx", "rx"; 486 i2c-scl-internal-delay-ns = <110>; 487 #address-cells = <1>; 488 #size-cells = <0>; 489 status = "disabled"; 490 }; 491 492 i2c5: i2c@e66e0000 { 493 compatible = "renesas,i2c-r8a779f0", 494 "renesas,rcar-gen4-i2c"; 495 reg = <0 0xe66e0000 0 0x40>; 496 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 497 clocks = <&cpg CPG_MOD 523>; 498 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 499 resets = <&cpg 523>; 500 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>, 501 <&dmac1 0x9b>, <&dmac1 0x9a>; 502 dma-names = "tx", "rx", "tx", "rx"; 503 i2c-scl-internal-delay-ns = <110>; 504 #address-cells = <1>; 505 #size-cells = <0>; 506 status = "disabled"; 507 }; 508 509 hscif0: serial@e6540000 { 510 compatible = "renesas,hscif-r8a779f0", 511 "renesas,rcar-gen4-hscif", "renesas,hscif"; 512 reg = <0 0xe6540000 0 0x60>; 513 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 514 clocks = <&cpg CPG_MOD 514>, 515 <&cpg CPG_CORE R8A779F0_CLK_S0D3>, 516 <&scif_clk>; 517 clock-names = "fck", "brg_int", "scif_clk"; 518 dmas = <&dmac0 0x31>, <&dmac0 0x30>, 519 <&dmac1 0x31>, <&dmac1 0x30>; 520 dma-names = "tx", "rx", "tx", "rx"; 521 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 522 resets = <&cpg 514>; 523 status = "disabled"; 524 }; 525 526 hscif1: serial@e6550000 { 527 compatible = "renesas,hscif-r8a779f0", 528 "renesas,rcar-gen4-hscif", "renesas,hscif"; 529 reg = <0 0xe6550000 0 0x60>; 530 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 531 clocks = <&cpg CPG_MOD 515>, 532 <&cpg CPG_CORE R8A779F0_CLK_S0D3>, 533 <&scif_clk>; 534 clock-names = "fck", "brg_int", "scif_clk"; 535 dmas = <&dmac0 0x33>, <&dmac0 0x32>, 536 <&dmac1 0x33>, <&dmac1 0x32>; 537 dma-names = "tx", "rx", "tx", "rx"; 538 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 539 resets = <&cpg 515>; 540 status = "disabled"; 541 }; 542 543 hscif2: serial@e6560000 { 544 compatible = "renesas,hscif-r8a779f0", 545 "renesas,rcar-gen4-hscif", "renesas,hscif"; 546 reg = <0 0xe6560000 0 0x60>; 547 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 548 clocks = <&cpg CPG_MOD 516>, 549 <&cpg CPG_CORE R8A779F0_CLK_S0D3>, 550 <&scif_clk>; 551 clock-names = "fck", "brg_int", "scif_clk"; 552 dmas = <&dmac0 0x35>, <&dmac0 0x34>, 553 <&dmac1 0x35>, <&dmac1 0x34>; 554 dma-names = "tx", "rx", "tx", "rx"; 555 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 556 resets = <&cpg 516>; 557 status = "disabled"; 558 }; 559 560 hscif3: serial@e66a0000 { 561 compatible = "renesas,hscif-r8a779f0", 562 "renesas,rcar-gen4-hscif", "renesas,hscif"; 563 reg = <0 0xe66a0000 0 0x60>; 564 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 565 clocks = <&cpg CPG_MOD 517>, 566 <&cpg CPG_CORE R8A779F0_CLK_S0D3>, 567 <&scif_clk>; 568 clock-names = "fck", "brg_int", "scif_clk"; 569 dmas = <&dmac0 0x37>, <&dmac0 0x36>, 570 <&dmac1 0x37>, <&dmac1 0x36>; 571 dma-names = "tx", "rx", "tx", "rx"; 572 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 573 resets = <&cpg 517>; 574 status = "disabled"; 575 }; 576 577 ufs: ufs@e6860000 { 578 compatible = "renesas,r8a779f0-ufs"; 579 reg = <0 0xe6860000 0 0x100>; 580 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>; 582 clock-names = "fck", "ref_clk"; 583 freq-table-hz = <200000000 200000000>, <38400000 38400000>; 584 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 585 resets = <&cpg 1514>; 586 status = "disabled"; 587 }; 588 589 scif0: serial@e6e60000 { 590 compatible = "renesas,scif-r8a779f0", 591 "renesas,rcar-gen4-scif", "renesas,scif"; 592 reg = <0 0xe6e60000 0 64>; 593 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 594 clocks = <&cpg CPG_MOD 702>, 595 <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>, 596 <&scif_clk>; 597 clock-names = "fck", "brg_int", "scif_clk"; 598 dmas = <&dmac0 0x51>, <&dmac0 0x50>, 599 <&dmac1 0x51>, <&dmac1 0x50>; 600 dma-names = "tx", "rx", "tx", "rx"; 601 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 602 resets = <&cpg 702>; 603 status = "disabled"; 604 }; 605 606 scif1: serial@e6e68000 { 607 compatible = "renesas,scif-r8a779f0", 608 "renesas,rcar-gen4-scif", "renesas,scif"; 609 reg = <0 0xe6e68000 0 64>; 610 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>; 611 clocks = <&cpg CPG_MOD 703>, 612 <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>, 613 <&scif_clk>; 614 clock-names = "fck", "brg_int", "scif_clk"; 615 dmas = <&dmac0 0x53>, <&dmac0 0x52>, 616 <&dmac1 0x53>, <&dmac1 0x52>; 617 dma-names = "tx", "rx", "tx", "rx"; 618 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 619 resets = <&cpg 703>; 620 status = "disabled"; 621 }; 622 623 scif3: serial@e6c50000 { 624 compatible = "renesas,scif-r8a779f0", 625 "renesas,rcar-gen4-scif", "renesas,scif"; 626 reg = <0 0xe6c50000 0 64>; 627 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 628 clocks = <&cpg CPG_MOD 704>, 629 <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>, 630 <&scif_clk>; 631 clock-names = "fck", "brg_int", "scif_clk"; 632 dmas = <&dmac0 0x57>, <&dmac0 0x56>, 633 <&dmac1 0x57>, <&dmac1 0x56>; 634 dma-names = "tx", "rx", "tx", "rx"; 635 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 636 resets = <&cpg 704>; 637 status = "disabled"; 638 }; 639 640 scif4: serial@e6c40000 { 641 compatible = "renesas,scif-r8a779f0", 642 "renesas,rcar-gen4-scif", "renesas,scif"; 643 reg = <0 0xe6c40000 0 64>; 644 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 645 clocks = <&cpg CPG_MOD 705>, 646 <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>, 647 <&scif_clk>; 648 clock-names = "fck", "brg_int", "scif_clk"; 649 dmas = <&dmac0 0x59>, <&dmac0 0x58>, 650 <&dmac1 0x59>, <&dmac1 0x58>; 651 dma-names = "tx", "rx", "tx", "rx"; 652 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 653 resets = <&cpg 705>; 654 status = "disabled"; 655 }; 656 657 dmac0: dma-controller@e7350000 { 658 compatible = "renesas,dmac-r8a779f0", 659 "renesas,rcar-gen4-dmac"; 660 reg = <0 0xe7350000 0 0x1000>, 661 <0 0xe7300000 0 0x10000>; 662 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 663 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 664 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 672 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 673 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 674 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 675 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 676 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 677 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 679 interrupt-names = "error", 680 "ch0", "ch1", "ch2", "ch3", "ch4", 681 "ch5", "ch6", "ch7", "ch8", "ch9", 682 "ch10", "ch11", "ch12", "ch13", 683 "ch14", "ch15"; 684 clocks = <&cpg CPG_MOD 709>; 685 clock-names = "fck"; 686 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 687 resets = <&cpg 709>; 688 #dma-cells = <1>; 689 dma-channels = <16>; 690 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 691 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 692 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 693 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 694 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 695 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 696 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 697 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 698 }; 699 700 dmac1: dma-controller@e7351000 { 701 compatible = "renesas,dmac-r8a779f0", 702 "renesas,rcar-gen4-dmac"; 703 reg = <0 0xe7351000 0 0x1000>, 704 <0 0xe7310000 0 0x10000>; 705 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 715 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 722 interrupt-names = "error", 723 "ch0", "ch1", "ch2", "ch3", "ch4", 724 "ch5", "ch6", "ch7", "ch8", "ch9", 725 "ch10", "ch11", "ch12", "ch13", 726 "ch14", "ch15"; 727 clocks = <&cpg CPG_MOD 710>; 728 clock-names = "fck"; 729 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 730 resets = <&cpg 710>; 731 #dma-cells = <1>; 732 dma-channels = <16>; 733 iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>, 734 <&ipmmu_ds0 18>, <&ipmmu_ds0 19>, 735 <&ipmmu_ds0 20>, <&ipmmu_ds0 21>, 736 <&ipmmu_ds0 22>, <&ipmmu_ds0 23>, 737 <&ipmmu_ds0 24>, <&ipmmu_ds0 25>, 738 <&ipmmu_ds0 26>, <&ipmmu_ds0 27>, 739 <&ipmmu_ds0 28>, <&ipmmu_ds0 29>, 740 <&ipmmu_ds0 30>, <&ipmmu_ds0 31>; 741 }; 742 743 mmc0: mmc@ee140000 { 744 compatible = "renesas,sdhi-r8a779f0", 745 "renesas,rcar-gen4-sdhi"; 746 reg = <0 0xee140000 0 0x2000>; 747 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 748 clocks = <&cpg CPG_MOD 706>, <&cpg CPG_CORE R8A779F0_CLK_SD0H>; 749 clock-names = "core", "clkh"; 750 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 751 resets = <&cpg 706>; 752 max-frequency = <200000000>; 753 status = "disabled"; 754 }; 755 756 ipmmu_rt0: iommu@ee480000 { 757 compatible = "renesas,ipmmu-r8a779f0", 758 "renesas,rcar-gen4-ipmmu-vmsa"; 759 reg = <0 0xee480000 0 0x20000>; 760 renesas,ipmmu-main = <&ipmmu_mm 10>; 761 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 762 #iommu-cells = <1>; 763 }; 764 765 ipmmu_rt1: iommu@ee4c0000 { 766 compatible = "renesas,ipmmu-r8a779f0", 767 "renesas,rcar-gen4-ipmmu-vmsa"; 768 reg = <0 0xee4c0000 0 0x20000>; 769 renesas,ipmmu-main = <&ipmmu_mm 19>; 770 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 771 #iommu-cells = <1>; 772 }; 773 774 ipmmu_ds0: iommu@eed00000 { 775 compatible = "renesas,ipmmu-r8a779f0", 776 "renesas,rcar-gen4-ipmmu-vmsa"; 777 reg = <0 0xeed00000 0 0x20000>; 778 renesas,ipmmu-main = <&ipmmu_mm 0>; 779 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 780 #iommu-cells = <1>; 781 }; 782 783 ipmmu_hc: iommu@eed40000 { 784 compatible = "renesas,ipmmu-r8a779f0", 785 "renesas,rcar-gen4-ipmmu-vmsa"; 786 reg = <0 0xeed40000 0 0x20000>; 787 renesas,ipmmu-main = <&ipmmu_mm 2>; 788 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 789 #iommu-cells = <1>; 790 }; 791 792 ipmmu_mm: iommu@eefc0000 { 793 compatible = "renesas,ipmmu-r8a779f0", 794 "renesas,rcar-gen4-ipmmu-vmsa"; 795 reg = <0 0xeefc0000 0 0x20000>; 796 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 798 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 799 #iommu-cells = <1>; 800 }; 801 802 gic: interrupt-controller@f1000000 { 803 compatible = "arm,gic-v3"; 804 #interrupt-cells = <3>; 805 #address-cells = <0>; 806 interrupt-controller; 807 reg = <0x0 0xf1000000 0 0x20000>, 808 <0x0 0xf1060000 0 0x110000>; 809 interrupts = <GIC_PPI 9 810 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 811 }; 812 813 prr: chipid@fff00044 { 814 compatible = "renesas,prr"; 815 reg = <0 0xfff00044 0 4>; 816 }; 817 }; 818 819 thermal-zones { 820 sensor_thermal1: sensor1-thermal { 821 polling-delay-passive = <250>; 822 polling-delay = <1000>; 823 thermal-sensors = <&tsc 0>; 824 825 trips { 826 sensor1_crit: sensor1-crit { 827 temperature = <120000>; 828 hysteresis = <1000>; 829 type = "critical"; 830 }; 831 }; 832 }; 833 834 sensor_thermal2: sensor2-thermal { 835 polling-delay-passive = <250>; 836 polling-delay = <1000>; 837 thermal-sensors = <&tsc 1>; 838 839 trips { 840 sensor2_crit: sensor2-crit { 841 temperature = <120000>; 842 hysteresis = <1000>; 843 type = "critical"; 844 }; 845 }; 846 }; 847 848 sensor_thermal3: sensor3-thermal { 849 polling-delay-passive = <250>; 850 polling-delay = <1000>; 851 thermal-sensors = <&tsc 2>; 852 853 trips { 854 sensor3_crit: sensor3-crit { 855 temperature = <120000>; 856 hysteresis = <1000>; 857 type = "critical"; 858 }; 859 }; 860 }; 861 }; 862 863 timer { 864 compatible = "arm,armv8-timer"; 865 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 866 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 867 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 868 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 869 }; 870 871 ufs30_clk: ufs30-clk { 872 compatible = "fixed-clock"; 873 #clock-cells = <0>; 874 /* This value must be overridden by the board */ 875 clock-frequency = <0>; 876 }; 877}; 878