xref: /linux/scripts/dtc/include-prefixes/arm64/renesas/r8a779f0.dtsi (revision c29a017f9df34d190fbc7917d30dbefce7d9dc1f)
1// SPDX-License-Identifier: (GPL-2.0 or MIT)
2/*
3 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/power/r8a779f0-sysc.h>
11
12/ {
13	compatible = "renesas,r8a779f0";
14	#address-cells = <2>;
15	#size-cells = <2>;
16
17	cpus {
18		#address-cells = <1>;
19		#size-cells = <0>;
20
21		cpu-map {
22			cluster0 {
23				core0 {
24					cpu = <&a55_0>;
25				};
26				core1 {
27					cpu = <&a55_1>;
28				};
29			};
30
31			cluster1 {
32				core0 {
33					cpu = <&a55_2>;
34				};
35				core1 {
36					cpu = <&a55_3>;
37				};
38			};
39
40			cluster2 {
41				core0 {
42					cpu = <&a55_4>;
43				};
44				core1 {
45					cpu = <&a55_5>;
46				};
47			};
48
49			cluster3 {
50				core0 {
51					cpu = <&a55_6>;
52				};
53				core1 {
54					cpu = <&a55_7>;
55				};
56			};
57		};
58
59		a55_0: cpu@0 {
60			compatible = "arm,cortex-a55";
61			reg = <0>;
62			device_type = "cpu";
63			power-domains = <&sysc R8A779F0_PD_A1E0D0C0>;
64			next-level-cache = <&L3_CA55_0>;
65			enable-method = "psci";
66			cpu-idle-states = <&CPU_SLEEP_0>;
67			clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
68		};
69
70		a55_1: cpu@100 {
71			compatible = "arm,cortex-a55";
72			reg = <0x100>;
73			device_type = "cpu";
74			power-domains = <&sysc R8A779F0_PD_A1E0D0C1>;
75			next-level-cache = <&L3_CA55_0>;
76			enable-method = "psci";
77			cpu-idle-states = <&CPU_SLEEP_0>;
78			clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
79		};
80
81		a55_2: cpu@10000 {
82			compatible = "arm,cortex-a55";
83			reg = <0x10000>;
84			device_type = "cpu";
85			power-domains = <&sysc R8A779F0_PD_A1E0D1C0>;
86			next-level-cache = <&L3_CA55_1>;
87			enable-method = "psci";
88			cpu-idle-states = <&CPU_SLEEP_0>;
89			clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
90		};
91
92		a55_3: cpu@10100 {
93			compatible = "arm,cortex-a55";
94			reg = <0x10100>;
95			device_type = "cpu";
96			power-domains = <&sysc R8A779F0_PD_A1E0D1C1>;
97			next-level-cache = <&L3_CA55_1>;
98			enable-method = "psci";
99			cpu-idle-states = <&CPU_SLEEP_0>;
100			clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
101		};
102
103		a55_4: cpu@20000 {
104			compatible = "arm,cortex-a55";
105			reg = <0x20000>;
106			device_type = "cpu";
107			power-domains = <&sysc R8A779F0_PD_A1E1D0C0>;
108			next-level-cache = <&L3_CA55_2>;
109			enable-method = "psci";
110			cpu-idle-states = <&CPU_SLEEP_0>;
111			clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
112		};
113
114		a55_5: cpu@20100 {
115			compatible = "arm,cortex-a55";
116			reg = <0x20100>;
117			device_type = "cpu";
118			power-domains = <&sysc R8A779F0_PD_A1E1D0C1>;
119			next-level-cache = <&L3_CA55_2>;
120			enable-method = "psci";
121			cpu-idle-states = <&CPU_SLEEP_0>;
122			clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
123		};
124
125		a55_6: cpu@30000 {
126			compatible = "arm,cortex-a55";
127			reg = <0x30000>;
128			device_type = "cpu";
129			power-domains = <&sysc R8A779F0_PD_A1E1D1C0>;
130			next-level-cache = <&L3_CA55_3>;
131			enable-method = "psci";
132			cpu-idle-states = <&CPU_SLEEP_0>;
133			clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
134		};
135
136		a55_7: cpu@30100 {
137			compatible = "arm,cortex-a55";
138			reg = <0x30100>;
139			device_type = "cpu";
140			power-domains = <&sysc R8A779F0_PD_A1E1D1C1>;
141			next-level-cache = <&L3_CA55_3>;
142			enable-method = "psci";
143			cpu-idle-states = <&CPU_SLEEP_0>;
144			clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
145		};
146
147		L3_CA55_0: cache-controller-0 {
148			compatible = "cache";
149			power-domains = <&sysc R8A779F0_PD_A2E0D0>;
150			cache-unified;
151			cache-level = <3>;
152		};
153
154		L3_CA55_1: cache-controller-1 {
155			compatible = "cache";
156			power-domains = <&sysc R8A779F0_PD_A2E0D1>;
157			cache-unified;
158			cache-level = <3>;
159		};
160
161		L3_CA55_2: cache-controller-2 {
162			compatible = "cache";
163			power-domains = <&sysc R8A779F0_PD_A2E1D0>;
164			cache-unified;
165			cache-level = <3>;
166		};
167
168		L3_CA55_3: cache-controller-3 {
169			compatible = "cache";
170			power-domains = <&sysc R8A779F0_PD_A2E1D1>;
171			cache-unified;
172			cache-level = <3>;
173		};
174
175		idle-states {
176			entry-method = "psci";
177
178			CPU_SLEEP_0: cpu-sleep-0 {
179				compatible = "arm,idle-state";
180				arm,psci-suspend-param = <0x0010000>;
181				local-timer-stop;
182				entry-latency-us = <400>;
183				exit-latency-us = <500>;
184				min-residency-us = <4000>;
185			};
186		};
187	};
188
189	extal_clk: extal {
190		compatible = "fixed-clock";
191		#clock-cells = <0>;
192		/* This value must be overridden by the board */
193		clock-frequency = <0>;
194	};
195
196	extalr_clk: extalr {
197		compatible = "fixed-clock";
198		#clock-cells = <0>;
199		/* This value must be overridden by the board */
200		clock-frequency = <0>;
201	};
202
203	pmu_a55 {
204		compatible = "arm,cortex-a55-pmu";
205		interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
206	};
207
208	psci {
209		compatible = "arm,psci-1.0", "arm,psci-0.2";
210		method = "smc";
211	};
212
213	/* External SCIF clock - to be overridden by boards that provide it */
214	scif_clk: scif {
215		compatible = "fixed-clock";
216		#clock-cells = <0>;
217		clock-frequency = <0>;
218	};
219
220	soc: soc {
221		compatible = "simple-bus";
222		interrupt-parent = <&gic>;
223		#address-cells = <2>;
224		#size-cells = <2>;
225		ranges;
226
227		rwdt: watchdog@e6020000 {
228			compatible = "renesas,r8a779f0-wdt",
229				     "renesas,rcar-gen4-wdt";
230			reg = <0 0xe6020000 0 0x0c>;
231			interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>;
232			clocks = <&cpg CPG_MOD 907>;
233			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
234			resets = <&cpg 907>;
235			status = "disabled";
236		};
237
238		pfc: pinctrl@e6050000 {
239			compatible = "renesas,pfc-r8a779f0";
240			reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
241			      <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>;
242		};
243
244		gpio0: gpio@e6050180 {
245			compatible = "renesas,gpio-r8a779f0",
246				     "renesas,rcar-gen4-gpio";
247			reg = <0 0xe6050180 0 0x54>;
248			interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
249			clocks = <&cpg CPG_MOD 915>;
250			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
251			resets = <&cpg 915>;
252			gpio-controller;
253			#gpio-cells = <2>;
254			gpio-ranges = <&pfc 0 0 21>;
255			interrupt-controller;
256			#interrupt-cells = <2>;
257		};
258
259		gpio1: gpio@e6050980 {
260			compatible = "renesas,gpio-r8a779f0",
261				     "renesas,rcar-gen4-gpio";
262			reg = <0 0xe6050980 0 0x54>;
263			interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
264			clocks = <&cpg CPG_MOD 915>;
265			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
266			resets = <&cpg 915>;
267			gpio-controller;
268			#gpio-cells = <2>;
269			gpio-ranges = <&pfc 0 32 25>;
270			interrupt-controller;
271			#interrupt-cells = <2>;
272		};
273
274		gpio2: gpio@e6051180 {
275			compatible = "renesas,gpio-r8a779f0",
276				     "renesas,rcar-gen4-gpio";
277			reg = <0 0xe6051180 0 0x54>;
278			interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
279			clocks = <&cpg CPG_MOD 915>;
280			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
281			resets = <&cpg 915>;
282			gpio-controller;
283			#gpio-cells = <2>;
284			gpio-ranges = <&pfc 0 64 17>;
285			interrupt-controller;
286			#interrupt-cells = <2>;
287		};
288
289		gpio3: gpio@e6051980 {
290			compatible = "renesas,gpio-r8a779f0",
291				     "renesas,rcar-gen4-gpio";
292			reg = <0 0xe6051980 0 0x54>;
293			interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
294			clocks = <&cpg CPG_MOD 915>;
295			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
296			resets = <&cpg 915>;
297			gpio-controller;
298			#gpio-cells = <2>;
299			gpio-ranges = <&pfc 0 96 19>;
300			interrupt-controller;
301			#interrupt-cells = <2>;
302		};
303
304		cmt0: timer@e60f0000 {
305			compatible = "renesas,r8a779f0-cmt0",
306				     "renesas,rcar-gen4-cmt0";
307			reg = <0 0xe60f0000 0 0x1004>;
308			interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
309				     <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>;
310			clocks = <&cpg CPG_MOD 910>;
311			clock-names = "fck";
312			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
313			resets = <&cpg 910>;
314			status = "disabled";
315		};
316
317		cmt1: timer@e6130000 {
318			compatible = "renesas,r8a779f0-cmt1",
319				     "renesas,rcar-gen4-cmt1";
320			reg = <0 0xe6130000 0 0x1004>;
321			interrupts = <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
322				     <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
323				     <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
324				     <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
325				     <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
326				     <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
327				     <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
328				     <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>;
329			clocks = <&cpg CPG_MOD 911>;
330			clock-names = "fck";
331			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
332			resets = <&cpg 911>;
333			status = "disabled";
334		};
335
336		cmt2: timer@e6140000 {
337			compatible = "renesas,r8a779f0-cmt1",
338				     "renesas,rcar-gen4-cmt1";
339			reg = <0 0xe6140000 0 0x1004>;
340			interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
341				     <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
342				     <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
343				     <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
344				     <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
345				     <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
346				     <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
347				     <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
348			clocks = <&cpg CPG_MOD 912>;
349			clock-names = "fck";
350			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
351			resets = <&cpg 912>;
352			status = "disabled";
353		};
354
355		cmt3: timer@e6148000 {
356			compatible = "renesas,r8a779f0-cmt1",
357				     "renesas,rcar-gen4-cmt1";
358			reg = <0 0xe6148000 0 0x1004>;
359			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
360				     <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
361				     <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
362				     <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
363				     <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
364				     <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
365				     <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
366				     <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
367			clocks = <&cpg CPG_MOD 913>;
368			clock-names = "fck";
369			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
370			resets = <&cpg 913>;
371			status = "disabled";
372		};
373
374		cpg: clock-controller@e6150000 {
375			compatible = "renesas,r8a779f0-cpg-mssr";
376			reg = <0 0xe6150000 0 0x4000>;
377			clocks = <&extal_clk>, <&extalr_clk>;
378			clock-names = "extal", "extalr";
379			#clock-cells = <2>;
380			#power-domain-cells = <0>;
381			#reset-cells = <1>;
382		};
383
384		rst: reset-controller@e6160000 {
385			compatible = "renesas,r8a779f0-rst";
386			reg = <0 0xe6160000 0 0x4000>;
387		};
388
389		sysc: system-controller@e6180000 {
390			compatible = "renesas,r8a779f0-sysc";
391			reg = <0 0xe6180000 0 0x4000>;
392			#power-domain-cells = <1>;
393		};
394
395		tsc: thermal@e6198000 {
396			compatible = "renesas,r8a779f0-thermal";
397			/* The 4th sensor is in control domain and not for Linux */
398			reg = <0 0xe6198000 0 0x200>,
399			      <0 0xe61a0000 0 0x200>,
400			      <0 0xe61a8000 0 0x200>;
401			clocks = <&cpg CPG_MOD 919>;
402			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
403			resets = <&cpg 919>;
404			#thermal-sensor-cells = <1>;
405		};
406
407		tmu0: timer@e61e0000 {
408			compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
409			reg = <0 0xe61e0000 0 0x30>;
410			interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
411				     <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
412				     <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;
413			clocks = <&cpg CPG_MOD 713>;
414			clock-names = "fck";
415			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
416			resets = <&cpg 713>;
417			status = "disabled";
418		};
419
420		tmu1: timer@e6fc0000 {
421			compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
422			reg = <0 0xe6fc0000 0 0x30>;
423			interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
424				     <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
425				     <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>;
426			clocks = <&cpg CPG_MOD 714>;
427			clock-names = "fck";
428			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
429			resets = <&cpg 714>;
430			status = "disabled";
431		};
432
433		tmu2: timer@e6fd0000 {
434			compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
435			reg = <0 0xe6fd0000 0 0x30>;
436			interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>,
437				     <GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>,
438				     <GIC_SPI 483 IRQ_TYPE_LEVEL_HIGH>;
439			clocks = <&cpg CPG_MOD 715>;
440			clock-names = "fck";
441			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
442			resets = <&cpg 715>;
443			status = "disabled";
444		};
445
446		tmu3: timer@e6fe0000 {
447			compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
448			reg = <0 0xe6fe0000 0 0x30>;
449			interrupts = <GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH>,
450				     <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
451				     <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>;
452			clocks = <&cpg CPG_MOD 716>;
453			clock-names = "fck";
454			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
455			resets = <&cpg 716>;
456			status = "disabled";
457		};
458
459		tmu4: timer@ffc00000 {
460			compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
461			reg = <0 0xffc00000 0 0x30>;
462			interrupts = <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>,
463				     <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
464				     <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
465			clocks = <&cpg CPG_MOD 717>;
466			clock-names = "fck";
467			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
468			resets = <&cpg 717>;
469			status = "disabled";
470		};
471
472		i2c0: i2c@e6500000 {
473			compatible = "renesas,i2c-r8a779f0",
474				     "renesas,rcar-gen4-i2c";
475			reg = <0 0xe6500000 0 0x40>;
476			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
477			clocks = <&cpg CPG_MOD 518>;
478			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
479			resets = <&cpg 518>;
480			dmas = <&dmac0 0x91>, <&dmac0 0x90>,
481			       <&dmac1 0x91>, <&dmac1 0x90>;
482			dma-names = "tx", "rx", "tx", "rx";
483			i2c-scl-internal-delay-ns = <110>;
484			#address-cells = <1>;
485			#size-cells = <0>;
486			status = "disabled";
487		};
488
489		i2c1: i2c@e6508000 {
490			compatible = "renesas,i2c-r8a779f0",
491				     "renesas,rcar-gen4-i2c";
492			reg = <0 0xe6508000 0 0x40>;
493			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
494			clocks = <&cpg CPG_MOD 519>;
495			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
496			resets = <&cpg 519>;
497			dmas = <&dmac0 0x93>, <&dmac0 0x92>,
498			       <&dmac1 0x93>, <&dmac1 0x92>;
499			dma-names = "tx", "rx", "tx", "rx";
500			i2c-scl-internal-delay-ns = <110>;
501			#address-cells = <1>;
502			#size-cells = <0>;
503			status = "disabled";
504		};
505
506		i2c2: i2c@e6510000 {
507			compatible = "renesas,i2c-r8a779f0",
508				     "renesas,rcar-gen4-i2c";
509			reg = <0 0xe6510000 0 0x40>;
510			interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>;
511			clocks = <&cpg CPG_MOD 520>;
512			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
513			resets = <&cpg 520>;
514			dmas = <&dmac0 0x95>, <&dmac0 0x94>,
515			       <&dmac1 0x95>, <&dmac1 0x94>;
516			dma-names = "tx", "rx", "tx", "rx";
517			i2c-scl-internal-delay-ns = <110>;
518			#address-cells = <1>;
519			#size-cells = <0>;
520			status = "disabled";
521		};
522
523		i2c3: i2c@e66d0000 {
524			compatible = "renesas,i2c-r8a779f0",
525				     "renesas,rcar-gen4-i2c";
526			reg = <0 0xe66d0000 0 0x40>;
527			interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
528			clocks = <&cpg CPG_MOD 521>;
529			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
530			resets = <&cpg 521>;
531			dmas = <&dmac0 0x97>, <&dmac0 0x96>,
532			       <&dmac1 0x97>, <&dmac1 0x96>;
533			dma-names = "tx", "rx", "tx", "rx";
534			i2c-scl-internal-delay-ns = <110>;
535			#address-cells = <1>;
536			#size-cells = <0>;
537			status = "disabled";
538		};
539
540		i2c4: i2c@e66d8000 {
541			compatible = "renesas,i2c-r8a779f0",
542				     "renesas,rcar-gen4-i2c";
543			reg = <0 0xe66d8000 0 0x40>;
544			interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
545			clocks = <&cpg CPG_MOD 522>;
546			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
547			resets = <&cpg 522>;
548			dmas = <&dmac0 0x99>, <&dmac0 0x98>,
549			       <&dmac1 0x99>, <&dmac1 0x98>;
550			dma-names = "tx", "rx", "tx", "rx";
551			i2c-scl-internal-delay-ns = <110>;
552			#address-cells = <1>;
553			#size-cells = <0>;
554			status = "disabled";
555		};
556
557		i2c5: i2c@e66e0000 {
558			compatible = "renesas,i2c-r8a779f0",
559				     "renesas,rcar-gen4-i2c";
560			reg = <0 0xe66e0000 0 0x40>;
561			interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
562			clocks = <&cpg CPG_MOD 523>;
563			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
564			resets = <&cpg 523>;
565			dmas = <&dmac0 0x9b>, <&dmac0 0x9a>,
566			       <&dmac1 0x9b>, <&dmac1 0x9a>;
567			dma-names = "tx", "rx", "tx", "rx";
568			i2c-scl-internal-delay-ns = <110>;
569			#address-cells = <1>;
570			#size-cells = <0>;
571			status = "disabled";
572		};
573
574		hscif0: serial@e6540000 {
575			compatible = "renesas,hscif-r8a779f0",
576				     "renesas,rcar-gen4-hscif", "renesas,hscif";
577			reg = <0 0xe6540000 0 0x60>;
578			interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
579			clocks = <&cpg CPG_MOD 514>,
580				 <&cpg CPG_CORE R8A779F0_CLK_S0D3>,
581				 <&scif_clk>;
582			clock-names = "fck", "brg_int", "scif_clk";
583			dmas = <&dmac0 0x31>, <&dmac0 0x30>,
584			       <&dmac1 0x31>, <&dmac1 0x30>;
585			dma-names = "tx", "rx", "tx", "rx";
586			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
587			resets = <&cpg 514>;
588			status = "disabled";
589		};
590
591		hscif1: serial@e6550000 {
592			compatible = "renesas,hscif-r8a779f0",
593				     "renesas,rcar-gen4-hscif", "renesas,hscif";
594			reg = <0 0xe6550000 0 0x60>;
595			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
596			clocks = <&cpg CPG_MOD 515>,
597				 <&cpg CPG_CORE R8A779F0_CLK_S0D3>,
598				 <&scif_clk>;
599			clock-names = "fck", "brg_int", "scif_clk";
600			dmas = <&dmac0 0x33>, <&dmac0 0x32>,
601			       <&dmac1 0x33>, <&dmac1 0x32>;
602			dma-names = "tx", "rx", "tx", "rx";
603			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
604			resets = <&cpg 515>;
605			status = "disabled";
606		};
607
608		hscif2: serial@e6560000 {
609			compatible = "renesas,hscif-r8a779f0",
610				     "renesas,rcar-gen4-hscif", "renesas,hscif";
611			reg = <0 0xe6560000 0 0x60>;
612			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
613			clocks = <&cpg CPG_MOD 516>,
614				 <&cpg CPG_CORE R8A779F0_CLK_S0D3>,
615				 <&scif_clk>;
616			clock-names = "fck", "brg_int", "scif_clk";
617			dmas = <&dmac0 0x35>, <&dmac0 0x34>,
618			       <&dmac1 0x35>, <&dmac1 0x34>;
619			dma-names = "tx", "rx", "tx", "rx";
620			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
621			resets = <&cpg 516>;
622			status = "disabled";
623		};
624
625		hscif3: serial@e66a0000 {
626			compatible = "renesas,hscif-r8a779f0",
627				     "renesas,rcar-gen4-hscif", "renesas,hscif";
628			reg = <0 0xe66a0000 0 0x60>;
629			interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
630			clocks = <&cpg CPG_MOD 517>,
631				 <&cpg CPG_CORE R8A779F0_CLK_S0D3>,
632				 <&scif_clk>;
633			clock-names = "fck", "brg_int", "scif_clk";
634			dmas = <&dmac0 0x37>, <&dmac0 0x36>,
635			       <&dmac1 0x37>, <&dmac1 0x36>;
636			dma-names = "tx", "rx", "tx", "rx";
637			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
638			resets = <&cpg 517>;
639			status = "disabled";
640		};
641
642		ufs: ufs@e6860000 {
643			compatible = "renesas,r8a779f0-ufs";
644			reg = <0 0xe6860000 0 0x100>;
645			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
646			clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>;
647			clock-names = "fck", "ref_clk";
648			freq-table-hz = <200000000 200000000>, <38400000 38400000>;
649			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
650			resets = <&cpg 1514>;
651			status = "disabled";
652		};
653
654		scif0: serial@e6e60000 {
655			compatible = "renesas,scif-r8a779f0",
656				     "renesas,rcar-gen4-scif", "renesas,scif";
657			reg = <0 0xe6e60000 0 64>;
658			interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
659			clocks = <&cpg CPG_MOD 702>,
660				 <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>,
661				 <&scif_clk>;
662			clock-names = "fck", "brg_int", "scif_clk";
663			dmas = <&dmac0 0x51>, <&dmac0 0x50>,
664			       <&dmac1 0x51>, <&dmac1 0x50>;
665			dma-names = "tx", "rx", "tx", "rx";
666			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
667			resets = <&cpg 702>;
668			status = "disabled";
669		};
670
671		scif1: serial@e6e68000 {
672			compatible = "renesas,scif-r8a779f0",
673				     "renesas,rcar-gen4-scif", "renesas,scif";
674			reg = <0 0xe6e68000 0 64>;
675			interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
676			clocks = <&cpg CPG_MOD 703>,
677				 <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>,
678				 <&scif_clk>;
679			clock-names = "fck", "brg_int", "scif_clk";
680			dmas = <&dmac0 0x53>, <&dmac0 0x52>,
681			       <&dmac1 0x53>, <&dmac1 0x52>;
682			dma-names = "tx", "rx", "tx", "rx";
683			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
684			resets = <&cpg 703>;
685			status = "disabled";
686		};
687
688		scif3: serial@e6c50000 {
689			compatible = "renesas,scif-r8a779f0",
690				     "renesas,rcar-gen4-scif", "renesas,scif";
691			reg = <0 0xe6c50000 0 64>;
692			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
693			clocks = <&cpg CPG_MOD 704>,
694				 <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>,
695				 <&scif_clk>;
696			clock-names = "fck", "brg_int", "scif_clk";
697			dmas = <&dmac0 0x57>, <&dmac0 0x56>,
698			       <&dmac1 0x57>, <&dmac1 0x56>;
699			dma-names = "tx", "rx", "tx", "rx";
700			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
701			resets = <&cpg 704>;
702			status = "disabled";
703		};
704
705		scif4: serial@e6c40000 {
706			compatible = "renesas,scif-r8a779f0",
707				     "renesas,rcar-gen4-scif", "renesas,scif";
708			reg = <0 0xe6c40000 0 64>;
709			interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
710			clocks = <&cpg CPG_MOD 705>,
711				 <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>,
712				 <&scif_clk>;
713			clock-names = "fck", "brg_int", "scif_clk";
714			dmas = <&dmac0 0x59>, <&dmac0 0x58>,
715			       <&dmac1 0x59>, <&dmac1 0x58>;
716			dma-names = "tx", "rx", "tx", "rx";
717			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
718			resets = <&cpg 705>;
719			status = "disabled";
720		};
721
722		msiof0: spi@e6e90000 {
723			compatible = "renesas,msiof-r8a779f0",
724				     "renesas,rcar-gen4-msiof";
725			reg = <0 0xe6e90000 0 0x0064>;
726			interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
727			clocks = <&cpg CPG_MOD 618>;
728			dmas = <&dmac0 0x41>, <&dmac0 0x40>,
729			       <&dmac1 0x41>, <&dmac1 0x40>;
730			dma-names = "tx", "rx", "tx", "rx";
731			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
732			resets = <&cpg 618>;
733			#address-cells = <1>;
734			#size-cells = <0>;
735			status = "disabled";
736		};
737
738		msiof1: spi@e6ea0000 {
739			compatible = "renesas,msiof-r8a779f0",
740				     "renesas,rcar-gen4-msiof";
741			reg = <0 0xe6ea0000 0 0x0064>;
742			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
743			clocks = <&cpg CPG_MOD 619>;
744			dmas = <&dmac0 0x43>, <&dmac0 0x42>,
745			       <&dmac1 0x43>, <&dmac1 0x42>;
746			dma-names = "tx", "rx", "tx", "rx";
747			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
748			resets = <&cpg 619>;
749			#address-cells = <1>;
750			#size-cells = <0>;
751			status = "disabled";
752		};
753
754		msiof2: spi@e6c00000 {
755			compatible = "renesas,msiof-r8a779f0",
756				     "renesas,rcar-gen4-msiof";
757			reg = <0 0xe6c00000 0 0x0064>;
758			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
759			clocks = <&cpg CPG_MOD 620>;
760			dmas = <&dmac0 0x45>, <&dmac0 0x44>,
761			       <&dmac1 0x45>, <&dmac1 0x44>;
762			dma-names = "tx", "rx", "tx", "rx";
763			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
764			resets = <&cpg 620>;
765			#address-cells = <1>;
766			#size-cells = <0>;
767			status = "disabled";
768		};
769
770		msiof3: spi@e6c10000 {
771			compatible = "renesas,msiof-r8a779f0",
772				     "renesas,rcar-gen4-msiof";
773			reg = <0 0xe6c10000 0 0x0064>;
774			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
775			clocks = <&cpg CPG_MOD 621>;
776			dmas = <&dmac0 0x47>, <&dmac0 0x46>,
777			       <&dmac1 0x47>, <&dmac1 0x46>;
778			dma-names = "tx", "rx", "tx", "rx";
779			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
780			resets = <&cpg 621>;
781			#address-cells = <1>;
782			#size-cells = <0>;
783			status = "disabled";
784		};
785
786		dmac0: dma-controller@e7350000 {
787			compatible = "renesas,dmac-r8a779f0",
788				     "renesas,rcar-gen4-dmac";
789			reg = <0 0xe7350000 0 0x1000>,
790			      <0 0xe7300000 0 0x10000>;
791			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
792				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
793				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
794				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
795				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
796				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
797				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
798				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
799				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
800				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
801				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
802				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
803				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
804				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
805				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
806				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
807				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
808			interrupt-names = "error",
809					  "ch0", "ch1", "ch2", "ch3", "ch4",
810					  "ch5", "ch6", "ch7", "ch8", "ch9",
811					  "ch10", "ch11", "ch12", "ch13",
812					  "ch14", "ch15";
813			clocks = <&cpg CPG_MOD 709>;
814			clock-names = "fck";
815			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
816			resets = <&cpg 709>;
817			#dma-cells = <1>;
818			dma-channels = <16>;
819			iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
820				 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
821				 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
822				 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
823				 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
824				 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
825				 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
826				 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
827		};
828
829		dmac1: dma-controller@e7351000 {
830			compatible = "renesas,dmac-r8a779f0",
831				     "renesas,rcar-gen4-dmac";
832			reg = <0 0xe7351000 0 0x1000>,
833			      <0 0xe7310000 0 0x10000>;
834			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
835				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
836				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
837				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
838				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
839				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
840				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
841				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
842				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
843				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
844				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
845				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
846				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
847				     <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
848				     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
849				     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
850				     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
851			interrupt-names = "error",
852					  "ch0", "ch1", "ch2", "ch3", "ch4",
853					  "ch5", "ch6", "ch7", "ch8", "ch9",
854					  "ch10", "ch11", "ch12", "ch13",
855					  "ch14", "ch15";
856			clocks = <&cpg CPG_MOD 710>;
857			clock-names = "fck";
858			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
859			resets = <&cpg 710>;
860			#dma-cells = <1>;
861			dma-channels = <16>;
862			iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>,
863				 <&ipmmu_ds0 18>, <&ipmmu_ds0 19>,
864				 <&ipmmu_ds0 20>, <&ipmmu_ds0 21>,
865				 <&ipmmu_ds0 22>, <&ipmmu_ds0 23>,
866				 <&ipmmu_ds0 24>, <&ipmmu_ds0 25>,
867				 <&ipmmu_ds0 26>, <&ipmmu_ds0 27>,
868				 <&ipmmu_ds0 28>, <&ipmmu_ds0 29>,
869				 <&ipmmu_ds0 30>, <&ipmmu_ds0 31>;
870		};
871
872		mmc0: mmc@ee140000 {
873			compatible = "renesas,sdhi-r8a779f0",
874				     "renesas,rcar-gen4-sdhi";
875			reg = <0 0xee140000 0 0x2000>;
876			interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
877			clocks = <&cpg CPG_MOD 706>, <&cpg CPG_CORE R8A779F0_CLK_SD0H>;
878			clock-names = "core", "clkh";
879			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
880			resets = <&cpg 706>;
881			max-frequency = <200000000>;
882			status = "disabled";
883		};
884
885		ipmmu_rt0: iommu@ee480000 {
886			compatible = "renesas,ipmmu-r8a779f0",
887				     "renesas,rcar-gen4-ipmmu-vmsa";
888			reg = <0 0xee480000 0 0x20000>;
889			renesas,ipmmu-main = <&ipmmu_mm 10>;
890			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
891			#iommu-cells = <1>;
892		};
893
894		ipmmu_rt1: iommu@ee4c0000 {
895			compatible = "renesas,ipmmu-r8a779f0",
896				     "renesas,rcar-gen4-ipmmu-vmsa";
897			reg = <0 0xee4c0000 0 0x20000>;
898			renesas,ipmmu-main = <&ipmmu_mm 19>;
899			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
900			#iommu-cells = <1>;
901		};
902
903		ipmmu_ds0: iommu@eed00000 {
904			compatible = "renesas,ipmmu-r8a779f0",
905				     "renesas,rcar-gen4-ipmmu-vmsa";
906			reg = <0 0xeed00000 0 0x20000>;
907			renesas,ipmmu-main = <&ipmmu_mm 0>;
908			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
909			#iommu-cells = <1>;
910		};
911
912		ipmmu_hc: iommu@eed40000 {
913			compatible = "renesas,ipmmu-r8a779f0",
914				     "renesas,rcar-gen4-ipmmu-vmsa";
915			reg = <0 0xeed40000 0 0x20000>;
916			renesas,ipmmu-main = <&ipmmu_mm 2>;
917			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
918			#iommu-cells = <1>;
919		};
920
921		ipmmu_mm: iommu@eefc0000 {
922			compatible = "renesas,ipmmu-r8a779f0",
923				     "renesas,rcar-gen4-ipmmu-vmsa";
924			reg = <0 0xeefc0000 0 0x20000>;
925			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
926				     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
927			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
928			#iommu-cells = <1>;
929		};
930
931		gic: interrupt-controller@f1000000 {
932			compatible = "arm,gic-v3";
933			#interrupt-cells = <3>;
934			#address-cells = <0>;
935			interrupt-controller;
936			reg = <0x0 0xf1000000 0 0x20000>,
937			      <0x0 0xf1060000 0 0x110000>;
938			interrupts = <GIC_PPI 9
939				      (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
940		};
941
942		prr: chipid@fff00044 {
943			compatible = "renesas,prr";
944			reg = <0 0xfff00044 0 4>;
945		};
946	};
947
948	thermal-zones {
949		sensor_thermal1: sensor1-thermal {
950			polling-delay-passive = <250>;
951			polling-delay = <1000>;
952			thermal-sensors = <&tsc 0>;
953
954			trips {
955				sensor1_crit: sensor1-crit {
956					temperature = <120000>;
957					hysteresis = <1000>;
958					type = "critical";
959				};
960			};
961		};
962
963		sensor_thermal2: sensor2-thermal {
964			polling-delay-passive = <250>;
965			polling-delay = <1000>;
966			thermal-sensors = <&tsc 1>;
967
968			trips {
969				sensor2_crit: sensor2-crit {
970					temperature = <120000>;
971					hysteresis = <1000>;
972					type = "critical";
973				};
974			};
975		};
976
977		sensor_thermal3: sensor3-thermal {
978			polling-delay-passive = <250>;
979			polling-delay = <1000>;
980			thermal-sensors = <&tsc 2>;
981
982			trips {
983				sensor3_crit: sensor3-crit {
984					temperature = <120000>;
985					hysteresis = <1000>;
986					type = "critical";
987				};
988			};
989		};
990	};
991
992	timer {
993		compatible = "arm,armv8-timer";
994		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
995				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
996				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
997				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
998	};
999
1000	ufs30_clk: ufs30-clk {
1001		compatible = "fixed-clock";
1002		#clock-cells = <0>;
1003		/* This value must be overridden by the board */
1004		clock-frequency = <0>;
1005	};
1006};
1007