1// SPDX-License-Identifier: (GPL-2.0 or MIT) 2/* 3 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a779f0-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a779f0-sysc.h> 11 12/ { 13 compatible = "renesas,r8a779f0"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 cluster01_opp: opp-table-0 { 18 compatible = "operating-points-v2"; 19 opp-shared; 20 21 opp-500000000 { 22 opp-hz = /bits/ 64 <500000000>; 23 opp-microvolt = <880000>; 24 clock-latency-ns = <500000>; 25 }; 26 opp-800000000 { 27 opp-hz = /bits/ 64 <800000000>; 28 opp-microvolt = <880000>; 29 clock-latency-ns = <500000>; 30 }; 31 opp-1000000000 { 32 opp-hz = /bits/ 64 <1000000000>; 33 opp-microvolt = <880000>; 34 clock-latency-ns = <500000>; 35 }; 36 opp-1200000000 { 37 opp-hz = /bits/ 64 <1200000000>; 38 opp-microvolt = <880000>; 39 clock-latency-ns = <500000>; 40 opp-suspend; 41 }; 42 }; 43 44 cluster23_opp: opp-table-1 { 45 compatible = "operating-points-v2"; 46 opp-shared; 47 48 opp-500000000 { 49 opp-hz = /bits/ 64 <500000000>; 50 opp-microvolt = <880000>; 51 clock-latency-ns = <500000>; 52 }; 53 opp-800000000 { 54 opp-hz = /bits/ 64 <800000000>; 55 opp-microvolt = <880000>; 56 clock-latency-ns = <500000>; 57 }; 58 opp-1000000000 { 59 opp-hz = /bits/ 64 <1000000000>; 60 opp-microvolt = <880000>; 61 clock-latency-ns = <500000>; 62 }; 63 opp-1200000000 { 64 opp-hz = /bits/ 64 <1200000000>; 65 opp-microvolt = <880000>; 66 clock-latency-ns = <500000>; 67 opp-suspend; 68 }; 69 }; 70 71 cpus { 72 #address-cells = <1>; 73 #size-cells = <0>; 74 75 cpu-map { 76 cluster0 { 77 core0 { 78 cpu = <&a55_0>; 79 }; 80 core1 { 81 cpu = <&a55_1>; 82 }; 83 }; 84 85 cluster1 { 86 core0 { 87 cpu = <&a55_2>; 88 }; 89 core1 { 90 cpu = <&a55_3>; 91 }; 92 }; 93 94 cluster2 { 95 core0 { 96 cpu = <&a55_4>; 97 }; 98 core1 { 99 cpu = <&a55_5>; 100 }; 101 }; 102 103 cluster3 { 104 core0 { 105 cpu = <&a55_6>; 106 }; 107 core1 { 108 cpu = <&a55_7>; 109 }; 110 }; 111 }; 112 113 a55_0: cpu@0 { 114 compatible = "arm,cortex-a55"; 115 reg = <0>; 116 device_type = "cpu"; 117 power-domains = <&sysc R8A779F0_PD_A1E0D0C0>; 118 next-level-cache = <&L3_CA55_0>; 119 enable-method = "psci"; 120 cpu-idle-states = <&CPU_SLEEP_0>; 121 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; 122 operating-points-v2 = <&cluster01_opp>; 123 }; 124 125 a55_1: cpu@100 { 126 compatible = "arm,cortex-a55"; 127 reg = <0x100>; 128 device_type = "cpu"; 129 power-domains = <&sysc R8A779F0_PD_A1E0D0C1>; 130 next-level-cache = <&L3_CA55_0>; 131 enable-method = "psci"; 132 cpu-idle-states = <&CPU_SLEEP_0>; 133 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; 134 operating-points-v2 = <&cluster01_opp>; 135 }; 136 137 a55_2: cpu@10000 { 138 compatible = "arm,cortex-a55"; 139 reg = <0x10000>; 140 device_type = "cpu"; 141 power-domains = <&sysc R8A779F0_PD_A1E0D1C0>; 142 next-level-cache = <&L3_CA55_1>; 143 enable-method = "psci"; 144 cpu-idle-states = <&CPU_SLEEP_0>; 145 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; 146 operating-points-v2 = <&cluster01_opp>; 147 }; 148 149 a55_3: cpu@10100 { 150 compatible = "arm,cortex-a55"; 151 reg = <0x10100>; 152 device_type = "cpu"; 153 power-domains = <&sysc R8A779F0_PD_A1E0D1C1>; 154 next-level-cache = <&L3_CA55_1>; 155 enable-method = "psci"; 156 cpu-idle-states = <&CPU_SLEEP_0>; 157 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; 158 operating-points-v2 = <&cluster01_opp>; 159 }; 160 161 a55_4: cpu@20000 { 162 compatible = "arm,cortex-a55"; 163 reg = <0x20000>; 164 device_type = "cpu"; 165 power-domains = <&sysc R8A779F0_PD_A1E1D0C0>; 166 next-level-cache = <&L3_CA55_2>; 167 enable-method = "psci"; 168 cpu-idle-states = <&CPU_SLEEP_0>; 169 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; 170 operating-points-v2 = <&cluster23_opp>; 171 }; 172 173 a55_5: cpu@20100 { 174 compatible = "arm,cortex-a55"; 175 reg = <0x20100>; 176 device_type = "cpu"; 177 power-domains = <&sysc R8A779F0_PD_A1E1D0C1>; 178 next-level-cache = <&L3_CA55_2>; 179 enable-method = "psci"; 180 cpu-idle-states = <&CPU_SLEEP_0>; 181 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; 182 operating-points-v2 = <&cluster23_opp>; 183 }; 184 185 a55_6: cpu@30000 { 186 compatible = "arm,cortex-a55"; 187 reg = <0x30000>; 188 device_type = "cpu"; 189 power-domains = <&sysc R8A779F0_PD_A1E1D1C0>; 190 next-level-cache = <&L3_CA55_3>; 191 enable-method = "psci"; 192 cpu-idle-states = <&CPU_SLEEP_0>; 193 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; 194 operating-points-v2 = <&cluster23_opp>; 195 }; 196 197 a55_7: cpu@30100 { 198 compatible = "arm,cortex-a55"; 199 reg = <0x30100>; 200 device_type = "cpu"; 201 power-domains = <&sysc R8A779F0_PD_A1E1D1C1>; 202 next-level-cache = <&L3_CA55_3>; 203 enable-method = "psci"; 204 cpu-idle-states = <&CPU_SLEEP_0>; 205 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; 206 operating-points-v2 = <&cluster23_opp>; 207 }; 208 209 L3_CA55_0: cache-controller-0 { 210 compatible = "cache"; 211 power-domains = <&sysc R8A779F0_PD_A2E0D0>; 212 cache-unified; 213 cache-level = <3>; 214 }; 215 216 L3_CA55_1: cache-controller-1 { 217 compatible = "cache"; 218 power-domains = <&sysc R8A779F0_PD_A2E0D1>; 219 cache-unified; 220 cache-level = <3>; 221 }; 222 223 L3_CA55_2: cache-controller-2 { 224 compatible = "cache"; 225 power-domains = <&sysc R8A779F0_PD_A2E1D0>; 226 cache-unified; 227 cache-level = <3>; 228 }; 229 230 L3_CA55_3: cache-controller-3 { 231 compatible = "cache"; 232 power-domains = <&sysc R8A779F0_PD_A2E1D1>; 233 cache-unified; 234 cache-level = <3>; 235 }; 236 237 idle-states { 238 entry-method = "psci"; 239 240 CPU_SLEEP_0: cpu-sleep-0 { 241 compatible = "arm,idle-state"; 242 arm,psci-suspend-param = <0x0010000>; 243 local-timer-stop; 244 entry-latency-us = <400>; 245 exit-latency-us = <500>; 246 min-residency-us = <4000>; 247 }; 248 }; 249 }; 250 251 extal_clk: extal { 252 compatible = "fixed-clock"; 253 #clock-cells = <0>; 254 /* This value must be overridden by the board */ 255 clock-frequency = <0>; 256 }; 257 258 extalr_clk: extalr { 259 compatible = "fixed-clock"; 260 #clock-cells = <0>; 261 /* This value must be overridden by the board */ 262 clock-frequency = <0>; 263 }; 264 265 pmu_a55 { 266 compatible = "arm,cortex-a55-pmu"; 267 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 268 }; 269 270 psci { 271 compatible = "arm,psci-1.0", "arm,psci-0.2"; 272 method = "smc"; 273 }; 274 275 /* External SCIF clock - to be overridden by boards that provide it */ 276 scif_clk: scif { 277 compatible = "fixed-clock"; 278 #clock-cells = <0>; 279 clock-frequency = <0>; 280 }; 281 282 soc: soc { 283 compatible = "simple-bus"; 284 interrupt-parent = <&gic>; 285 #address-cells = <2>; 286 #size-cells = <2>; 287 ranges; 288 289 rwdt: watchdog@e6020000 { 290 compatible = "renesas,r8a779f0-wdt", 291 "renesas,rcar-gen4-wdt"; 292 reg = <0 0xe6020000 0 0x0c>; 293 interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&cpg CPG_MOD 907>; 295 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 296 resets = <&cpg 907>; 297 status = "disabled"; 298 }; 299 300 pfc: pinctrl@e6050000 { 301 compatible = "renesas,pfc-r8a779f0"; 302 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, 303 <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>; 304 }; 305 306 gpio0: gpio@e6050180 { 307 compatible = "renesas,gpio-r8a779f0", 308 "renesas,rcar-gen4-gpio"; 309 reg = <0 0xe6050180 0 0x54>; 310 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&cpg CPG_MOD 915>; 312 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 313 resets = <&cpg 915>; 314 gpio-controller; 315 #gpio-cells = <2>; 316 gpio-ranges = <&pfc 0 0 21>; 317 interrupt-controller; 318 #interrupt-cells = <2>; 319 }; 320 321 gpio1: gpio@e6050980 { 322 compatible = "renesas,gpio-r8a779f0", 323 "renesas,rcar-gen4-gpio"; 324 reg = <0 0xe6050980 0 0x54>; 325 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; 326 clocks = <&cpg CPG_MOD 915>; 327 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 328 resets = <&cpg 915>; 329 gpio-controller; 330 #gpio-cells = <2>; 331 gpio-ranges = <&pfc 0 32 25>; 332 interrupt-controller; 333 #interrupt-cells = <2>; 334 }; 335 336 gpio2: gpio@e6051180 { 337 compatible = "renesas,gpio-r8a779f0", 338 "renesas,rcar-gen4-gpio"; 339 reg = <0 0xe6051180 0 0x54>; 340 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; 341 clocks = <&cpg CPG_MOD 915>; 342 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 343 resets = <&cpg 915>; 344 gpio-controller; 345 #gpio-cells = <2>; 346 gpio-ranges = <&pfc 0 64 17>; 347 interrupt-controller; 348 #interrupt-cells = <2>; 349 }; 350 351 gpio3: gpio@e6051980 { 352 compatible = "renesas,gpio-r8a779f0", 353 "renesas,rcar-gen4-gpio"; 354 reg = <0 0xe6051980 0 0x54>; 355 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; 356 clocks = <&cpg CPG_MOD 915>; 357 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 358 resets = <&cpg 915>; 359 gpio-controller; 360 #gpio-cells = <2>; 361 gpio-ranges = <&pfc 0 96 19>; 362 interrupt-controller; 363 #interrupt-cells = <2>; 364 }; 365 366 cmt0: timer@e60f0000 { 367 compatible = "renesas,r8a779f0-cmt0", 368 "renesas,rcar-gen4-cmt0"; 369 reg = <0 0xe60f0000 0 0x1004>; 370 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 371 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>; 372 clocks = <&cpg CPG_MOD 910>; 373 clock-names = "fck"; 374 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 375 resets = <&cpg 910>; 376 status = "disabled"; 377 }; 378 379 cmt1: timer@e6130000 { 380 compatible = "renesas,r8a779f0-cmt1", 381 "renesas,rcar-gen4-cmt1"; 382 reg = <0 0xe6130000 0 0x1004>; 383 interrupts = <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 386 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 389 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, 390 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>; 391 clocks = <&cpg CPG_MOD 911>; 392 clock-names = "fck"; 393 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 394 resets = <&cpg 911>; 395 status = "disabled"; 396 }; 397 398 cmt2: timer@e6140000 { 399 compatible = "renesas,r8a779f0-cmt1", 400 "renesas,rcar-gen4-cmt1"; 401 reg = <0 0xe6140000 0 0x1004>; 402 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 403 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 404 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 405 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, 406 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 407 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 410 clocks = <&cpg CPG_MOD 912>; 411 clock-names = "fck"; 412 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 413 resets = <&cpg 912>; 414 status = "disabled"; 415 }; 416 417 cmt3: timer@e6148000 { 418 compatible = "renesas,r8a779f0-cmt1", 419 "renesas,rcar-gen4-cmt1"; 420 reg = <0 0xe6148000 0 0x1004>; 421 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 422 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 429 clocks = <&cpg CPG_MOD 913>; 430 clock-names = "fck"; 431 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 432 resets = <&cpg 913>; 433 status = "disabled"; 434 }; 435 436 cpg: clock-controller@e6150000 { 437 compatible = "renesas,r8a779f0-cpg-mssr"; 438 reg = <0 0xe6150000 0 0x4000>; 439 clocks = <&extal_clk>, <&extalr_clk>; 440 clock-names = "extal", "extalr"; 441 #clock-cells = <2>; 442 #power-domain-cells = <0>; 443 #reset-cells = <1>; 444 }; 445 446 rst: reset-controller@e6160000 { 447 compatible = "renesas,r8a779f0-rst"; 448 reg = <0 0xe6160000 0 0x4000>; 449 }; 450 451 sysc: system-controller@e6180000 { 452 compatible = "renesas,r8a779f0-sysc"; 453 reg = <0 0xe6180000 0 0x4000>; 454 #power-domain-cells = <1>; 455 }; 456 457 tsc: thermal@e6198000 { 458 compatible = "renesas,r8a779f0-thermal"; 459 /* The 4th sensor is in control domain and not for Linux */ 460 reg = <0 0xe6198000 0 0x200>, 461 <0 0xe61a0000 0 0x200>, 462 <0 0xe61a8000 0 0x200>; 463 clocks = <&cpg CPG_MOD 919>; 464 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 465 resets = <&cpg 919>; 466 #thermal-sensor-cells = <1>; 467 }; 468 469 intc_ex: interrupt-controller@e61c0000 { 470 compatible = "renesas,intc-ex-r8a779f0", "renesas,irqc"; 471 #interrupt-cells = <2>; 472 interrupt-controller; 473 reg = <0 0xe61c0000 0 0x200>; 474 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&cpg CPG_CORE R8A779F0_CLK_CL16M>; 481 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 482 }; 483 484 tmu0: timer@e61e0000 { 485 compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; 486 reg = <0 0xe61e0000 0 0x30>; 487 interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>; 490 clocks = <&cpg CPG_MOD 713>; 491 clock-names = "fck"; 492 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 493 resets = <&cpg 713>; 494 status = "disabled"; 495 }; 496 497 tmu1: timer@e6fc0000 { 498 compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; 499 reg = <0 0xe6fc0000 0 0x30>; 500 interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>; 503 clocks = <&cpg CPG_MOD 714>; 504 clock-names = "fck"; 505 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 506 resets = <&cpg 714>; 507 status = "disabled"; 508 }; 509 510 tmu2: timer@e6fd0000 { 511 compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; 512 reg = <0 0xe6fd0000 0 0x30>; 513 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 483 IRQ_TYPE_LEVEL_HIGH>; 516 clocks = <&cpg CPG_MOD 715>; 517 clock-names = "fck"; 518 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 519 resets = <&cpg 715>; 520 status = "disabled"; 521 }; 522 523 tmu3: timer@e6fe0000 { 524 compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; 525 reg = <0 0xe6fe0000 0 0x30>; 526 interrupts = <GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>; 529 clocks = <&cpg CPG_MOD 716>; 530 clock-names = "fck"; 531 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 532 resets = <&cpg 716>; 533 status = "disabled"; 534 }; 535 536 tmu4: timer@ffc00000 { 537 compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; 538 reg = <0 0xffc00000 0 0x30>; 539 interrupts = <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&cpg CPG_MOD 717>; 543 clock-names = "fck"; 544 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 545 resets = <&cpg 717>; 546 status = "disabled"; 547 }; 548 549 eth_serdes: phy@e6444000 { 550 compatible = "renesas,r8a779f0-ether-serdes"; 551 reg = <0 0xe6444000 0 0x2800>; 552 clocks = <&cpg CPG_MOD 1506>; 553 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 554 resets = <&cpg 1506>; 555 #phy-cells = <1>; 556 status = "disabled"; 557 }; 558 559 i2c0: i2c@e6500000 { 560 compatible = "renesas,i2c-r8a779f0", 561 "renesas,rcar-gen4-i2c"; 562 reg = <0 0xe6500000 0 0x40>; 563 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 564 clocks = <&cpg CPG_MOD 518>; 565 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 566 resets = <&cpg 518>; 567 dmas = <&dmac0 0x91>, <&dmac0 0x90>, 568 <&dmac1 0x91>, <&dmac1 0x90>; 569 dma-names = "tx", "rx", "tx", "rx"; 570 i2c-scl-internal-delay-ns = <110>; 571 #address-cells = <1>; 572 #size-cells = <0>; 573 status = "disabled"; 574 }; 575 576 i2c1: i2c@e6508000 { 577 compatible = "renesas,i2c-r8a779f0", 578 "renesas,rcar-gen4-i2c"; 579 reg = <0 0xe6508000 0 0x40>; 580 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&cpg CPG_MOD 519>; 582 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 583 resets = <&cpg 519>; 584 dmas = <&dmac0 0x93>, <&dmac0 0x92>, 585 <&dmac1 0x93>, <&dmac1 0x92>; 586 dma-names = "tx", "rx", "tx", "rx"; 587 i2c-scl-internal-delay-ns = <110>; 588 #address-cells = <1>; 589 #size-cells = <0>; 590 status = "disabled"; 591 }; 592 593 i2c2: i2c@e6510000 { 594 compatible = "renesas,i2c-r8a779f0", 595 "renesas,rcar-gen4-i2c"; 596 reg = <0 0xe6510000 0 0x40>; 597 interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>; 598 clocks = <&cpg CPG_MOD 520>; 599 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 600 resets = <&cpg 520>; 601 dmas = <&dmac0 0x95>, <&dmac0 0x94>, 602 <&dmac1 0x95>, <&dmac1 0x94>; 603 dma-names = "tx", "rx", "tx", "rx"; 604 i2c-scl-internal-delay-ns = <110>; 605 #address-cells = <1>; 606 #size-cells = <0>; 607 status = "disabled"; 608 }; 609 610 i2c3: i2c@e66d0000 { 611 compatible = "renesas,i2c-r8a779f0", 612 "renesas,rcar-gen4-i2c"; 613 reg = <0 0xe66d0000 0 0x40>; 614 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 615 clocks = <&cpg CPG_MOD 521>; 616 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 617 resets = <&cpg 521>; 618 dmas = <&dmac0 0x97>, <&dmac0 0x96>, 619 <&dmac1 0x97>, <&dmac1 0x96>; 620 dma-names = "tx", "rx", "tx", "rx"; 621 i2c-scl-internal-delay-ns = <110>; 622 #address-cells = <1>; 623 #size-cells = <0>; 624 status = "disabled"; 625 }; 626 627 i2c4: i2c@e66d8000 { 628 compatible = "renesas,i2c-r8a779f0", 629 "renesas,rcar-gen4-i2c"; 630 reg = <0 0xe66d8000 0 0x40>; 631 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&cpg CPG_MOD 522>; 633 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 634 resets = <&cpg 522>; 635 dmas = <&dmac0 0x99>, <&dmac0 0x98>, 636 <&dmac1 0x99>, <&dmac1 0x98>; 637 dma-names = "tx", "rx", "tx", "rx"; 638 i2c-scl-internal-delay-ns = <110>; 639 #address-cells = <1>; 640 #size-cells = <0>; 641 status = "disabled"; 642 }; 643 644 i2c5: i2c@e66e0000 { 645 compatible = "renesas,i2c-r8a779f0", 646 "renesas,rcar-gen4-i2c"; 647 reg = <0 0xe66e0000 0 0x40>; 648 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 649 clocks = <&cpg CPG_MOD 523>; 650 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 651 resets = <&cpg 523>; 652 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>, 653 <&dmac1 0x9b>, <&dmac1 0x9a>; 654 dma-names = "tx", "rx", "tx", "rx"; 655 i2c-scl-internal-delay-ns = <110>; 656 #address-cells = <1>; 657 #size-cells = <0>; 658 status = "disabled"; 659 }; 660 661 hscif0: serial@e6540000 { 662 compatible = "renesas,hscif-r8a779f0", 663 "renesas,rcar-gen4-hscif", "renesas,hscif"; 664 reg = <0 0xe6540000 0 0x60>; 665 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 666 clocks = <&cpg CPG_MOD 514>, 667 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 668 <&scif_clk>; 669 clock-names = "fck", "brg_int", "scif_clk"; 670 dmas = <&dmac0 0x31>, <&dmac0 0x30>, 671 <&dmac1 0x31>, <&dmac1 0x30>; 672 dma-names = "tx", "rx", "tx", "rx"; 673 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 674 resets = <&cpg 514>; 675 status = "disabled"; 676 }; 677 678 hscif1: serial@e6550000 { 679 compatible = "renesas,hscif-r8a779f0", 680 "renesas,rcar-gen4-hscif", "renesas,hscif"; 681 reg = <0 0xe6550000 0 0x60>; 682 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 683 clocks = <&cpg CPG_MOD 515>, 684 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 685 <&scif_clk>; 686 clock-names = "fck", "brg_int", "scif_clk"; 687 dmas = <&dmac0 0x33>, <&dmac0 0x32>, 688 <&dmac1 0x33>, <&dmac1 0x32>; 689 dma-names = "tx", "rx", "tx", "rx"; 690 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 691 resets = <&cpg 515>; 692 status = "disabled"; 693 }; 694 695 hscif2: serial@e6560000 { 696 compatible = "renesas,hscif-r8a779f0", 697 "renesas,rcar-gen4-hscif", "renesas,hscif"; 698 reg = <0 0xe6560000 0 0x60>; 699 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 700 clocks = <&cpg CPG_MOD 516>, 701 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 702 <&scif_clk>; 703 clock-names = "fck", "brg_int", "scif_clk"; 704 dmas = <&dmac0 0x35>, <&dmac0 0x34>, 705 <&dmac1 0x35>, <&dmac1 0x34>; 706 dma-names = "tx", "rx", "tx", "rx"; 707 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 708 resets = <&cpg 516>; 709 status = "disabled"; 710 }; 711 712 hscif3: serial@e66a0000 { 713 compatible = "renesas,hscif-r8a779f0", 714 "renesas,rcar-gen4-hscif", "renesas,hscif"; 715 reg = <0 0xe66a0000 0 0x60>; 716 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 717 clocks = <&cpg CPG_MOD 517>, 718 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 719 <&scif_clk>; 720 clock-names = "fck", "brg_int", "scif_clk"; 721 dmas = <&dmac0 0x37>, <&dmac0 0x36>, 722 <&dmac1 0x37>, <&dmac1 0x36>; 723 dma-names = "tx", "rx", "tx", "rx"; 724 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 725 resets = <&cpg 517>; 726 status = "disabled"; 727 }; 728 729 ufs: ufs@e6860000 { 730 compatible = "renesas,r8a779f0-ufs"; 731 reg = <0 0xe6860000 0 0x100>; 732 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 733 clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>; 734 clock-names = "fck", "ref_clk"; 735 freq-table-hz = <200000000 200000000>, <38400000 38400000>; 736 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 737 resets = <&cpg 1514>; 738 status = "disabled"; 739 }; 740 741 rswitch: ethernet@e6880000 { 742 compatible = "renesas,r8a779f0-ether-switch"; 743 reg = <0 0xe6880000 0 0x20000>, <0 0xe68c0000 0 0x20000>; 744 reg-names = "base", "secure_base"; 745 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 758 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 763 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 766 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 792 interrupt-names = "mfwd_error", "race_error", 793 "coma_error", "gwca0_error", 794 "gwca1_error", "etha0_error", 795 "etha1_error", "etha2_error", 796 "gptp0_status", "gptp1_status", 797 "mfwd_status", "race_status", 798 "coma_status", "gwca0_status", 799 "gwca1_status", "etha0_status", 800 "etha1_status", "etha2_status", 801 "rmac0_status", "rmac1_status", 802 "rmac2_status", 803 "gwca0_rxtx0", "gwca0_rxtx1", 804 "gwca0_rxtx2", "gwca0_rxtx3", 805 "gwca0_rxtx4", "gwca0_rxtx5", 806 "gwca0_rxtx6", "gwca0_rxtx7", 807 "gwca1_rxtx0", "gwca1_rxtx1", 808 "gwca1_rxtx2", "gwca1_rxtx3", 809 "gwca1_rxtx4", "gwca1_rxtx5", 810 "gwca1_rxtx6", "gwca1_rxtx7", 811 "gwca0_rxts0", "gwca0_rxts1", 812 "gwca1_rxts0", "gwca1_rxts1", 813 "rmac0_mdio", "rmac1_mdio", 814 "rmac2_mdio", 815 "rmac0_phy", "rmac1_phy", 816 "rmac2_phy"; 817 clocks = <&cpg CPG_MOD 1505>; 818 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 819 resets = <&cpg 1505>; 820 status = "disabled"; 821 822 ethernet-ports { 823 #address-cells = <1>; 824 #size-cells = <0>; 825 826 port@0 { 827 reg = <0>; 828 phys = <ð_serdes 0>; 829 }; 830 port@1 { 831 reg = <1>; 832 phys = <ð_serdes 1>; 833 }; 834 port@2 { 835 reg = <2>; 836 phys = <ð_serdes 2>; 837 }; 838 }; 839 }; 840 841 scif0: serial@e6e60000 { 842 compatible = "renesas,scif-r8a779f0", 843 "renesas,rcar-gen4-scif", "renesas,scif"; 844 reg = <0 0xe6e60000 0 64>; 845 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 846 clocks = <&cpg CPG_MOD 702>, 847 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 848 <&scif_clk>; 849 clock-names = "fck", "brg_int", "scif_clk"; 850 dmas = <&dmac0 0x51>, <&dmac0 0x50>, 851 <&dmac1 0x51>, <&dmac1 0x50>; 852 dma-names = "tx", "rx", "tx", "rx"; 853 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 854 resets = <&cpg 702>; 855 status = "disabled"; 856 }; 857 858 scif1: serial@e6e68000 { 859 compatible = "renesas,scif-r8a779f0", 860 "renesas,rcar-gen4-scif", "renesas,scif"; 861 reg = <0 0xe6e68000 0 64>; 862 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>; 863 clocks = <&cpg CPG_MOD 703>, 864 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 865 <&scif_clk>; 866 clock-names = "fck", "brg_int", "scif_clk"; 867 dmas = <&dmac0 0x53>, <&dmac0 0x52>, 868 <&dmac1 0x53>, <&dmac1 0x52>; 869 dma-names = "tx", "rx", "tx", "rx"; 870 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 871 resets = <&cpg 703>; 872 status = "disabled"; 873 }; 874 875 scif3: serial@e6c50000 { 876 compatible = "renesas,scif-r8a779f0", 877 "renesas,rcar-gen4-scif", "renesas,scif"; 878 reg = <0 0xe6c50000 0 64>; 879 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 880 clocks = <&cpg CPG_MOD 704>, 881 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 882 <&scif_clk>; 883 clock-names = "fck", "brg_int", "scif_clk"; 884 dmas = <&dmac0 0x57>, <&dmac0 0x56>, 885 <&dmac1 0x57>, <&dmac1 0x56>; 886 dma-names = "tx", "rx", "tx", "rx"; 887 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 888 resets = <&cpg 704>; 889 status = "disabled"; 890 }; 891 892 scif4: serial@e6c40000 { 893 compatible = "renesas,scif-r8a779f0", 894 "renesas,rcar-gen4-scif", "renesas,scif"; 895 reg = <0 0xe6c40000 0 64>; 896 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 897 clocks = <&cpg CPG_MOD 705>, 898 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 899 <&scif_clk>; 900 clock-names = "fck", "brg_int", "scif_clk"; 901 dmas = <&dmac0 0x59>, <&dmac0 0x58>, 902 <&dmac1 0x59>, <&dmac1 0x58>; 903 dma-names = "tx", "rx", "tx", "rx"; 904 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 905 resets = <&cpg 705>; 906 status = "disabled"; 907 }; 908 909 msiof0: spi@e6e90000 { 910 compatible = "renesas,msiof-r8a779f0", 911 "renesas,rcar-gen4-msiof"; 912 reg = <0 0xe6e90000 0 0x0064>; 913 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 914 clocks = <&cpg CPG_MOD 618>; 915 dmas = <&dmac0 0x41>, <&dmac0 0x40>, 916 <&dmac1 0x41>, <&dmac1 0x40>; 917 dma-names = "tx", "rx", "tx", "rx"; 918 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 919 resets = <&cpg 618>; 920 #address-cells = <1>; 921 #size-cells = <0>; 922 status = "disabled"; 923 }; 924 925 msiof1: spi@e6ea0000 { 926 compatible = "renesas,msiof-r8a779f0", 927 "renesas,rcar-gen4-msiof"; 928 reg = <0 0xe6ea0000 0 0x0064>; 929 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 930 clocks = <&cpg CPG_MOD 619>; 931 dmas = <&dmac0 0x43>, <&dmac0 0x42>, 932 <&dmac1 0x43>, <&dmac1 0x42>; 933 dma-names = "tx", "rx", "tx", "rx"; 934 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 935 resets = <&cpg 619>; 936 #address-cells = <1>; 937 #size-cells = <0>; 938 status = "disabled"; 939 }; 940 941 msiof2: spi@e6c00000 { 942 compatible = "renesas,msiof-r8a779f0", 943 "renesas,rcar-gen4-msiof"; 944 reg = <0 0xe6c00000 0 0x0064>; 945 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 946 clocks = <&cpg CPG_MOD 620>; 947 dmas = <&dmac0 0x45>, <&dmac0 0x44>, 948 <&dmac1 0x45>, <&dmac1 0x44>; 949 dma-names = "tx", "rx", "tx", "rx"; 950 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 951 resets = <&cpg 620>; 952 #address-cells = <1>; 953 #size-cells = <0>; 954 status = "disabled"; 955 }; 956 957 msiof3: spi@e6c10000 { 958 compatible = "renesas,msiof-r8a779f0", 959 "renesas,rcar-gen4-msiof"; 960 reg = <0 0xe6c10000 0 0x0064>; 961 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 962 clocks = <&cpg CPG_MOD 621>; 963 dmas = <&dmac0 0x47>, <&dmac0 0x46>, 964 <&dmac1 0x47>, <&dmac1 0x46>; 965 dma-names = "tx", "rx", "tx", "rx"; 966 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 967 resets = <&cpg 621>; 968 #address-cells = <1>; 969 #size-cells = <0>; 970 status = "disabled"; 971 }; 972 973 dmac0: dma-controller@e7350000 { 974 compatible = "renesas,dmac-r8a779f0", 975 "renesas,rcar-gen4-dmac"; 976 reg = <0 0xe7350000 0 0x1000>, 977 <0 0xe7300000 0 0x10000>; 978 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 979 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 980 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 981 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 982 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 983 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 984 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 985 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 995 interrupt-names = "error", 996 "ch0", "ch1", "ch2", "ch3", "ch4", 997 "ch5", "ch6", "ch7", "ch8", "ch9", 998 "ch10", "ch11", "ch12", "ch13", 999 "ch14", "ch15"; 1000 clocks = <&cpg CPG_MOD 709>; 1001 clock-names = "fck"; 1002 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1003 resets = <&cpg 709>; 1004 #dma-cells = <1>; 1005 dma-channels = <16>; 1006 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 1007 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 1008 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 1009 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 1010 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 1011 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 1012 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 1013 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 1014 }; 1015 1016 dmac1: dma-controller@e7351000 { 1017 compatible = "renesas,dmac-r8a779f0", 1018 "renesas,rcar-gen4-dmac"; 1019 reg = <0 0xe7351000 0 0x1000>, 1020 <0 0xe7310000 0 0x10000>; 1021 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1022 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1023 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1024 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1025 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1026 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1027 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1028 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1029 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1030 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1031 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1032 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1033 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1034 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1035 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 1036 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 1037 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1038 interrupt-names = "error", 1039 "ch0", "ch1", "ch2", "ch3", "ch4", 1040 "ch5", "ch6", "ch7", "ch8", "ch9", 1041 "ch10", "ch11", "ch12", "ch13", 1042 "ch14", "ch15"; 1043 clocks = <&cpg CPG_MOD 710>; 1044 clock-names = "fck"; 1045 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1046 resets = <&cpg 710>; 1047 #dma-cells = <1>; 1048 dma-channels = <16>; 1049 iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>, 1050 <&ipmmu_ds0 18>, <&ipmmu_ds0 19>, 1051 <&ipmmu_ds0 20>, <&ipmmu_ds0 21>, 1052 <&ipmmu_ds0 22>, <&ipmmu_ds0 23>, 1053 <&ipmmu_ds0 24>, <&ipmmu_ds0 25>, 1054 <&ipmmu_ds0 26>, <&ipmmu_ds0 27>, 1055 <&ipmmu_ds0 28>, <&ipmmu_ds0 29>, 1056 <&ipmmu_ds0 30>, <&ipmmu_ds0 31>; 1057 }; 1058 1059 mmc0: mmc@ee140000 { 1060 compatible = "renesas,sdhi-r8a779f0", 1061 "renesas,rcar-gen4-sdhi"; 1062 reg = <0 0xee140000 0 0x2000>; 1063 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 1064 clocks = <&cpg CPG_MOD 706>, <&cpg CPG_CORE R8A779F0_CLK_SD0H>; 1065 clock-names = "core", "clkh"; 1066 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1067 resets = <&cpg 706>; 1068 max-frequency = <200000000>; 1069 iommus = <&ipmmu_ds0 32>; 1070 status = "disabled"; 1071 }; 1072 1073 ipmmu_rt0: iommu@ee480000 { 1074 compatible = "renesas,ipmmu-r8a779f0", 1075 "renesas,rcar-gen4-ipmmu-vmsa"; 1076 reg = <0 0xee480000 0 0x20000>; 1077 renesas,ipmmu-main = <&ipmmu_mm>; 1078 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1079 #iommu-cells = <1>; 1080 }; 1081 1082 ipmmu_rt1: iommu@ee4c0000 { 1083 compatible = "renesas,ipmmu-r8a779f0", 1084 "renesas,rcar-gen4-ipmmu-vmsa"; 1085 reg = <0 0xee4c0000 0 0x20000>; 1086 renesas,ipmmu-main = <&ipmmu_mm>; 1087 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1088 #iommu-cells = <1>; 1089 }; 1090 1091 ipmmu_ds0: iommu@eed00000 { 1092 compatible = "renesas,ipmmu-r8a779f0", 1093 "renesas,rcar-gen4-ipmmu-vmsa"; 1094 reg = <0 0xeed00000 0 0x20000>; 1095 renesas,ipmmu-main = <&ipmmu_mm>; 1096 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1097 #iommu-cells = <1>; 1098 }; 1099 1100 ipmmu_hc: iommu@eed40000 { 1101 compatible = "renesas,ipmmu-r8a779f0", 1102 "renesas,rcar-gen4-ipmmu-vmsa"; 1103 reg = <0 0xeed40000 0 0x20000>; 1104 renesas,ipmmu-main = <&ipmmu_mm>; 1105 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1106 #iommu-cells = <1>; 1107 }; 1108 1109 ipmmu_mm: iommu@eefc0000 { 1110 compatible = "renesas,ipmmu-r8a779f0", 1111 "renesas,rcar-gen4-ipmmu-vmsa"; 1112 reg = <0 0xeefc0000 0 0x20000>; 1113 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1115 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1116 #iommu-cells = <1>; 1117 }; 1118 1119 gic: interrupt-controller@f1000000 { 1120 compatible = "arm,gic-v3"; 1121 #interrupt-cells = <3>; 1122 #address-cells = <0>; 1123 interrupt-controller; 1124 reg = <0x0 0xf1000000 0 0x20000>, 1125 <0x0 0xf1060000 0 0x110000>; 1126 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1127 }; 1128 1129 prr: chipid@fff00044 { 1130 compatible = "renesas,prr"; 1131 reg = <0 0xfff00044 0 4>; 1132 }; 1133 }; 1134 1135 thermal-zones { 1136 sensor_thermal_rtcore: sensor1-thermal { 1137 polling-delay-passive = <250>; 1138 polling-delay = <1000>; 1139 thermal-sensors = <&tsc 0>; 1140 1141 trips { 1142 sensor1_crit: sensor1-crit { 1143 temperature = <120000>; 1144 hysteresis = <1000>; 1145 type = "critical"; 1146 }; 1147 }; 1148 }; 1149 1150 sensor_thermal_apcore0: sensor2-thermal { 1151 polling-delay-passive = <250>; 1152 polling-delay = <1000>; 1153 thermal-sensors = <&tsc 1>; 1154 1155 trips { 1156 sensor2_crit: sensor2-crit { 1157 temperature = <120000>; 1158 hysteresis = <1000>; 1159 type = "critical"; 1160 }; 1161 }; 1162 }; 1163 1164 sensor_thermal_apcore4: sensor3-thermal { 1165 polling-delay-passive = <250>; 1166 polling-delay = <1000>; 1167 thermal-sensors = <&tsc 2>; 1168 1169 trips { 1170 sensor3_crit: sensor3-crit { 1171 temperature = <120000>; 1172 hysteresis = <1000>; 1173 type = "critical"; 1174 }; 1175 }; 1176 }; 1177 }; 1178 1179 timer { 1180 compatible = "arm,armv8-timer"; 1181 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 1182 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 1183 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 1184 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 1185 }; 1186 1187 ufs30_clk: ufs30-clk { 1188 compatible = "fixed-clock"; 1189 #clock-cells = <0>; 1190 /* This value must be overridden by the board */ 1191 clock-frequency = <0>; 1192 }; 1193}; 1194