1// SPDX-License-Identifier: (GPL-2.0 or MIT) 2/* 3 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a779f0-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a779f0-sysc.h> 11 12/ { 13 compatible = "renesas,r8a779f0"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 a55_0: cpu@0 { 22 compatible = "arm,cortex-a55"; 23 reg = <0>; 24 device_type = "cpu"; 25 power-domains = <&sysc R8A779F0_PD_A1E0D0C0>; 26 }; 27 }; 28 29 extal_clk: extal { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 /* This value must be overridden by the board */ 33 clock-frequency = <0>; 34 }; 35 36 extalr_clk: extalr { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 /* This value must be overridden by the board */ 40 clock-frequency = <0>; 41 }; 42 43 pmu_a55 { 44 compatible = "arm,cortex-a55-pmu"; 45 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 46 }; 47 48 /* External SCIF clock - to be overridden by boards that provide it */ 49 scif_clk: scif { 50 compatible = "fixed-clock"; 51 #clock-cells = <0>; 52 clock-frequency = <0>; 53 }; 54 55 soc: soc { 56 compatible = "simple-bus"; 57 interrupt-parent = <&gic>; 58 #address-cells = <2>; 59 #size-cells = <2>; 60 ranges; 61 62 rwdt: watchdog@e6020000 { 63 compatible = "renesas,r8a779f0-wdt", 64 "renesas,rcar-gen4-wdt"; 65 reg = <0 0xe6020000 0 0x0c>; 66 clocks = <&cpg CPG_MOD 907>; 67 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 68 resets = <&cpg 907>; 69 status = "disabled"; 70 }; 71 72 cpg: clock-controller@e6150000 { 73 compatible = "renesas,r8a779f0-cpg-mssr"; 74 reg = <0 0xe6150000 0 0x4000>; 75 clocks = <&extal_clk>, <&extalr_clk>; 76 clock-names = "extal", "extalr"; 77 #clock-cells = <2>; 78 #power-domain-cells = <0>; 79 #reset-cells = <1>; 80 }; 81 82 rst: reset-controller@e6160000 { 83 compatible = "renesas,r8a779f0-rst"; 84 reg = <0 0xe6160000 0 0x4000>; 85 }; 86 87 sysc: system-controller@e6180000 { 88 compatible = "renesas,r8a779f0-sysc"; 89 reg = <0 0xe6180000 0 0x4000>; 90 #power-domain-cells = <1>; 91 }; 92 93 scif3: serial@e6c50000 { 94 compatible = "renesas,scif-r8a779f0", 95 "renesas,rcar-gen4-scif", "renesas,scif"; 96 reg = <0 0xe6c50000 0 64>; 97 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 98 clocks = <&cpg CPG_MOD 704>, 99 <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>, 100 <&scif_clk>; 101 clock-names = "fck", "brg_int", "scif_clk"; 102 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 103 resets = <&cpg 704>; 104 status = "disabled"; 105 }; 106 107 dmac0: dma-controller@e7350000 { 108 compatible = "renesas,dmac-r8a779f0", 109 "renesas,rcar-gen4-dmac"; 110 reg = <0 0xe7350000 0 0x1000>, 111 <0 0xe7300000 0 0x10000>; 112 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 127 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 129 interrupt-names = "error", 130 "ch0", "ch1", "ch2", "ch3", "ch4", 131 "ch5", "ch6", "ch7", "ch8", "ch9", 132 "ch10", "ch11", "ch12", "ch13", 133 "ch14", "ch15"; 134 clocks = <&cpg CPG_MOD 709>; 135 clock-names = "fck"; 136 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 137 resets = <&cpg 709>; 138 #dma-cells = <1>; 139 dma-channels = <16>; 140 }; 141 142 dmac1: dma-controller@e7351000 { 143 compatible = "renesas,dmac-r8a779f0", 144 "renesas,rcar-gen4-dmac"; 145 reg = <0 0xe7351000 0 0x1000>, 146 <0 0xe7310000 0 0x10000>; 147 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 164 interrupt-names = "error", 165 "ch0", "ch1", "ch2", "ch3", "ch4", 166 "ch5", "ch6", "ch7", "ch8", "ch9", 167 "ch10", "ch11", "ch12", "ch13", 168 "ch14", "ch15"; 169 clocks = <&cpg CPG_MOD 710>; 170 clock-names = "fck"; 171 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 172 resets = <&cpg 710>; 173 #dma-cells = <1>; 174 dma-channels = <16>; 175 }; 176 177 gic: interrupt-controller@f1000000 { 178 compatible = "arm,gic-v3"; 179 #interrupt-cells = <3>; 180 #address-cells = <0>; 181 interrupt-controller; 182 reg = <0x0 0xf1000000 0 0x20000>, 183 <0x0 0xf1060000 0 0x110000>; 184 interrupts = <GIC_PPI 9 185 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 186 }; 187 188 prr: chipid@fff00044 { 189 compatible = "renesas,prr"; 190 reg = <0 0xfff00044 0 4>; 191 }; 192 }; 193 194 timer { 195 compatible = "arm,armv8-timer"; 196 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 197 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 198 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 199 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 200 }; 201}; 202