1599fdfddSGeert Uytterhoeven// SPDX-License-Identifier: GPL-2.0 2599fdfddSGeert Uytterhoeven/* 3599fdfddSGeert Uytterhoeven * Device Tree Source for the Spider Ethernet sub-board 4599fdfddSGeert Uytterhoeven * 5599fdfddSGeert Uytterhoeven * Copyright (C) 2021 Renesas Electronics Corp. 6599fdfddSGeert Uytterhoeven */ 7599fdfddSGeert Uytterhoeven 8*884af88bSYoshihiro Shimodað_serdes { 9*884af88bSYoshihiro Shimoda status = "okay"; 10*884af88bSYoshihiro Shimoda}; 11*884af88bSYoshihiro Shimoda 12599fdfddSGeert Uytterhoeven&i2c4 { 13599fdfddSGeert Uytterhoeven eeprom@52 { 14599fdfddSGeert Uytterhoeven compatible = "rohm,br24g01", "atmel,24c01"; 15599fdfddSGeert Uytterhoeven label = "ethernet-sub-board"; 16599fdfddSGeert Uytterhoeven reg = <0x52>; 17599fdfddSGeert Uytterhoeven pagesize = <8>; 18599fdfddSGeert Uytterhoeven }; 19599fdfddSGeert Uytterhoeven}; 20*884af88bSYoshihiro Shimoda 21*884af88bSYoshihiro Shimoda&pfc { 22*884af88bSYoshihiro Shimoda tsn0_pins: tsn0 { 23*884af88bSYoshihiro Shimoda groups = "tsn0_mdio_b", "tsn0_link_b"; 24*884af88bSYoshihiro Shimoda function = "tsn0"; 25*884af88bSYoshihiro Shimoda power-source = <1800>; 26*884af88bSYoshihiro Shimoda }; 27*884af88bSYoshihiro Shimoda 28*884af88bSYoshihiro Shimoda tsn1_pins: tsn1 { 29*884af88bSYoshihiro Shimoda groups = "tsn1_mdio_b", "tsn1_link_b"; 30*884af88bSYoshihiro Shimoda function = "tsn1"; 31*884af88bSYoshihiro Shimoda power-source = <1800>; 32*884af88bSYoshihiro Shimoda }; 33*884af88bSYoshihiro Shimoda 34*884af88bSYoshihiro Shimoda tsn2_pins: tsn2 { 35*884af88bSYoshihiro Shimoda groups = "tsn2_mdio_b", "tsn2_link_b"; 36*884af88bSYoshihiro Shimoda function = "tsn2"; 37*884af88bSYoshihiro Shimoda power-source = <1800>; 38*884af88bSYoshihiro Shimoda }; 39*884af88bSYoshihiro Shimoda}; 40*884af88bSYoshihiro Shimoda 41*884af88bSYoshihiro Shimoda&rswitch { 42*884af88bSYoshihiro Shimoda pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>, <&tsn2_pins>; 43*884af88bSYoshihiro Shimoda pinctrl-names = "default"; 44*884af88bSYoshihiro Shimoda status = "okay"; 45*884af88bSYoshihiro Shimoda 46*884af88bSYoshihiro Shimoda ethernet-ports { 47*884af88bSYoshihiro Shimoda #address-cells = <1>; 48*884af88bSYoshihiro Shimoda #size-cells = <0>; 49*884af88bSYoshihiro Shimoda 50*884af88bSYoshihiro Shimoda port@0 { 51*884af88bSYoshihiro Shimoda reg = <0>; 52*884af88bSYoshihiro Shimoda phy-handle = <&u101>; 53*884af88bSYoshihiro Shimoda phy-mode = "sgmii"; 54*884af88bSYoshihiro Shimoda phys = <ð_serdes 0>; 55*884af88bSYoshihiro Shimoda 56*884af88bSYoshihiro Shimoda mdio { 57*884af88bSYoshihiro Shimoda #address-cells = <1>; 58*884af88bSYoshihiro Shimoda #size-cells = <0>; 59*884af88bSYoshihiro Shimoda 60*884af88bSYoshihiro Shimoda u101: ethernet-phy@1 { 61*884af88bSYoshihiro Shimoda reg = <1>; 62*884af88bSYoshihiro Shimoda compatible = "ethernet-phy-ieee802.3-c45"; 63*884af88bSYoshihiro Shimoda interrupt-parent = <&gpio3>; 64*884af88bSYoshihiro Shimoda interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 65*884af88bSYoshihiro Shimoda }; 66*884af88bSYoshihiro Shimoda }; 67*884af88bSYoshihiro Shimoda }; 68*884af88bSYoshihiro Shimoda port@1 { 69*884af88bSYoshihiro Shimoda reg = <1>; 70*884af88bSYoshihiro Shimoda phy-handle = <&u201>; 71*884af88bSYoshihiro Shimoda phy-mode = "sgmii"; 72*884af88bSYoshihiro Shimoda phys = <ð_serdes 1>; 73*884af88bSYoshihiro Shimoda 74*884af88bSYoshihiro Shimoda mdio { 75*884af88bSYoshihiro Shimoda #address-cells = <1>; 76*884af88bSYoshihiro Shimoda #size-cells = <0>; 77*884af88bSYoshihiro Shimoda 78*884af88bSYoshihiro Shimoda u201: ethernet-phy@2 { 79*884af88bSYoshihiro Shimoda reg = <2>; 80*884af88bSYoshihiro Shimoda compatible = "ethernet-phy-ieee802.3-c45"; 81*884af88bSYoshihiro Shimoda interrupt-parent = <&gpio3>; 82*884af88bSYoshihiro Shimoda interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 83*884af88bSYoshihiro Shimoda }; 84*884af88bSYoshihiro Shimoda }; 85*884af88bSYoshihiro Shimoda }; 86*884af88bSYoshihiro Shimoda port@2 { 87*884af88bSYoshihiro Shimoda reg = <2>; 88*884af88bSYoshihiro Shimoda phy-handle = <&u301>; 89*884af88bSYoshihiro Shimoda phy-mode = "sgmii"; 90*884af88bSYoshihiro Shimoda phys = <ð_serdes 2>; 91*884af88bSYoshihiro Shimoda 92*884af88bSYoshihiro Shimoda mdio { 93*884af88bSYoshihiro Shimoda #address-cells = <1>; 94*884af88bSYoshihiro Shimoda #size-cells = <0>; 95*884af88bSYoshihiro Shimoda 96*884af88bSYoshihiro Shimoda u301: ethernet-phy@3 { 97*884af88bSYoshihiro Shimoda reg = <3>; 98*884af88bSYoshihiro Shimoda compatible = "ethernet-phy-ieee802.3-c45"; 99*884af88bSYoshihiro Shimoda interrupt-parent = <&gpio3>; 100*884af88bSYoshihiro Shimoda interrupts = <9 IRQ_TYPE_LEVEL_LOW>; 101*884af88bSYoshihiro Shimoda }; 102*884af88bSYoshihiro Shimoda }; 103*884af88bSYoshihiro Shimoda }; 104*884af88bSYoshihiro Shimoda }; 105*884af88bSYoshihiro Shimoda}; 106