163070d7cSYoshihiro Shimoda// SPDX-License-Identifier: GPL-2.0 263070d7cSYoshihiro Shimoda/* 363070d7cSYoshihiro Shimoda * Device Tree Source for the Falcon CPU board 463070d7cSYoshihiro Shimoda * 563070d7cSYoshihiro Shimoda * Copyright (C) 2020 Renesas Electronics Corp. 663070d7cSYoshihiro Shimoda */ 763070d7cSYoshihiro Shimoda 863070d7cSYoshihiro Shimoda#include "r8a779a0.dtsi" 963070d7cSYoshihiro Shimoda 1063070d7cSYoshihiro Shimoda/ { 1163070d7cSYoshihiro Shimoda model = "Renesas Falcon CPU board"; 1263070d7cSYoshihiro Shimoda compatible = "renesas,falcon-cpu", "renesas,r8a779a0"; 1363070d7cSYoshihiro Shimoda 1463070d7cSYoshihiro Shimoda memory@48000000 { 1563070d7cSYoshihiro Shimoda device_type = "memory"; 1663070d7cSYoshihiro Shimoda /* first 128MB is reserved for secure area. */ 1763070d7cSYoshihiro Shimoda reg = <0x0 0x48000000 0x0 0x78000000>; 1863070d7cSYoshihiro Shimoda }; 1963070d7cSYoshihiro Shimoda 2063070d7cSYoshihiro Shimoda memory@500000000 { 2163070d7cSYoshihiro Shimoda device_type = "memory"; 2263070d7cSYoshihiro Shimoda reg = <0x5 0x00000000 0x0 0x80000000>; 2363070d7cSYoshihiro Shimoda }; 2463070d7cSYoshihiro Shimoda 2563070d7cSYoshihiro Shimoda memory@600000000 { 2663070d7cSYoshihiro Shimoda device_type = "memory"; 2763070d7cSYoshihiro Shimoda reg = <0x6 0x00000000 0x0 0x80000000>; 2863070d7cSYoshihiro Shimoda }; 2963070d7cSYoshihiro Shimoda 3063070d7cSYoshihiro Shimoda memory@700000000 { 3163070d7cSYoshihiro Shimoda device_type = "memory"; 3263070d7cSYoshihiro Shimoda reg = <0x7 0x00000000 0x0 0x80000000>; 3363070d7cSYoshihiro Shimoda }; 3463070d7cSYoshihiro Shimoda}; 3563070d7cSYoshihiro Shimoda 3663070d7cSYoshihiro Shimoda&extal_clk { 3763070d7cSYoshihiro Shimoda clock-frequency = <16666666>; 3863070d7cSYoshihiro Shimoda}; 3963070d7cSYoshihiro Shimoda 4063070d7cSYoshihiro Shimoda&extalr_clk { 4163070d7cSYoshihiro Shimoda clock-frequency = <32768>; 4263070d7cSYoshihiro Shimoda}; 4363070d7cSYoshihiro Shimoda 44*0e6fb83eSWolfram Sang&i2c0 { 45*0e6fb83eSWolfram Sang pinctrl-0 = <&i2c0_pins>; 46*0e6fb83eSWolfram Sang pinctrl-names = "default"; 47*0e6fb83eSWolfram Sang 48*0e6fb83eSWolfram Sang status = "okay"; 49*0e6fb83eSWolfram Sang clock-frequency = <400000>; 50*0e6fb83eSWolfram Sang}; 51*0e6fb83eSWolfram Sang 52*0e6fb83eSWolfram Sang&i2c1 { 53*0e6fb83eSWolfram Sang pinctrl-0 = <&i2c1_pins>; 54*0e6fb83eSWolfram Sang pinctrl-names = "default"; 55*0e6fb83eSWolfram Sang 56*0e6fb83eSWolfram Sang status = "okay"; 57*0e6fb83eSWolfram Sang clock-frequency = <400000>; 58*0e6fb83eSWolfram Sang}; 59*0e6fb83eSWolfram Sang 60*0e6fb83eSWolfram Sang&i2c6 { 61*0e6fb83eSWolfram Sang pinctrl-0 = <&i2c6_pins>; 62*0e6fb83eSWolfram Sang pinctrl-names = "default"; 63*0e6fb83eSWolfram Sang 64*0e6fb83eSWolfram Sang status = "okay"; 65*0e6fb83eSWolfram Sang clock-frequency = <400000>; 66*0e6fb83eSWolfram Sang}; 67*0e6fb83eSWolfram Sang 68*0e6fb83eSWolfram Sang&pfc { 69*0e6fb83eSWolfram Sang i2c0_pins: i2c0 { 70*0e6fb83eSWolfram Sang groups = "i2c0"; 71*0e6fb83eSWolfram Sang function = "i2c0"; 72*0e6fb83eSWolfram Sang }; 73*0e6fb83eSWolfram Sang 74*0e6fb83eSWolfram Sang i2c1_pins: i2c1 { 75*0e6fb83eSWolfram Sang groups = "i2c1"; 76*0e6fb83eSWolfram Sang function = "i2c1"; 77*0e6fb83eSWolfram Sang }; 78*0e6fb83eSWolfram Sang 79*0e6fb83eSWolfram Sang i2c6_pins: i2c6 { 80*0e6fb83eSWolfram Sang groups = "i2c6"; 81*0e6fb83eSWolfram Sang function = "i2c6"; 82*0e6fb83eSWolfram Sang }; 83*0e6fb83eSWolfram Sang}; 84*0e6fb83eSWolfram Sang 8563070d7cSYoshihiro Shimoda&scif0 { 8663070d7cSYoshihiro Shimoda status = "okay"; 8763070d7cSYoshihiro Shimoda}; 88