1f37a7767SYoshihiro Shimoda/* SPDX-License-Identifier: GPL-2.0 */ 2f37a7767SYoshihiro Shimoda/* 3e18a31a7SMagnus Damm * Device Tree Source for the R-Car E3 (R8A77990) SoC 4f37a7767SYoshihiro Shimoda * 5f37a7767SYoshihiro Shimoda * Copyright (C) 2018 Renesas Electronics Corp. 6f37a7767SYoshihiro Shimoda */ 7f37a7767SYoshihiro Shimoda 883e7d2ecSGeert Uytterhoeven#include <dt-bindings/clock/r8a77990-cpg-mssr.h> 9f37a7767SYoshihiro Shimoda#include <dt-bindings/interrupt-controller/arm-gic.h> 1055697cbbSMagnus Damm#include <dt-bindings/power/r8a77990-sysc.h> 11f37a7767SYoshihiro Shimoda 12f37a7767SYoshihiro Shimoda/ { 13f37a7767SYoshihiro Shimoda compatible = "renesas,r8a77990"; 14f37a7767SYoshihiro Shimoda #address-cells = <2>; 15f37a7767SYoshihiro Shimoda #size-cells = <2>; 16f37a7767SYoshihiro Shimoda 17*bc011dfaSTakeshi Kihara aliases { 18*bc011dfaSTakeshi Kihara i2c0 = &i2c0; 19*bc011dfaSTakeshi Kihara i2c1 = &i2c1; 20*bc011dfaSTakeshi Kihara i2c2 = &i2c2; 21*bc011dfaSTakeshi Kihara i2c3 = &i2c3; 22*bc011dfaSTakeshi Kihara i2c4 = &i2c4; 23*bc011dfaSTakeshi Kihara i2c5 = &i2c5; 24*bc011dfaSTakeshi Kihara i2c6 = &i2c6; 25*bc011dfaSTakeshi Kihara i2c7 = &i2c7; 26*bc011dfaSTakeshi Kihara }; 27*bc011dfaSTakeshi Kihara 28f37a7767SYoshihiro Shimoda cpus { 29f37a7767SYoshihiro Shimoda #address-cells = <1>; 30f37a7767SYoshihiro Shimoda #size-cells = <0>; 31f37a7767SYoshihiro Shimoda 32f37a7767SYoshihiro Shimoda a53_0: cpu@0 { 33f37a7767SYoshihiro Shimoda compatible = "arm,cortex-a53", "arm,armv8"; 347085f5d9SGeert Uytterhoeven reg = <0>; 35f37a7767SYoshihiro Shimoda device_type = "cpu"; 3683e7d2ecSGeert Uytterhoeven power-domains = <&sysc R8A77990_PD_CA53_CPU0>; 37f37a7767SYoshihiro Shimoda next-level-cache = <&L2_CA53>; 38f37a7767SYoshihiro Shimoda enable-method = "psci"; 39f37a7767SYoshihiro Shimoda }; 40f37a7767SYoshihiro Shimoda 417085f5d9SGeert Uytterhoeven a53_1: cpu@1 { 427085f5d9SGeert Uytterhoeven compatible = "arm,cortex-a53", "arm,armv8"; 437085f5d9SGeert Uytterhoeven reg = <1>; 447085f5d9SGeert Uytterhoeven device_type = "cpu"; 4583e7d2ecSGeert Uytterhoeven power-domains = <&sysc R8A77990_PD_CA53_CPU1>; 467085f5d9SGeert Uytterhoeven next-level-cache = <&L2_CA53>; 477085f5d9SGeert Uytterhoeven enable-method = "psci"; 487085f5d9SGeert Uytterhoeven }; 497085f5d9SGeert Uytterhoeven 50de1eb23cSYoshihiro Shimoda L2_CA53: cache-controller-0 { 51f37a7767SYoshihiro Shimoda compatible = "cache"; 5283e7d2ecSGeert Uytterhoeven power-domains = <&sysc R8A77990_PD_CA53_SCU>; 53f37a7767SYoshihiro Shimoda cache-unified; 54f37a7767SYoshihiro Shimoda cache-level = <2>; 55f37a7767SYoshihiro Shimoda }; 56f37a7767SYoshihiro Shimoda }; 57f37a7767SYoshihiro Shimoda 58f37a7767SYoshihiro Shimoda extal_clk: extal { 59f37a7767SYoshihiro Shimoda compatible = "fixed-clock"; 60f37a7767SYoshihiro Shimoda #clock-cells = <0>; 61f37a7767SYoshihiro Shimoda /* This value must be overridden by the board */ 62f37a7767SYoshihiro Shimoda clock-frequency = <0>; 63f37a7767SYoshihiro Shimoda }; 64f37a7767SYoshihiro Shimoda 65f37a7767SYoshihiro Shimoda pmu_a53 { 66f37a7767SYoshihiro Shimoda compatible = "arm,cortex-a53-pmu"; 677085f5d9SGeert Uytterhoeven interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 687085f5d9SGeert Uytterhoeven <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 697085f5d9SGeert Uytterhoeven interrupt-affinity = <&a53_0>, <&a53_1>; 70f37a7767SYoshihiro Shimoda }; 71f37a7767SYoshihiro Shimoda 72f37a7767SYoshihiro Shimoda psci { 73bc26b8f4SYoshihiro Shimoda compatible = "arm,psci-1.0", "arm,psci-0.2"; 74f37a7767SYoshihiro Shimoda method = "smc"; 75f37a7767SYoshihiro Shimoda }; 76f37a7767SYoshihiro Shimoda 77103db9b5STakeshi Kihara /* External SCIF clock - to be overridden by boards that provide it */ 78103db9b5STakeshi Kihara scif_clk: scif { 79103db9b5STakeshi Kihara compatible = "fixed-clock"; 80103db9b5STakeshi Kihara #clock-cells = <0>; 81103db9b5STakeshi Kihara clock-frequency = <0>; 82103db9b5STakeshi Kihara }; 83103db9b5STakeshi Kihara 84f37a7767SYoshihiro Shimoda soc: soc { 85f37a7767SYoshihiro Shimoda compatible = "simple-bus"; 86f37a7767SYoshihiro Shimoda interrupt-parent = <&gic>; 87f37a7767SYoshihiro Shimoda #address-cells = <2>; 88f37a7767SYoshihiro Shimoda #size-cells = <2>; 89f37a7767SYoshihiro Shimoda ranges; 90f37a7767SYoshihiro Shimoda 91eb614d94STakeshi Kihara rwdt: watchdog@e6020000 { 92eb614d94STakeshi Kihara compatible = "renesas,r8a77990-wdt", 93eb614d94STakeshi Kihara "renesas,rcar-gen3-wdt"; 94eb614d94STakeshi Kihara reg = <0 0xe6020000 0 0x0c>; 95eb614d94STakeshi Kihara clocks = <&cpg CPG_MOD 402>; 9683e7d2ecSGeert Uytterhoeven power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 97eb614d94STakeshi Kihara resets = <&cpg 402>; 98eb614d94STakeshi Kihara status = "disabled"; 99eb614d94STakeshi Kihara }; 100eb614d94STakeshi Kihara 1010d292de1SYoshihiro Shimoda gpio0: gpio@e6050000 { 1020d292de1SYoshihiro Shimoda compatible = "renesas,gpio-r8a77990", 1030d292de1SYoshihiro Shimoda "renesas,rcar-gen3-gpio"; 1040d292de1SYoshihiro Shimoda reg = <0 0xe6050000 0 0x50>; 1050d292de1SYoshihiro Shimoda interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1060d292de1SYoshihiro Shimoda #gpio-cells = <2>; 1070d292de1SYoshihiro Shimoda gpio-controller; 1080d292de1SYoshihiro Shimoda gpio-ranges = <&pfc 0 0 18>; 1090d292de1SYoshihiro Shimoda #interrupt-cells = <2>; 1100d292de1SYoshihiro Shimoda interrupt-controller; 1110d292de1SYoshihiro Shimoda clocks = <&cpg CPG_MOD 912>; 11283e7d2ecSGeert Uytterhoeven power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1130d292de1SYoshihiro Shimoda resets = <&cpg 912>; 1140d292de1SYoshihiro Shimoda }; 1150d292de1SYoshihiro Shimoda 1160d292de1SYoshihiro Shimoda gpio1: gpio@e6051000 { 1170d292de1SYoshihiro Shimoda compatible = "renesas,gpio-r8a77990", 1180d292de1SYoshihiro Shimoda "renesas,rcar-gen3-gpio"; 1190d292de1SYoshihiro Shimoda reg = <0 0xe6051000 0 0x50>; 1200d292de1SYoshihiro Shimoda interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1210d292de1SYoshihiro Shimoda #gpio-cells = <2>; 1220d292de1SYoshihiro Shimoda gpio-controller; 1230d292de1SYoshihiro Shimoda gpio-ranges = <&pfc 0 32 23>; 1240d292de1SYoshihiro Shimoda #interrupt-cells = <2>; 1250d292de1SYoshihiro Shimoda interrupt-controller; 1260d292de1SYoshihiro Shimoda clocks = <&cpg CPG_MOD 911>; 12783e7d2ecSGeert Uytterhoeven power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1280d292de1SYoshihiro Shimoda resets = <&cpg 911>; 1290d292de1SYoshihiro Shimoda }; 1300d292de1SYoshihiro Shimoda 1310d292de1SYoshihiro Shimoda gpio2: gpio@e6052000 { 1320d292de1SYoshihiro Shimoda compatible = "renesas,gpio-r8a77990", 1330d292de1SYoshihiro Shimoda "renesas,rcar-gen3-gpio"; 1340d292de1SYoshihiro Shimoda reg = <0 0xe6052000 0 0x50>; 1350d292de1SYoshihiro Shimoda interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1360d292de1SYoshihiro Shimoda #gpio-cells = <2>; 1370d292de1SYoshihiro Shimoda gpio-controller; 1380d292de1SYoshihiro Shimoda gpio-ranges = <&pfc 0 64 26>; 1390d292de1SYoshihiro Shimoda #interrupt-cells = <2>; 1400d292de1SYoshihiro Shimoda interrupt-controller; 1410d292de1SYoshihiro Shimoda clocks = <&cpg CPG_MOD 910>; 14283e7d2ecSGeert Uytterhoeven power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1430d292de1SYoshihiro Shimoda resets = <&cpg 910>; 1440d292de1SYoshihiro Shimoda }; 1450d292de1SYoshihiro Shimoda 1460d292de1SYoshihiro Shimoda gpio3: gpio@e6053000 { 1470d292de1SYoshihiro Shimoda compatible = "renesas,gpio-r8a77990", 1480d292de1SYoshihiro Shimoda "renesas,rcar-gen3-gpio"; 1490d292de1SYoshihiro Shimoda reg = <0 0xe6053000 0 0x50>; 1500d292de1SYoshihiro Shimoda interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1510d292de1SYoshihiro Shimoda #gpio-cells = <2>; 1520d292de1SYoshihiro Shimoda gpio-controller; 1530d292de1SYoshihiro Shimoda gpio-ranges = <&pfc 0 96 16>; 1540d292de1SYoshihiro Shimoda #interrupt-cells = <2>; 1550d292de1SYoshihiro Shimoda interrupt-controller; 1560d292de1SYoshihiro Shimoda clocks = <&cpg CPG_MOD 909>; 15783e7d2ecSGeert Uytterhoeven power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1580d292de1SYoshihiro Shimoda resets = <&cpg 909>; 1590d292de1SYoshihiro Shimoda }; 1600d292de1SYoshihiro Shimoda 1610d292de1SYoshihiro Shimoda gpio4: gpio@e6054000 { 1620d292de1SYoshihiro Shimoda compatible = "renesas,gpio-r8a77990", 1630d292de1SYoshihiro Shimoda "renesas,rcar-gen3-gpio"; 1640d292de1SYoshihiro Shimoda reg = <0 0xe6054000 0 0x50>; 1650d292de1SYoshihiro Shimoda interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1660d292de1SYoshihiro Shimoda #gpio-cells = <2>; 1670d292de1SYoshihiro Shimoda gpio-controller; 1680d292de1SYoshihiro Shimoda gpio-ranges = <&pfc 0 128 11>; 1690d292de1SYoshihiro Shimoda #interrupt-cells = <2>; 1700d292de1SYoshihiro Shimoda interrupt-controller; 1710d292de1SYoshihiro Shimoda clocks = <&cpg CPG_MOD 908>; 17283e7d2ecSGeert Uytterhoeven power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1730d292de1SYoshihiro Shimoda resets = <&cpg 908>; 1740d292de1SYoshihiro Shimoda }; 1750d292de1SYoshihiro Shimoda 1760d292de1SYoshihiro Shimoda gpio5: gpio@e6055000 { 1770d292de1SYoshihiro Shimoda compatible = "renesas,gpio-r8a77990", 1780d292de1SYoshihiro Shimoda "renesas,rcar-gen3-gpio"; 1790d292de1SYoshihiro Shimoda reg = <0 0xe6055000 0 0x50>; 1800d292de1SYoshihiro Shimoda interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1810d292de1SYoshihiro Shimoda #gpio-cells = <2>; 1820d292de1SYoshihiro Shimoda gpio-controller; 1830d292de1SYoshihiro Shimoda gpio-ranges = <&pfc 0 160 20>; 1840d292de1SYoshihiro Shimoda #interrupt-cells = <2>; 1850d292de1SYoshihiro Shimoda interrupt-controller; 1860d292de1SYoshihiro Shimoda clocks = <&cpg CPG_MOD 907>; 18783e7d2ecSGeert Uytterhoeven power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1880d292de1SYoshihiro Shimoda resets = <&cpg 907>; 1890d292de1SYoshihiro Shimoda }; 1900d292de1SYoshihiro Shimoda 1910d292de1SYoshihiro Shimoda gpio6: gpio@e6055400 { 1920d292de1SYoshihiro Shimoda compatible = "renesas,gpio-r8a77990", 1930d292de1SYoshihiro Shimoda "renesas,rcar-gen3-gpio"; 1940d292de1SYoshihiro Shimoda reg = <0 0xe6055400 0 0x50>; 1950d292de1SYoshihiro Shimoda interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1960d292de1SYoshihiro Shimoda #gpio-cells = <2>; 1970d292de1SYoshihiro Shimoda gpio-controller; 1980d292de1SYoshihiro Shimoda gpio-ranges = <&pfc 0 192 18>; 1990d292de1SYoshihiro Shimoda #interrupt-cells = <2>; 2000d292de1SYoshihiro Shimoda interrupt-controller; 2010d292de1SYoshihiro Shimoda clocks = <&cpg CPG_MOD 906>; 20283e7d2ecSGeert Uytterhoeven power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 2030d292de1SYoshihiro Shimoda resets = <&cpg 906>; 2040d292de1SYoshihiro Shimoda }; 2050d292de1SYoshihiro Shimoda 206*bc011dfaSTakeshi Kihara i2c0: i2c@e6500000 { 207*bc011dfaSTakeshi Kihara #address-cells = <1>; 208*bc011dfaSTakeshi Kihara #size-cells = <0>; 209*bc011dfaSTakeshi Kihara compatible = "renesas,i2c-r8a77990", 210*bc011dfaSTakeshi Kihara "renesas,rcar-gen3-i2c"; 211*bc011dfaSTakeshi Kihara reg = <0 0xe6500000 0 0x40>; 212*bc011dfaSTakeshi Kihara interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 213*bc011dfaSTakeshi Kihara clocks = <&cpg CPG_MOD 931>; 214*bc011dfaSTakeshi Kihara power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 215*bc011dfaSTakeshi Kihara resets = <&cpg 931>; 216*bc011dfaSTakeshi Kihara i2c-scl-internal-delay-ns = <110>; 217*bc011dfaSTakeshi Kihara status = "disabled"; 218*bc011dfaSTakeshi Kihara }; 219*bc011dfaSTakeshi Kihara 220*bc011dfaSTakeshi Kihara i2c1: i2c@e6508000 { 221*bc011dfaSTakeshi Kihara #address-cells = <1>; 222*bc011dfaSTakeshi Kihara #size-cells = <0>; 223*bc011dfaSTakeshi Kihara compatible = "renesas,i2c-r8a77990", 224*bc011dfaSTakeshi Kihara "renesas,rcar-gen3-i2c"; 225*bc011dfaSTakeshi Kihara reg = <0 0xe6508000 0 0x40>; 226*bc011dfaSTakeshi Kihara interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 227*bc011dfaSTakeshi Kihara clocks = <&cpg CPG_MOD 930>; 228*bc011dfaSTakeshi Kihara power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 229*bc011dfaSTakeshi Kihara resets = <&cpg 930>; 230*bc011dfaSTakeshi Kihara i2c-scl-internal-delay-ns = <6>; 231*bc011dfaSTakeshi Kihara status = "disabled"; 232*bc011dfaSTakeshi Kihara }; 233*bc011dfaSTakeshi Kihara 234*bc011dfaSTakeshi Kihara i2c2: i2c@e6510000 { 235*bc011dfaSTakeshi Kihara #address-cells = <1>; 236*bc011dfaSTakeshi Kihara #size-cells = <0>; 237*bc011dfaSTakeshi Kihara compatible = "renesas,i2c-r8a77990", 238*bc011dfaSTakeshi Kihara "renesas,rcar-gen3-i2c"; 239*bc011dfaSTakeshi Kihara reg = <0 0xe6510000 0 0x40>; 240*bc011dfaSTakeshi Kihara interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 241*bc011dfaSTakeshi Kihara clocks = <&cpg CPG_MOD 929>; 242*bc011dfaSTakeshi Kihara power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 243*bc011dfaSTakeshi Kihara resets = <&cpg 929>; 244*bc011dfaSTakeshi Kihara i2c-scl-internal-delay-ns = <6>; 245*bc011dfaSTakeshi Kihara status = "disabled"; 246*bc011dfaSTakeshi Kihara }; 247*bc011dfaSTakeshi Kihara 248*bc011dfaSTakeshi Kihara i2c3: i2c@e66d0000 { 249*bc011dfaSTakeshi Kihara #address-cells = <1>; 250*bc011dfaSTakeshi Kihara #size-cells = <0>; 251*bc011dfaSTakeshi Kihara compatible = "renesas,i2c-r8a77990", 252*bc011dfaSTakeshi Kihara "renesas,rcar-gen3-i2c"; 253*bc011dfaSTakeshi Kihara reg = <0 0xe66d0000 0 0x40>; 254*bc011dfaSTakeshi Kihara interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 255*bc011dfaSTakeshi Kihara clocks = <&cpg CPG_MOD 928>; 256*bc011dfaSTakeshi Kihara power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 257*bc011dfaSTakeshi Kihara resets = <&cpg 928>; 258*bc011dfaSTakeshi Kihara i2c-scl-internal-delay-ns = <110>; 259*bc011dfaSTakeshi Kihara status = "disabled"; 260*bc011dfaSTakeshi Kihara }; 261*bc011dfaSTakeshi Kihara 262*bc011dfaSTakeshi Kihara i2c4: i2c@e66d8000 { 263*bc011dfaSTakeshi Kihara #address-cells = <1>; 264*bc011dfaSTakeshi Kihara #size-cells = <0>; 265*bc011dfaSTakeshi Kihara compatible = "renesas,i2c-r8a77990", 266*bc011dfaSTakeshi Kihara "renesas,rcar-gen3-i2c"; 267*bc011dfaSTakeshi Kihara reg = <0 0xe66d8000 0 0x40>; 268*bc011dfaSTakeshi Kihara interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 269*bc011dfaSTakeshi Kihara clocks = <&cpg CPG_MOD 927>; 270*bc011dfaSTakeshi Kihara power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 271*bc011dfaSTakeshi Kihara resets = <&cpg 927>; 272*bc011dfaSTakeshi Kihara i2c-scl-internal-delay-ns = <6>; 273*bc011dfaSTakeshi Kihara status = "disabled"; 274*bc011dfaSTakeshi Kihara }; 275*bc011dfaSTakeshi Kihara 276*bc011dfaSTakeshi Kihara i2c5: i2c@e66e0000 { 277*bc011dfaSTakeshi Kihara #address-cells = <1>; 278*bc011dfaSTakeshi Kihara #size-cells = <0>; 279*bc011dfaSTakeshi Kihara compatible = "renesas,i2c-r8a77990", 280*bc011dfaSTakeshi Kihara "renesas,rcar-gen3-i2c"; 281*bc011dfaSTakeshi Kihara reg = <0 0xe66e0000 0 0x40>; 282*bc011dfaSTakeshi Kihara interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 283*bc011dfaSTakeshi Kihara clocks = <&cpg CPG_MOD 919>; 284*bc011dfaSTakeshi Kihara power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 285*bc011dfaSTakeshi Kihara resets = <&cpg 919>; 286*bc011dfaSTakeshi Kihara i2c-scl-internal-delay-ns = <6>; 287*bc011dfaSTakeshi Kihara status = "disabled"; 288*bc011dfaSTakeshi Kihara }; 289*bc011dfaSTakeshi Kihara 290*bc011dfaSTakeshi Kihara i2c6: i2c@e66e8000 { 291*bc011dfaSTakeshi Kihara #address-cells = <1>; 292*bc011dfaSTakeshi Kihara #size-cells = <0>; 293*bc011dfaSTakeshi Kihara compatible = "renesas,i2c-r8a77990", 294*bc011dfaSTakeshi Kihara "renesas,rcar-gen3-i2c"; 295*bc011dfaSTakeshi Kihara reg = <0 0xe66e8000 0 0x40>; 296*bc011dfaSTakeshi Kihara interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 297*bc011dfaSTakeshi Kihara clocks = <&cpg CPG_MOD 918>; 298*bc011dfaSTakeshi Kihara power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 299*bc011dfaSTakeshi Kihara resets = <&cpg 918>; 300*bc011dfaSTakeshi Kihara i2c-scl-internal-delay-ns = <6>; 301*bc011dfaSTakeshi Kihara status = "disabled"; 302*bc011dfaSTakeshi Kihara }; 303*bc011dfaSTakeshi Kihara 304*bc011dfaSTakeshi Kihara i2c7: i2c@e6690000 { 305*bc011dfaSTakeshi Kihara #address-cells = <1>; 306*bc011dfaSTakeshi Kihara #size-cells = <0>; 307*bc011dfaSTakeshi Kihara compatible = "renesas,i2c-r8a77990", 308*bc011dfaSTakeshi Kihara "renesas,rcar-gen3-i2c"; 309*bc011dfaSTakeshi Kihara reg = <0 0xe6690000 0 0x40>; 310*bc011dfaSTakeshi Kihara interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 311*bc011dfaSTakeshi Kihara clocks = <&cpg CPG_MOD 1003>; 312*bc011dfaSTakeshi Kihara power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 313*bc011dfaSTakeshi Kihara resets = <&cpg 1003>; 314*bc011dfaSTakeshi Kihara i2c-scl-internal-delay-ns = <6>; 315*bc011dfaSTakeshi Kihara status = "disabled"; 316*bc011dfaSTakeshi Kihara }; 317*bc011dfaSTakeshi Kihara 3184ab0df33SYoshihiro Shimoda pfc: pin-controller@e6060000 { 3194ab0df33SYoshihiro Shimoda compatible = "renesas,pfc-r8a77990"; 3204ab0df33SYoshihiro Shimoda reg = <0 0xe6060000 0 0x508>; 3214ab0df33SYoshihiro Shimoda }; 3224ab0df33SYoshihiro Shimoda 323f37a7767SYoshihiro Shimoda cpg: clock-controller@e6150000 { 324f37a7767SYoshihiro Shimoda compatible = "renesas,r8a77990-cpg-mssr"; 325f37a7767SYoshihiro Shimoda reg = <0 0xe6150000 0 0x1000>; 326f37a7767SYoshihiro Shimoda clocks = <&extal_clk>; 327f37a7767SYoshihiro Shimoda clock-names = "extal"; 328f37a7767SYoshihiro Shimoda #clock-cells = <2>; 329f37a7767SYoshihiro Shimoda #power-domain-cells = <0>; 330f37a7767SYoshihiro Shimoda #reset-cells = <1>; 331f37a7767SYoshihiro Shimoda }; 332f37a7767SYoshihiro Shimoda 333f37a7767SYoshihiro Shimoda rst: reset-controller@e6160000 { 334f37a7767SYoshihiro Shimoda compatible = "renesas,r8a77990-rst"; 335f37a7767SYoshihiro Shimoda reg = <0 0xe6160000 0 0x0200>; 336f37a7767SYoshihiro Shimoda }; 337f37a7767SYoshihiro Shimoda 338f37a7767SYoshihiro Shimoda sysc: system-controller@e6180000 { 339f37a7767SYoshihiro Shimoda compatible = "renesas,r8a77990-sysc"; 340f37a7767SYoshihiro Shimoda reg = <0 0xe6180000 0 0x0400>; 341f37a7767SYoshihiro Shimoda #power-domain-cells = <1>; 342f37a7767SYoshihiro Shimoda }; 343f37a7767SYoshihiro Shimoda 34455697cbbSMagnus Damm ipmmu_ds0: mmu@e6740000 { 34555697cbbSMagnus Damm compatible = "renesas,ipmmu-r8a77990"; 34655697cbbSMagnus Damm reg = <0 0xe6740000 0 0x1000>; 34755697cbbSMagnus Damm renesas,ipmmu-main = <&ipmmu_mm 0>; 34855697cbbSMagnus Damm power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 34955697cbbSMagnus Damm #iommu-cells = <1>; 35055697cbbSMagnus Damm }; 35155697cbbSMagnus Damm 35255697cbbSMagnus Damm ipmmu_ds1: mmu@e7740000 { 35355697cbbSMagnus Damm compatible = "renesas,ipmmu-r8a77990"; 35455697cbbSMagnus Damm reg = <0 0xe7740000 0 0x1000>; 35555697cbbSMagnus Damm renesas,ipmmu-main = <&ipmmu_mm 1>; 35655697cbbSMagnus Damm power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 35755697cbbSMagnus Damm #iommu-cells = <1>; 35855697cbbSMagnus Damm }; 35955697cbbSMagnus Damm 36055697cbbSMagnus Damm ipmmu_hc: mmu@e6570000 { 36155697cbbSMagnus Damm compatible = "renesas,ipmmu-r8a77990"; 36255697cbbSMagnus Damm reg = <0 0xe6570000 0 0x1000>; 36355697cbbSMagnus Damm renesas,ipmmu-main = <&ipmmu_mm 2>; 36455697cbbSMagnus Damm power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 36555697cbbSMagnus Damm #iommu-cells = <1>; 36655697cbbSMagnus Damm }; 36755697cbbSMagnus Damm 36855697cbbSMagnus Damm ipmmu_mm: mmu@e67b0000 { 36955697cbbSMagnus Damm compatible = "renesas,ipmmu-r8a77990"; 37055697cbbSMagnus Damm reg = <0 0xe67b0000 0 0x1000>; 37155697cbbSMagnus Damm interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 37255697cbbSMagnus Damm <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 37355697cbbSMagnus Damm power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 37455697cbbSMagnus Damm #iommu-cells = <1>; 37555697cbbSMagnus Damm }; 37655697cbbSMagnus Damm 37755697cbbSMagnus Damm ipmmu_mp: mmu@ec670000 { 37855697cbbSMagnus Damm compatible = "renesas,ipmmu-r8a77990"; 37955697cbbSMagnus Damm reg = <0 0xec670000 0 0x1000>; 38055697cbbSMagnus Damm renesas,ipmmu-main = <&ipmmu_mm 4>; 38155697cbbSMagnus Damm power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 38255697cbbSMagnus Damm #iommu-cells = <1>; 38355697cbbSMagnus Damm }; 38455697cbbSMagnus Damm 38555697cbbSMagnus Damm ipmmu_pv0: mmu@fd800000 { 38655697cbbSMagnus Damm compatible = "renesas,ipmmu-r8a77990"; 38755697cbbSMagnus Damm reg = <0 0xfd800000 0 0x1000>; 38855697cbbSMagnus Damm renesas,ipmmu-main = <&ipmmu_mm 6>; 38955697cbbSMagnus Damm power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 39055697cbbSMagnus Damm #iommu-cells = <1>; 39155697cbbSMagnus Damm }; 39255697cbbSMagnus Damm 39355697cbbSMagnus Damm ipmmu_rt: mmu@ffc80000 { 39455697cbbSMagnus Damm compatible = "renesas,ipmmu-r8a77990"; 39555697cbbSMagnus Damm reg = <0 0xffc80000 0 0x1000>; 39655697cbbSMagnus Damm renesas,ipmmu-main = <&ipmmu_mm 10>; 39755697cbbSMagnus Damm power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 39855697cbbSMagnus Damm #iommu-cells = <1>; 39955697cbbSMagnus Damm }; 40055697cbbSMagnus Damm 40155697cbbSMagnus Damm ipmmu_vc0: mmu@fe6b0000 { 40255697cbbSMagnus Damm compatible = "renesas,ipmmu-r8a77990"; 40355697cbbSMagnus Damm reg = <0 0xfe6b0000 0 0x1000>; 40455697cbbSMagnus Damm renesas,ipmmu-main = <&ipmmu_mm 12>; 40555697cbbSMagnus Damm power-domains = <&sysc R8A77990_PD_A3VC>; 40655697cbbSMagnus Damm #iommu-cells = <1>; 40755697cbbSMagnus Damm }; 40855697cbbSMagnus Damm 40955697cbbSMagnus Damm ipmmu_vi0: mmu@febd0000 { 41055697cbbSMagnus Damm compatible = "renesas,ipmmu-r8a77990"; 41155697cbbSMagnus Damm reg = <0 0xfebd0000 0 0x1000>; 41255697cbbSMagnus Damm renesas,ipmmu-main = <&ipmmu_mm 14>; 41355697cbbSMagnus Damm power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 41455697cbbSMagnus Damm #iommu-cells = <1>; 41555697cbbSMagnus Damm }; 41655697cbbSMagnus Damm 41755697cbbSMagnus Damm ipmmu_vp0: mmu@fe990000 { 41855697cbbSMagnus Damm compatible = "renesas,ipmmu-r8a77990"; 41955697cbbSMagnus Damm reg = <0 0xfe990000 0 0x1000>; 42055697cbbSMagnus Damm renesas,ipmmu-main = <&ipmmu_mm 16>; 42155697cbbSMagnus Damm power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 42255697cbbSMagnus Damm #iommu-cells = <1>; 42355697cbbSMagnus Damm }; 42455697cbbSMagnus Damm 425913a78b5SYoshihiro Shimoda avb: ethernet@e6800000 { 426913a78b5SYoshihiro Shimoda compatible = "renesas,etheravb-r8a77990", 427913a78b5SYoshihiro Shimoda "renesas,etheravb-rcar-gen3"; 4284b03df5fSGeert Uytterhoeven reg = <0 0xe6800000 0 0x800>; 429913a78b5SYoshihiro Shimoda interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 430913a78b5SYoshihiro Shimoda <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 431913a78b5SYoshihiro Shimoda <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 432913a78b5SYoshihiro Shimoda <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 433913a78b5SYoshihiro Shimoda <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 434913a78b5SYoshihiro Shimoda <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 435913a78b5SYoshihiro Shimoda <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 436913a78b5SYoshihiro Shimoda <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 437913a78b5SYoshihiro Shimoda <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 438913a78b5SYoshihiro Shimoda <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 439913a78b5SYoshihiro Shimoda <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 440913a78b5SYoshihiro Shimoda <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 441913a78b5SYoshihiro Shimoda <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 442913a78b5SYoshihiro Shimoda <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 443913a78b5SYoshihiro Shimoda <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 444913a78b5SYoshihiro Shimoda <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 445913a78b5SYoshihiro Shimoda <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 446913a78b5SYoshihiro Shimoda <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 447913a78b5SYoshihiro Shimoda <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 448913a78b5SYoshihiro Shimoda <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 449913a78b5SYoshihiro Shimoda <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 450913a78b5SYoshihiro Shimoda <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 451913a78b5SYoshihiro Shimoda <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 452913a78b5SYoshihiro Shimoda <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 453913a78b5SYoshihiro Shimoda <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 454913a78b5SYoshihiro Shimoda interrupt-names = "ch0", "ch1", "ch2", "ch3", 455913a78b5SYoshihiro Shimoda "ch4", "ch5", "ch6", "ch7", 456913a78b5SYoshihiro Shimoda "ch8", "ch9", "ch10", "ch11", 457913a78b5SYoshihiro Shimoda "ch12", "ch13", "ch14", "ch15", 458913a78b5SYoshihiro Shimoda "ch16", "ch17", "ch18", "ch19", 459913a78b5SYoshihiro Shimoda "ch20", "ch21", "ch22", "ch23", 460913a78b5SYoshihiro Shimoda "ch24"; 461913a78b5SYoshihiro Shimoda clocks = <&cpg CPG_MOD 812>; 46283e7d2ecSGeert Uytterhoeven power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 463913a78b5SYoshihiro Shimoda resets = <&cpg 812>; 464913a78b5SYoshihiro Shimoda phy-mode = "rgmii"; 465913a78b5SYoshihiro Shimoda #address-cells = <1>; 466913a78b5SYoshihiro Shimoda #size-cells = <0>; 467913a78b5SYoshihiro Shimoda status = "disabled"; 468913a78b5SYoshihiro Shimoda }; 469913a78b5SYoshihiro Shimoda 47018048556SYoshihiro Shimoda pwm0: pwm@e6e30000 { 47118048556SYoshihiro Shimoda compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 47218048556SYoshihiro Shimoda reg = <0 0xe6e30000 0 0x8>; 47318048556SYoshihiro Shimoda clocks = <&cpg CPG_MOD 523>; 47418048556SYoshihiro Shimoda power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 47518048556SYoshihiro Shimoda resets = <&cpg 523>; 47618048556SYoshihiro Shimoda #pwm-cells = <2>; 47718048556SYoshihiro Shimoda status = "disabled"; 47818048556SYoshihiro Shimoda }; 47918048556SYoshihiro Shimoda 48018048556SYoshihiro Shimoda pwm1: pwm@e6e31000 { 48118048556SYoshihiro Shimoda compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 48218048556SYoshihiro Shimoda reg = <0 0xe6e31000 0 0x8>; 48318048556SYoshihiro Shimoda clocks = <&cpg CPG_MOD 523>; 48418048556SYoshihiro Shimoda power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 48518048556SYoshihiro Shimoda resets = <&cpg 523>; 48618048556SYoshihiro Shimoda #pwm-cells = <2>; 48718048556SYoshihiro Shimoda status = "disabled"; 48818048556SYoshihiro Shimoda }; 48918048556SYoshihiro Shimoda 49018048556SYoshihiro Shimoda pwm2: pwm@e6e32000 { 49118048556SYoshihiro Shimoda compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 49218048556SYoshihiro Shimoda reg = <0 0xe6e32000 0 0x8>; 49318048556SYoshihiro Shimoda clocks = <&cpg CPG_MOD 523>; 49418048556SYoshihiro Shimoda power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 49518048556SYoshihiro Shimoda resets = <&cpg 523>; 49618048556SYoshihiro Shimoda #pwm-cells = <2>; 49718048556SYoshihiro Shimoda status = "disabled"; 49818048556SYoshihiro Shimoda }; 49918048556SYoshihiro Shimoda 50018048556SYoshihiro Shimoda pwm3: pwm@e6e33000 { 50118048556SYoshihiro Shimoda compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 50218048556SYoshihiro Shimoda reg = <0 0xe6e33000 0 0x8>; 50318048556SYoshihiro Shimoda clocks = <&cpg CPG_MOD 523>; 50418048556SYoshihiro Shimoda power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 50518048556SYoshihiro Shimoda resets = <&cpg 523>; 50618048556SYoshihiro Shimoda #pwm-cells = <2>; 50718048556SYoshihiro Shimoda status = "disabled"; 50818048556SYoshihiro Shimoda }; 50918048556SYoshihiro Shimoda 51018048556SYoshihiro Shimoda pwm4: pwm@e6e34000 { 51118048556SYoshihiro Shimoda compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 51218048556SYoshihiro Shimoda reg = <0 0xe6e34000 0 0x8>; 51318048556SYoshihiro Shimoda clocks = <&cpg CPG_MOD 523>; 51418048556SYoshihiro Shimoda power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 51518048556SYoshihiro Shimoda resets = <&cpg 523>; 51618048556SYoshihiro Shimoda #pwm-cells = <2>; 51718048556SYoshihiro Shimoda status = "disabled"; 51818048556SYoshihiro Shimoda }; 51918048556SYoshihiro Shimoda 52018048556SYoshihiro Shimoda pwm5: pwm@e6e35000 { 52118048556SYoshihiro Shimoda compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 52218048556SYoshihiro Shimoda reg = <0 0xe6e35000 0 0x8>; 52318048556SYoshihiro Shimoda clocks = <&cpg CPG_MOD 523>; 52418048556SYoshihiro Shimoda power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 52518048556SYoshihiro Shimoda resets = <&cpg 523>; 52618048556SYoshihiro Shimoda #pwm-cells = <2>; 52718048556SYoshihiro Shimoda status = "disabled"; 52818048556SYoshihiro Shimoda }; 52918048556SYoshihiro Shimoda 53018048556SYoshihiro Shimoda pwm6: pwm@e6e36000 { 53118048556SYoshihiro Shimoda compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 53218048556SYoshihiro Shimoda reg = <0 0xe6e36000 0 0x8>; 53318048556SYoshihiro Shimoda clocks = <&cpg CPG_MOD 523>; 53418048556SYoshihiro Shimoda power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 53518048556SYoshihiro Shimoda resets = <&cpg 523>; 53618048556SYoshihiro Shimoda #pwm-cells = <2>; 53718048556SYoshihiro Shimoda status = "disabled"; 53818048556SYoshihiro Shimoda }; 53918048556SYoshihiro Shimoda 540f37a7767SYoshihiro Shimoda scif2: serial@e6e88000 { 541f37a7767SYoshihiro Shimoda compatible = "renesas,scif-r8a77990", 542f37a7767SYoshihiro Shimoda "renesas,rcar-gen3-scif", "renesas,scif"; 543f37a7767SYoshihiro Shimoda reg = <0 0xe6e88000 0 64>; 544f37a7767SYoshihiro Shimoda interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 545103db9b5STakeshi Kihara clocks = <&cpg CPG_MOD 310>, 546103db9b5STakeshi Kihara <&cpg CPG_CORE R8A77990_CLK_S3D1C>, 547103db9b5STakeshi Kihara <&scif_clk>; 548103db9b5STakeshi Kihara clock-names = "fck", "brg_int", "scif_clk"; 549103db9b5STakeshi Kihara 55083e7d2ecSGeert Uytterhoeven power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 551f37a7767SYoshihiro Shimoda resets = <&cpg 310>; 552f37a7767SYoshihiro Shimoda status = "disabled"; 553f37a7767SYoshihiro Shimoda }; 554f37a7767SYoshihiro Shimoda 5554b7e3ab1SGeert Uytterhoeven msiof0: spi@e6e90000 { 5564b7e3ab1SGeert Uytterhoeven compatible = "renesas,msiof-r8a77990", 5574b7e3ab1SGeert Uytterhoeven "renesas,rcar-gen3-msiof"; 5584b7e3ab1SGeert Uytterhoeven reg = <0 0xe6e90000 0 0x0064>; 5594b7e3ab1SGeert Uytterhoeven interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 5604b7e3ab1SGeert Uytterhoeven clocks = <&cpg CPG_MOD 211>; 5614b7e3ab1SGeert Uytterhoeven power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 5624b7e3ab1SGeert Uytterhoeven resets = <&cpg 211>; 5634b7e3ab1SGeert Uytterhoeven #address-cells = <1>; 5644b7e3ab1SGeert Uytterhoeven #size-cells = <0>; 5654b7e3ab1SGeert Uytterhoeven status = "disabled"; 5664b7e3ab1SGeert Uytterhoeven }; 5674b7e3ab1SGeert Uytterhoeven 5684b7e3ab1SGeert Uytterhoeven msiof1: spi@e6ea0000 { 5694b7e3ab1SGeert Uytterhoeven compatible = "renesas,msiof-r8a77990", 5704b7e3ab1SGeert Uytterhoeven "renesas,rcar-gen3-msiof"; 5714b7e3ab1SGeert Uytterhoeven reg = <0 0xe6ea0000 0 0x0064>; 5724b7e3ab1SGeert Uytterhoeven interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 5734b7e3ab1SGeert Uytterhoeven clocks = <&cpg CPG_MOD 210>; 5744b7e3ab1SGeert Uytterhoeven power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 5754b7e3ab1SGeert Uytterhoeven resets = <&cpg 210>; 5764b7e3ab1SGeert Uytterhoeven #address-cells = <1>; 5774b7e3ab1SGeert Uytterhoeven #size-cells = <0>; 5784b7e3ab1SGeert Uytterhoeven status = "disabled"; 5794b7e3ab1SGeert Uytterhoeven }; 5804b7e3ab1SGeert Uytterhoeven 5814b7e3ab1SGeert Uytterhoeven msiof2: spi@e6c00000 { 5824b7e3ab1SGeert Uytterhoeven compatible = "renesas,msiof-r8a77990", 5834b7e3ab1SGeert Uytterhoeven "renesas,rcar-gen3-msiof"; 5844b7e3ab1SGeert Uytterhoeven reg = <0 0xe6c00000 0 0x0064>; 5854b7e3ab1SGeert Uytterhoeven interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 5864b7e3ab1SGeert Uytterhoeven clocks = <&cpg CPG_MOD 209>; 5874b7e3ab1SGeert Uytterhoeven power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 5884b7e3ab1SGeert Uytterhoeven resets = <&cpg 209>; 5894b7e3ab1SGeert Uytterhoeven #address-cells = <1>; 5904b7e3ab1SGeert Uytterhoeven #size-cells = <0>; 5914b7e3ab1SGeert Uytterhoeven status = "disabled"; 5924b7e3ab1SGeert Uytterhoeven }; 5934b7e3ab1SGeert Uytterhoeven 5944b7e3ab1SGeert Uytterhoeven msiof3: spi@e6c10000 { 5954b7e3ab1SGeert Uytterhoeven compatible = "renesas,msiof-r8a77990", 5964b7e3ab1SGeert Uytterhoeven "renesas,rcar-gen3-msiof"; 5974b7e3ab1SGeert Uytterhoeven reg = <0 0xe6c10000 0 0x0064>; 5984b7e3ab1SGeert Uytterhoeven interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 5994b7e3ab1SGeert Uytterhoeven clocks = <&cpg CPG_MOD 208>; 6004b7e3ab1SGeert Uytterhoeven power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 6014b7e3ab1SGeert Uytterhoeven resets = <&cpg 208>; 6024b7e3ab1SGeert Uytterhoeven #address-cells = <1>; 6034b7e3ab1SGeert Uytterhoeven #size-cells = <0>; 6044b7e3ab1SGeert Uytterhoeven status = "disabled"; 6054b7e3ab1SGeert Uytterhoeven }; 6064b7e3ab1SGeert Uytterhoeven 607ec70407aSKoji Matsuoka vin4: video@e6ef4000 { 608ec70407aSKoji Matsuoka compatible = "renesas,vin-r8a77990"; 609ec70407aSKoji Matsuoka reg = <0 0xe6ef4000 0 0x1000>; 610ec70407aSKoji Matsuoka interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 611ec70407aSKoji Matsuoka clocks = <&cpg CPG_MOD 807>; 612ec70407aSKoji Matsuoka power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 613ec70407aSKoji Matsuoka resets = <&cpg 807>; 614ec70407aSKoji Matsuoka renesas,id = <4>; 615ec70407aSKoji Matsuoka status = "disabled"; 616ec70407aSKoji Matsuoka 617ec70407aSKoji Matsuoka ports { 618ec70407aSKoji Matsuoka #address-cells = <1>; 619ec70407aSKoji Matsuoka #size-cells = <0>; 620ec70407aSKoji Matsuoka 621ec70407aSKoji Matsuoka port@1 { 622ec70407aSKoji Matsuoka reg = <1>; 623ec70407aSKoji Matsuoka 624ec70407aSKoji Matsuoka vin4csi40: endpoint { 625ec70407aSKoji Matsuoka remote-endpoint= <&csi40vin4>; 626ec70407aSKoji Matsuoka }; 627ec70407aSKoji Matsuoka }; 628ec70407aSKoji Matsuoka }; 629ec70407aSKoji Matsuoka }; 630ec70407aSKoji Matsuoka 631ec70407aSKoji Matsuoka vin5: video@e6ef5000 { 632ec70407aSKoji Matsuoka compatible = "renesas,vin-r8a77990"; 633ec70407aSKoji Matsuoka reg = <0 0xe6ef5000 0 0x1000>; 634ec70407aSKoji Matsuoka interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 635ec70407aSKoji Matsuoka clocks = <&cpg CPG_MOD 806>; 636ec70407aSKoji Matsuoka power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 637ec70407aSKoji Matsuoka resets = <&cpg 806>; 638ec70407aSKoji Matsuoka renesas,id = <5>; 639ec70407aSKoji Matsuoka status = "disabled"; 640ec70407aSKoji Matsuoka 641ec70407aSKoji Matsuoka ports { 642ec70407aSKoji Matsuoka #address-cells = <1>; 643ec70407aSKoji Matsuoka #size-cells = <0>; 644ec70407aSKoji Matsuoka 645ec70407aSKoji Matsuoka port@1 { 646ec70407aSKoji Matsuoka reg = <1>; 647ec70407aSKoji Matsuoka 648ec70407aSKoji Matsuoka vin5csi40: endpoint { 649ec70407aSKoji Matsuoka remote-endpoint= <&csi40vin5>; 650ec70407aSKoji Matsuoka }; 651ec70407aSKoji Matsuoka }; 652ec70407aSKoji Matsuoka }; 653ec70407aSKoji Matsuoka }; 654ec70407aSKoji Matsuoka 655fe1bc94aSYoshihiro Shimoda xhci0: usb@ee000000 { 656fe1bc94aSYoshihiro Shimoda compatible = "renesas,xhci-r8a77990", 657fe1bc94aSYoshihiro Shimoda "renesas,rcar-gen3-xhci"; 658fe1bc94aSYoshihiro Shimoda reg = <0 0xee000000 0 0xc00>; 659fe1bc94aSYoshihiro Shimoda interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 660fe1bc94aSYoshihiro Shimoda clocks = <&cpg CPG_MOD 328>; 661fe1bc94aSYoshihiro Shimoda power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 662fe1bc94aSYoshihiro Shimoda resets = <&cpg 328>; 663fe1bc94aSYoshihiro Shimoda status = "disabled"; 664fe1bc94aSYoshihiro Shimoda }; 665fe1bc94aSYoshihiro Shimoda 6666dd72b4dSYoshihiro Shimoda ohci0: usb@ee080000 { 6676dd72b4dSYoshihiro Shimoda compatible = "generic-ohci"; 6686dd72b4dSYoshihiro Shimoda reg = <0 0xee080000 0 0x100>; 6696dd72b4dSYoshihiro Shimoda interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 6706dd72b4dSYoshihiro Shimoda clocks = <&cpg CPG_MOD 703>; 6716dd72b4dSYoshihiro Shimoda phys = <&usb2_phy0>; 6726dd72b4dSYoshihiro Shimoda phy-names = "usb"; 67383e7d2ecSGeert Uytterhoeven power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 6746dd72b4dSYoshihiro Shimoda resets = <&cpg 703>; 6756dd72b4dSYoshihiro Shimoda status = "disabled"; 6766dd72b4dSYoshihiro Shimoda }; 6776dd72b4dSYoshihiro Shimoda 6786dd72b4dSYoshihiro Shimoda ehci0: usb@ee080100 { 6796dd72b4dSYoshihiro Shimoda compatible = "generic-ehci"; 6806dd72b4dSYoshihiro Shimoda reg = <0 0xee080100 0 0x100>; 6816dd72b4dSYoshihiro Shimoda interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 6826dd72b4dSYoshihiro Shimoda clocks = <&cpg CPG_MOD 703>; 6836dd72b4dSYoshihiro Shimoda phys = <&usb2_phy0>; 6846dd72b4dSYoshihiro Shimoda phy-names = "usb"; 6856dd72b4dSYoshihiro Shimoda companion = <&ohci0>; 68683e7d2ecSGeert Uytterhoeven power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 6876dd72b4dSYoshihiro Shimoda resets = <&cpg 703>; 6886dd72b4dSYoshihiro Shimoda status = "disabled"; 6896dd72b4dSYoshihiro Shimoda }; 6906dd72b4dSYoshihiro Shimoda 6916dd72b4dSYoshihiro Shimoda usb2_phy0: usb-phy@ee080200 { 6926dd72b4dSYoshihiro Shimoda compatible = "renesas,usb2-phy-r8a77990", 6936dd72b4dSYoshihiro Shimoda "renesas,rcar-gen3-usb2-phy"; 6946dd72b4dSYoshihiro Shimoda reg = <0 0xee080200 0 0x700>; 6956dd72b4dSYoshihiro Shimoda interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 6966dd72b4dSYoshihiro Shimoda clocks = <&cpg CPG_MOD 703>; 69783e7d2ecSGeert Uytterhoeven power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 6986dd72b4dSYoshihiro Shimoda resets = <&cpg 703>; 6996dd72b4dSYoshihiro Shimoda #phy-cells = <0>; 7006dd72b4dSYoshihiro Shimoda status = "disabled"; 7016dd72b4dSYoshihiro Shimoda }; 7026dd72b4dSYoshihiro Shimoda 703f37a7767SYoshihiro Shimoda gic: interrupt-controller@f1010000 { 704f37a7767SYoshihiro Shimoda compatible = "arm,gic-400"; 705f37a7767SYoshihiro Shimoda #interrupt-cells = <3>; 706f37a7767SYoshihiro Shimoda #address-cells = <0>; 707f37a7767SYoshihiro Shimoda interrupt-controller; 708f37a7767SYoshihiro Shimoda reg = <0x0 0xf1010000 0 0x1000>, 709f37a7767SYoshihiro Shimoda <0x0 0xf1020000 0 0x20000>, 710f37a7767SYoshihiro Shimoda <0x0 0xf1040000 0 0x20000>, 711f37a7767SYoshihiro Shimoda <0x0 0xf1060000 0 0x20000>; 712f37a7767SYoshihiro Shimoda interrupts = <GIC_PPI 9 7137085f5d9SGeert Uytterhoeven (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 714f37a7767SYoshihiro Shimoda clocks = <&cpg CPG_MOD 408>; 715f37a7767SYoshihiro Shimoda clock-names = "clk"; 71683e7d2ecSGeert Uytterhoeven power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 717f37a7767SYoshihiro Shimoda resets = <&cpg 408>; 718f37a7767SYoshihiro Shimoda }; 719f37a7767SYoshihiro Shimoda 720ec70407aSKoji Matsuoka csi40: csi2@feaa0000 { 721ec70407aSKoji Matsuoka compatible = "renesas,r8a77990-csi2", "renesas,rcar-gen3-csi2"; 722ec70407aSKoji Matsuoka reg = <0 0xfeaa0000 0 0x10000>; 723ec70407aSKoji Matsuoka interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 724ec70407aSKoji Matsuoka clocks = <&cpg CPG_MOD 716>; 725ec70407aSKoji Matsuoka power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 726ec70407aSKoji Matsuoka resets = <&cpg 716>; 727ec70407aSKoji Matsuoka status = "disabled"; 728ec70407aSKoji Matsuoka 729ec70407aSKoji Matsuoka ports { 730ec70407aSKoji Matsuoka #address-cells = <1>; 731ec70407aSKoji Matsuoka #size-cells = <0>; 732ec70407aSKoji Matsuoka 733ec70407aSKoji Matsuoka port@1 { 734ec70407aSKoji Matsuoka #address-cells = <1>; 735ec70407aSKoji Matsuoka #size-cells = <0>; 736ec70407aSKoji Matsuoka 737ec70407aSKoji Matsuoka reg = <1>; 738ec70407aSKoji Matsuoka 739ec70407aSKoji Matsuoka csi40vin4: endpoint@0 { 740ec70407aSKoji Matsuoka reg = <0>; 741ec70407aSKoji Matsuoka remote-endpoint = <&vin4csi40>; 742ec70407aSKoji Matsuoka }; 743ec70407aSKoji Matsuoka csi40vin5: endpoint@1 { 744ec70407aSKoji Matsuoka reg = <1>; 745ec70407aSKoji Matsuoka remote-endpoint = <&vin5csi40>; 746ec70407aSKoji Matsuoka }; 747ec70407aSKoji Matsuoka }; 748ec70407aSKoji Matsuoka }; 749ec70407aSKoji Matsuoka }; 750ec70407aSKoji Matsuoka 751f37a7767SYoshihiro Shimoda prr: chipid@fff00044 { 752f37a7767SYoshihiro Shimoda compatible = "renesas,prr"; 753f37a7767SYoshihiro Shimoda reg = <0 0xfff00044 0 4>; 754f37a7767SYoshihiro Shimoda }; 755f37a7767SYoshihiro Shimoda }; 756f37a7767SYoshihiro Shimoda 757f37a7767SYoshihiro Shimoda timer { 758f37a7767SYoshihiro Shimoda compatible = "arm,armv8-timer"; 7597085f5d9SGeert Uytterhoeven interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 7607085f5d9SGeert Uytterhoeven <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 7617085f5d9SGeert Uytterhoeven <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 7627085f5d9SGeert Uytterhoeven <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 763f37a7767SYoshihiro Shimoda }; 764f37a7767SYoshihiro Shimoda}; 765