xref: /linux/scripts/dtc/include-prefixes/arm64/renesas/r8a77990.dtsi (revision 5c6479d9b25b40001e814003f62a93485f9ff82f)
1f37a7767SYoshihiro Shimoda/* SPDX-License-Identifier: GPL-2.0 */
2f37a7767SYoshihiro Shimoda/*
3e18a31a7SMagnus Damm * Device Tree Source for the R-Car E3 (R8A77990) SoC
4f37a7767SYoshihiro Shimoda *
5f37a7767SYoshihiro Shimoda * Copyright (C) 2018 Renesas Electronics Corp.
6f37a7767SYoshihiro Shimoda */
7f37a7767SYoshihiro Shimoda
883e7d2ecSGeert Uytterhoeven#include <dt-bindings/clock/r8a77990-cpg-mssr.h>
9f37a7767SYoshihiro Shimoda#include <dt-bindings/interrupt-controller/arm-gic.h>
1055697cbbSMagnus Damm#include <dt-bindings/power/r8a77990-sysc.h>
11f37a7767SYoshihiro Shimoda
12f37a7767SYoshihiro Shimoda/ {
13f37a7767SYoshihiro Shimoda	compatible = "renesas,r8a77990";
14f37a7767SYoshihiro Shimoda	#address-cells = <2>;
15f37a7767SYoshihiro Shimoda	#size-cells = <2>;
16f37a7767SYoshihiro Shimoda
17bc011dfaSTakeshi Kihara	aliases {
18bc011dfaSTakeshi Kihara		i2c0 = &i2c0;
19bc011dfaSTakeshi Kihara		i2c1 = &i2c1;
20bc011dfaSTakeshi Kihara		i2c2 = &i2c2;
21bc011dfaSTakeshi Kihara		i2c3 = &i2c3;
22bc011dfaSTakeshi Kihara		i2c4 = &i2c4;
23bc011dfaSTakeshi Kihara		i2c5 = &i2c5;
24bc011dfaSTakeshi Kihara		i2c6 = &i2c6;
25bc011dfaSTakeshi Kihara		i2c7 = &i2c7;
26bc011dfaSTakeshi Kihara	};
27bc011dfaSTakeshi Kihara
28f37a7767SYoshihiro Shimoda	cpus {
29f37a7767SYoshihiro Shimoda		#address-cells = <1>;
30f37a7767SYoshihiro Shimoda		#size-cells = <0>;
31f37a7767SYoshihiro Shimoda
32f37a7767SYoshihiro Shimoda		a53_0: cpu@0 {
33f37a7767SYoshihiro Shimoda			compatible = "arm,cortex-a53", "arm,armv8";
347085f5d9SGeert Uytterhoeven			reg = <0>;
35f37a7767SYoshihiro Shimoda			device_type = "cpu";
3683e7d2ecSGeert Uytterhoeven			power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
37f37a7767SYoshihiro Shimoda			next-level-cache = <&L2_CA53>;
38f37a7767SYoshihiro Shimoda			enable-method = "psci";
39f37a7767SYoshihiro Shimoda		};
40f37a7767SYoshihiro Shimoda
417085f5d9SGeert Uytterhoeven		a53_1: cpu@1 {
427085f5d9SGeert Uytterhoeven			compatible = "arm,cortex-a53", "arm,armv8";
437085f5d9SGeert Uytterhoeven			reg = <1>;
447085f5d9SGeert Uytterhoeven			device_type = "cpu";
4583e7d2ecSGeert Uytterhoeven			power-domains = <&sysc R8A77990_PD_CA53_CPU1>;
467085f5d9SGeert Uytterhoeven			next-level-cache = <&L2_CA53>;
477085f5d9SGeert Uytterhoeven			enable-method = "psci";
487085f5d9SGeert Uytterhoeven		};
497085f5d9SGeert Uytterhoeven
50de1eb23cSYoshihiro Shimoda		L2_CA53: cache-controller-0 {
51f37a7767SYoshihiro Shimoda			compatible = "cache";
5283e7d2ecSGeert Uytterhoeven			power-domains = <&sysc R8A77990_PD_CA53_SCU>;
53f37a7767SYoshihiro Shimoda			cache-unified;
54f37a7767SYoshihiro Shimoda			cache-level = <2>;
55f37a7767SYoshihiro Shimoda		};
56f37a7767SYoshihiro Shimoda	};
57f37a7767SYoshihiro Shimoda
58f37a7767SYoshihiro Shimoda	extal_clk: extal {
59f37a7767SYoshihiro Shimoda		compatible = "fixed-clock";
60f37a7767SYoshihiro Shimoda		#clock-cells = <0>;
61f37a7767SYoshihiro Shimoda		/* This value must be overridden by the board */
62f37a7767SYoshihiro Shimoda		clock-frequency = <0>;
63f37a7767SYoshihiro Shimoda	};
64f37a7767SYoshihiro Shimoda
65f37a7767SYoshihiro Shimoda	pmu_a53 {
66f37a7767SYoshihiro Shimoda		compatible = "arm,cortex-a53-pmu";
677085f5d9SGeert Uytterhoeven		interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
687085f5d9SGeert Uytterhoeven				      <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
697085f5d9SGeert Uytterhoeven		interrupt-affinity = <&a53_0>, <&a53_1>;
70f37a7767SYoshihiro Shimoda	};
71f37a7767SYoshihiro Shimoda
72f37a7767SYoshihiro Shimoda	psci {
73bc26b8f4SYoshihiro Shimoda		compatible = "arm,psci-1.0", "arm,psci-0.2";
74f37a7767SYoshihiro Shimoda		method = "smc";
75f37a7767SYoshihiro Shimoda	};
76f37a7767SYoshihiro Shimoda
77103db9b5STakeshi Kihara	/* External SCIF clock - to be overridden by boards that provide it */
78103db9b5STakeshi Kihara	scif_clk: scif {
79103db9b5STakeshi Kihara		compatible = "fixed-clock";
80103db9b5STakeshi Kihara		#clock-cells = <0>;
81103db9b5STakeshi Kihara		clock-frequency = <0>;
82103db9b5STakeshi Kihara	};
83103db9b5STakeshi Kihara
84f37a7767SYoshihiro Shimoda	soc: soc {
85f37a7767SYoshihiro Shimoda		compatible = "simple-bus";
86f37a7767SYoshihiro Shimoda		interrupt-parent = <&gic>;
87f37a7767SYoshihiro Shimoda		#address-cells = <2>;
88f37a7767SYoshihiro Shimoda		#size-cells = <2>;
89f37a7767SYoshihiro Shimoda		ranges;
90f37a7767SYoshihiro Shimoda
91eb614d94STakeshi Kihara		rwdt: watchdog@e6020000 {
92eb614d94STakeshi Kihara			compatible = "renesas,r8a77990-wdt",
93eb614d94STakeshi Kihara				     "renesas,rcar-gen3-wdt";
94eb614d94STakeshi Kihara			reg = <0 0xe6020000 0 0x0c>;
95eb614d94STakeshi Kihara			clocks = <&cpg CPG_MOD 402>;
9683e7d2ecSGeert Uytterhoeven			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
97eb614d94STakeshi Kihara			resets = <&cpg 402>;
98eb614d94STakeshi Kihara			status = "disabled";
99eb614d94STakeshi Kihara		};
100eb614d94STakeshi Kihara
1010d292de1SYoshihiro Shimoda		gpio0: gpio@e6050000 {
1020d292de1SYoshihiro Shimoda			compatible = "renesas,gpio-r8a77990",
1030d292de1SYoshihiro Shimoda				     "renesas,rcar-gen3-gpio";
1040d292de1SYoshihiro Shimoda			reg = <0 0xe6050000 0 0x50>;
1050d292de1SYoshihiro Shimoda			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1060d292de1SYoshihiro Shimoda			#gpio-cells = <2>;
1070d292de1SYoshihiro Shimoda			gpio-controller;
1080d292de1SYoshihiro Shimoda			gpio-ranges = <&pfc 0 0 18>;
1090d292de1SYoshihiro Shimoda			#interrupt-cells = <2>;
1100d292de1SYoshihiro Shimoda			interrupt-controller;
1110d292de1SYoshihiro Shimoda			clocks = <&cpg CPG_MOD 912>;
11283e7d2ecSGeert Uytterhoeven			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1130d292de1SYoshihiro Shimoda			resets = <&cpg 912>;
1140d292de1SYoshihiro Shimoda		};
1150d292de1SYoshihiro Shimoda
1160d292de1SYoshihiro Shimoda		gpio1: gpio@e6051000 {
1170d292de1SYoshihiro Shimoda			compatible = "renesas,gpio-r8a77990",
1180d292de1SYoshihiro Shimoda				     "renesas,rcar-gen3-gpio";
1190d292de1SYoshihiro Shimoda			reg = <0 0xe6051000 0 0x50>;
1200d292de1SYoshihiro Shimoda			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1210d292de1SYoshihiro Shimoda			#gpio-cells = <2>;
1220d292de1SYoshihiro Shimoda			gpio-controller;
1230d292de1SYoshihiro Shimoda			gpio-ranges = <&pfc 0 32 23>;
1240d292de1SYoshihiro Shimoda			#interrupt-cells = <2>;
1250d292de1SYoshihiro Shimoda			interrupt-controller;
1260d292de1SYoshihiro Shimoda			clocks = <&cpg CPG_MOD 911>;
12783e7d2ecSGeert Uytterhoeven			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1280d292de1SYoshihiro Shimoda			resets = <&cpg 911>;
1290d292de1SYoshihiro Shimoda		};
1300d292de1SYoshihiro Shimoda
1310d292de1SYoshihiro Shimoda		gpio2: gpio@e6052000 {
1320d292de1SYoshihiro Shimoda			compatible = "renesas,gpio-r8a77990",
1330d292de1SYoshihiro Shimoda				     "renesas,rcar-gen3-gpio";
1340d292de1SYoshihiro Shimoda			reg = <0 0xe6052000 0 0x50>;
1350d292de1SYoshihiro Shimoda			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1360d292de1SYoshihiro Shimoda			#gpio-cells = <2>;
1370d292de1SYoshihiro Shimoda			gpio-controller;
1380d292de1SYoshihiro Shimoda			gpio-ranges = <&pfc 0 64 26>;
1390d292de1SYoshihiro Shimoda			#interrupt-cells = <2>;
1400d292de1SYoshihiro Shimoda			interrupt-controller;
1410d292de1SYoshihiro Shimoda			clocks = <&cpg CPG_MOD 910>;
14283e7d2ecSGeert Uytterhoeven			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1430d292de1SYoshihiro Shimoda			resets = <&cpg 910>;
1440d292de1SYoshihiro Shimoda		};
1450d292de1SYoshihiro Shimoda
1460d292de1SYoshihiro Shimoda		gpio3: gpio@e6053000 {
1470d292de1SYoshihiro Shimoda			compatible = "renesas,gpio-r8a77990",
1480d292de1SYoshihiro Shimoda				     "renesas,rcar-gen3-gpio";
1490d292de1SYoshihiro Shimoda			reg = <0 0xe6053000 0 0x50>;
1500d292de1SYoshihiro Shimoda			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1510d292de1SYoshihiro Shimoda			#gpio-cells = <2>;
1520d292de1SYoshihiro Shimoda			gpio-controller;
1530d292de1SYoshihiro Shimoda			gpio-ranges = <&pfc 0 96 16>;
1540d292de1SYoshihiro Shimoda			#interrupt-cells = <2>;
1550d292de1SYoshihiro Shimoda			interrupt-controller;
1560d292de1SYoshihiro Shimoda			clocks = <&cpg CPG_MOD 909>;
15783e7d2ecSGeert Uytterhoeven			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1580d292de1SYoshihiro Shimoda			resets = <&cpg 909>;
1590d292de1SYoshihiro Shimoda		};
1600d292de1SYoshihiro Shimoda
1610d292de1SYoshihiro Shimoda		gpio4: gpio@e6054000 {
1620d292de1SYoshihiro Shimoda			compatible = "renesas,gpio-r8a77990",
1630d292de1SYoshihiro Shimoda				     "renesas,rcar-gen3-gpio";
1640d292de1SYoshihiro Shimoda			reg = <0 0xe6054000 0 0x50>;
1650d292de1SYoshihiro Shimoda			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1660d292de1SYoshihiro Shimoda			#gpio-cells = <2>;
1670d292de1SYoshihiro Shimoda			gpio-controller;
1680d292de1SYoshihiro Shimoda			gpio-ranges = <&pfc 0 128 11>;
1690d292de1SYoshihiro Shimoda			#interrupt-cells = <2>;
1700d292de1SYoshihiro Shimoda			interrupt-controller;
1710d292de1SYoshihiro Shimoda			clocks = <&cpg CPG_MOD 908>;
17283e7d2ecSGeert Uytterhoeven			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1730d292de1SYoshihiro Shimoda			resets = <&cpg 908>;
1740d292de1SYoshihiro Shimoda		};
1750d292de1SYoshihiro Shimoda
1760d292de1SYoshihiro Shimoda		gpio5: gpio@e6055000 {
1770d292de1SYoshihiro Shimoda			compatible = "renesas,gpio-r8a77990",
1780d292de1SYoshihiro Shimoda				     "renesas,rcar-gen3-gpio";
1790d292de1SYoshihiro Shimoda			reg = <0 0xe6055000 0 0x50>;
1800d292de1SYoshihiro Shimoda			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1810d292de1SYoshihiro Shimoda			#gpio-cells = <2>;
1820d292de1SYoshihiro Shimoda			gpio-controller;
1830d292de1SYoshihiro Shimoda			gpio-ranges = <&pfc 0 160 20>;
1840d292de1SYoshihiro Shimoda			#interrupt-cells = <2>;
1850d292de1SYoshihiro Shimoda			interrupt-controller;
1860d292de1SYoshihiro Shimoda			clocks = <&cpg CPG_MOD 907>;
18783e7d2ecSGeert Uytterhoeven			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1880d292de1SYoshihiro Shimoda			resets = <&cpg 907>;
1890d292de1SYoshihiro Shimoda		};
1900d292de1SYoshihiro Shimoda
1910d292de1SYoshihiro Shimoda		gpio6: gpio@e6055400 {
1920d292de1SYoshihiro Shimoda			compatible = "renesas,gpio-r8a77990",
1930d292de1SYoshihiro Shimoda				     "renesas,rcar-gen3-gpio";
1940d292de1SYoshihiro Shimoda			reg = <0 0xe6055400 0 0x50>;
1950d292de1SYoshihiro Shimoda			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1960d292de1SYoshihiro Shimoda			#gpio-cells = <2>;
1970d292de1SYoshihiro Shimoda			gpio-controller;
1980d292de1SYoshihiro Shimoda			gpio-ranges = <&pfc 0 192 18>;
1990d292de1SYoshihiro Shimoda			#interrupt-cells = <2>;
2000d292de1SYoshihiro Shimoda			interrupt-controller;
2010d292de1SYoshihiro Shimoda			clocks = <&cpg CPG_MOD 906>;
20283e7d2ecSGeert Uytterhoeven			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
2030d292de1SYoshihiro Shimoda			resets = <&cpg 906>;
2040d292de1SYoshihiro Shimoda		};
2050d292de1SYoshihiro Shimoda
206bc011dfaSTakeshi Kihara		i2c0: i2c@e6500000 {
207bc011dfaSTakeshi Kihara			#address-cells = <1>;
208bc011dfaSTakeshi Kihara			#size-cells = <0>;
209bc011dfaSTakeshi Kihara			compatible = "renesas,i2c-r8a77990",
210bc011dfaSTakeshi Kihara				     "renesas,rcar-gen3-i2c";
211bc011dfaSTakeshi Kihara			reg = <0 0xe6500000 0 0x40>;
212bc011dfaSTakeshi Kihara			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
213bc011dfaSTakeshi Kihara			clocks = <&cpg CPG_MOD 931>;
214bc011dfaSTakeshi Kihara			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
215bc011dfaSTakeshi Kihara			resets = <&cpg 931>;
216bc011dfaSTakeshi Kihara			i2c-scl-internal-delay-ns = <110>;
217bc011dfaSTakeshi Kihara			status = "disabled";
218bc011dfaSTakeshi Kihara		};
219bc011dfaSTakeshi Kihara
220bc011dfaSTakeshi Kihara		i2c1: i2c@e6508000 {
221bc011dfaSTakeshi Kihara			#address-cells = <1>;
222bc011dfaSTakeshi Kihara			#size-cells = <0>;
223bc011dfaSTakeshi Kihara			compatible = "renesas,i2c-r8a77990",
224bc011dfaSTakeshi Kihara				     "renesas,rcar-gen3-i2c";
225bc011dfaSTakeshi Kihara			reg = <0 0xe6508000 0 0x40>;
226bc011dfaSTakeshi Kihara			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
227bc011dfaSTakeshi Kihara			clocks = <&cpg CPG_MOD 930>;
228bc011dfaSTakeshi Kihara			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
229bc011dfaSTakeshi Kihara			resets = <&cpg 930>;
230bc011dfaSTakeshi Kihara			i2c-scl-internal-delay-ns = <6>;
231bc011dfaSTakeshi Kihara			status = "disabled";
232bc011dfaSTakeshi Kihara		};
233bc011dfaSTakeshi Kihara
234bc011dfaSTakeshi Kihara		i2c2: i2c@e6510000 {
235bc011dfaSTakeshi Kihara			#address-cells = <1>;
236bc011dfaSTakeshi Kihara			#size-cells = <0>;
237bc011dfaSTakeshi Kihara			compatible = "renesas,i2c-r8a77990",
238bc011dfaSTakeshi Kihara				     "renesas,rcar-gen3-i2c";
239bc011dfaSTakeshi Kihara			reg = <0 0xe6510000 0 0x40>;
240bc011dfaSTakeshi Kihara			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
241bc011dfaSTakeshi Kihara			clocks = <&cpg CPG_MOD 929>;
242bc011dfaSTakeshi Kihara			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
243bc011dfaSTakeshi Kihara			resets = <&cpg 929>;
244bc011dfaSTakeshi Kihara			i2c-scl-internal-delay-ns = <6>;
245bc011dfaSTakeshi Kihara			status = "disabled";
246bc011dfaSTakeshi Kihara		};
247bc011dfaSTakeshi Kihara
248bc011dfaSTakeshi Kihara		i2c3: i2c@e66d0000 {
249bc011dfaSTakeshi Kihara			#address-cells = <1>;
250bc011dfaSTakeshi Kihara			#size-cells = <0>;
251bc011dfaSTakeshi Kihara			compatible = "renesas,i2c-r8a77990",
252bc011dfaSTakeshi Kihara				     "renesas,rcar-gen3-i2c";
253bc011dfaSTakeshi Kihara			reg = <0 0xe66d0000 0 0x40>;
254bc011dfaSTakeshi Kihara			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
255bc011dfaSTakeshi Kihara			clocks = <&cpg CPG_MOD 928>;
256bc011dfaSTakeshi Kihara			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
257bc011dfaSTakeshi Kihara			resets = <&cpg 928>;
258bc011dfaSTakeshi Kihara			i2c-scl-internal-delay-ns = <110>;
259bc011dfaSTakeshi Kihara			status = "disabled";
260bc011dfaSTakeshi Kihara		};
261bc011dfaSTakeshi Kihara
262bc011dfaSTakeshi Kihara		i2c4: i2c@e66d8000 {
263bc011dfaSTakeshi Kihara			#address-cells = <1>;
264bc011dfaSTakeshi Kihara			#size-cells = <0>;
265bc011dfaSTakeshi Kihara			compatible = "renesas,i2c-r8a77990",
266bc011dfaSTakeshi Kihara				     "renesas,rcar-gen3-i2c";
267bc011dfaSTakeshi Kihara			reg = <0 0xe66d8000 0 0x40>;
268bc011dfaSTakeshi Kihara			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
269bc011dfaSTakeshi Kihara			clocks = <&cpg CPG_MOD 927>;
270bc011dfaSTakeshi Kihara			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
271bc011dfaSTakeshi Kihara			resets = <&cpg 927>;
272bc011dfaSTakeshi Kihara			i2c-scl-internal-delay-ns = <6>;
273bc011dfaSTakeshi Kihara			status = "disabled";
274bc011dfaSTakeshi Kihara		};
275bc011dfaSTakeshi Kihara
276bc011dfaSTakeshi Kihara		i2c5: i2c@e66e0000 {
277bc011dfaSTakeshi Kihara			#address-cells = <1>;
278bc011dfaSTakeshi Kihara			#size-cells = <0>;
279bc011dfaSTakeshi Kihara			compatible = "renesas,i2c-r8a77990",
280bc011dfaSTakeshi Kihara				     "renesas,rcar-gen3-i2c";
281bc011dfaSTakeshi Kihara			reg = <0 0xe66e0000 0 0x40>;
282bc011dfaSTakeshi Kihara			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
283bc011dfaSTakeshi Kihara			clocks = <&cpg CPG_MOD 919>;
284bc011dfaSTakeshi Kihara			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
285bc011dfaSTakeshi Kihara			resets = <&cpg 919>;
286bc011dfaSTakeshi Kihara			i2c-scl-internal-delay-ns = <6>;
287bc011dfaSTakeshi Kihara			status = "disabled";
288bc011dfaSTakeshi Kihara		};
289bc011dfaSTakeshi Kihara
290bc011dfaSTakeshi Kihara		i2c6: i2c@e66e8000 {
291bc011dfaSTakeshi Kihara			#address-cells = <1>;
292bc011dfaSTakeshi Kihara			#size-cells = <0>;
293bc011dfaSTakeshi Kihara			compatible = "renesas,i2c-r8a77990",
294bc011dfaSTakeshi Kihara				     "renesas,rcar-gen3-i2c";
295bc011dfaSTakeshi Kihara			reg = <0 0xe66e8000 0 0x40>;
296bc011dfaSTakeshi Kihara			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
297bc011dfaSTakeshi Kihara			clocks = <&cpg CPG_MOD 918>;
298bc011dfaSTakeshi Kihara			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
299bc011dfaSTakeshi Kihara			resets = <&cpg 918>;
300bc011dfaSTakeshi Kihara			i2c-scl-internal-delay-ns = <6>;
301bc011dfaSTakeshi Kihara			status = "disabled";
302bc011dfaSTakeshi Kihara		};
303bc011dfaSTakeshi Kihara
304bc011dfaSTakeshi Kihara		i2c7: i2c@e6690000 {
305bc011dfaSTakeshi Kihara			#address-cells = <1>;
306bc011dfaSTakeshi Kihara			#size-cells = <0>;
307bc011dfaSTakeshi Kihara			compatible = "renesas,i2c-r8a77990",
308bc011dfaSTakeshi Kihara				     "renesas,rcar-gen3-i2c";
309bc011dfaSTakeshi Kihara			reg = <0 0xe6690000 0 0x40>;
310bc011dfaSTakeshi Kihara			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
311bc011dfaSTakeshi Kihara			clocks = <&cpg CPG_MOD 1003>;
312bc011dfaSTakeshi Kihara			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
313bc011dfaSTakeshi Kihara			resets = <&cpg 1003>;
314bc011dfaSTakeshi Kihara			i2c-scl-internal-delay-ns = <6>;
315bc011dfaSTakeshi Kihara			status = "disabled";
316bc011dfaSTakeshi Kihara		};
317bc011dfaSTakeshi Kihara
3184ab0df33SYoshihiro Shimoda		pfc: pin-controller@e6060000 {
3194ab0df33SYoshihiro Shimoda			compatible = "renesas,pfc-r8a77990";
3204ab0df33SYoshihiro Shimoda			reg = <0 0xe6060000 0 0x508>;
3214ab0df33SYoshihiro Shimoda		};
3224ab0df33SYoshihiro Shimoda
323f37a7767SYoshihiro Shimoda		cpg: clock-controller@e6150000 {
324f37a7767SYoshihiro Shimoda			compatible = "renesas,r8a77990-cpg-mssr";
325f37a7767SYoshihiro Shimoda			reg = <0 0xe6150000 0 0x1000>;
326f37a7767SYoshihiro Shimoda			clocks = <&extal_clk>;
327f37a7767SYoshihiro Shimoda			clock-names = "extal";
328f37a7767SYoshihiro Shimoda			#clock-cells = <2>;
329f37a7767SYoshihiro Shimoda			#power-domain-cells = <0>;
330f37a7767SYoshihiro Shimoda			#reset-cells = <1>;
331f37a7767SYoshihiro Shimoda		};
332f37a7767SYoshihiro Shimoda
333f37a7767SYoshihiro Shimoda		rst: reset-controller@e6160000 {
334f37a7767SYoshihiro Shimoda			compatible = "renesas,r8a77990-rst";
335f37a7767SYoshihiro Shimoda			reg = <0 0xe6160000 0 0x0200>;
336f37a7767SYoshihiro Shimoda		};
337f37a7767SYoshihiro Shimoda
338f37a7767SYoshihiro Shimoda		sysc: system-controller@e6180000 {
339f37a7767SYoshihiro Shimoda			compatible = "renesas,r8a77990-sysc";
340f37a7767SYoshihiro Shimoda			reg = <0 0xe6180000 0 0x0400>;
341f37a7767SYoshihiro Shimoda			#power-domain-cells = <1>;
342f37a7767SYoshihiro Shimoda		};
343f37a7767SYoshihiro Shimoda
3440c793a02STakeshi Kihara		intc_ex: interrupt-controller@e61c0000 {
3450c793a02STakeshi Kihara			compatible = "renesas,intc-ex-r8a77990", "renesas,irqc";
3460c793a02STakeshi Kihara			#interrupt-cells = <2>;
3470c793a02STakeshi Kihara			interrupt-controller;
3480c793a02STakeshi Kihara			reg = <0 0xe61c0000 0 0x200>;
3490c793a02STakeshi Kihara			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
3500c793a02STakeshi Kihara				      GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
3510c793a02STakeshi Kihara				      GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
3520c793a02STakeshi Kihara				      GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
3530c793a02STakeshi Kihara				      GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
3540c793a02STakeshi Kihara				      GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
3550c793a02STakeshi Kihara			clocks = <&cpg CPG_MOD 407>;
3560c793a02STakeshi Kihara			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
3570c793a02STakeshi Kihara			resets = <&cpg 407>;
3580c793a02STakeshi Kihara		};
3590c793a02STakeshi Kihara
360*5c6479d9SYoshihiro Shimoda		hsusb: usb@e6590000 {
361*5c6479d9SYoshihiro Shimoda			compatible = "renesas,usbhs-r8a77990",
362*5c6479d9SYoshihiro Shimoda				     "renesas,rcar-gen3-usbhs";
363*5c6479d9SYoshihiro Shimoda			reg = <0 0xe6590000 0 0x200>;
364*5c6479d9SYoshihiro Shimoda			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
365*5c6479d9SYoshihiro Shimoda			clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
366*5c6479d9SYoshihiro Shimoda			dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
367*5c6479d9SYoshihiro Shimoda			       <&usb_dmac1 0>, <&usb_dmac1 1>;
368*5c6479d9SYoshihiro Shimoda			dma-names = "ch0", "ch1", "ch2", "ch3";
369*5c6479d9SYoshihiro Shimoda			renesas,buswait = <11>;
370*5c6479d9SYoshihiro Shimoda			phys = <&usb2_phy0>;
371*5c6479d9SYoshihiro Shimoda			phy-names = "usb";
372*5c6479d9SYoshihiro Shimoda			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
373*5c6479d9SYoshihiro Shimoda			resets = <&cpg 704>, <&cpg 703>;
374*5c6479d9SYoshihiro Shimoda			status = "disabled";
375*5c6479d9SYoshihiro Shimoda		};
376*5c6479d9SYoshihiro Shimoda
377*5c6479d9SYoshihiro Shimoda		usb_dmac0: dma-controller@e65a0000 {
378*5c6479d9SYoshihiro Shimoda			compatible = "renesas,r8a77990-usb-dmac",
379*5c6479d9SYoshihiro Shimoda				     "renesas,usb-dmac";
380*5c6479d9SYoshihiro Shimoda			reg = <0 0xe65a0000 0 0x100>;
381*5c6479d9SYoshihiro Shimoda			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
382*5c6479d9SYoshihiro Shimoda				      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
383*5c6479d9SYoshihiro Shimoda			interrupt-names = "ch0", "ch1";
384*5c6479d9SYoshihiro Shimoda			clocks = <&cpg CPG_MOD 330>;
385*5c6479d9SYoshihiro Shimoda			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
386*5c6479d9SYoshihiro Shimoda			resets = <&cpg 330>;
387*5c6479d9SYoshihiro Shimoda			#dma-cells = <1>;
388*5c6479d9SYoshihiro Shimoda			dma-channels = <2>;
389*5c6479d9SYoshihiro Shimoda		};
390*5c6479d9SYoshihiro Shimoda
391*5c6479d9SYoshihiro Shimoda		usb_dmac1: dma-controller@e65b0000 {
392*5c6479d9SYoshihiro Shimoda			compatible = "renesas,r8a77990-usb-dmac",
393*5c6479d9SYoshihiro Shimoda				     "renesas,usb-dmac";
394*5c6479d9SYoshihiro Shimoda			reg = <0 0xe65b0000 0 0x100>;
395*5c6479d9SYoshihiro Shimoda			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
396*5c6479d9SYoshihiro Shimoda				      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
397*5c6479d9SYoshihiro Shimoda			interrupt-names = "ch0", "ch1";
398*5c6479d9SYoshihiro Shimoda			clocks = <&cpg CPG_MOD 331>;
399*5c6479d9SYoshihiro Shimoda			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
400*5c6479d9SYoshihiro Shimoda			resets = <&cpg 331>;
401*5c6479d9SYoshihiro Shimoda			#dma-cells = <1>;
402*5c6479d9SYoshihiro Shimoda			dma-channels = <2>;
403*5c6479d9SYoshihiro Shimoda		};
404*5c6479d9SYoshihiro Shimoda
4053943e896STakeshi Kihara		dmac0: dma-controller@e6700000 {
4063943e896STakeshi Kihara			compatible = "renesas,dmac-r8a77990",
4073943e896STakeshi Kihara				     "renesas,rcar-dmac";
4083943e896STakeshi Kihara			reg = <0 0xe6700000 0 0x10000>;
4093943e896STakeshi Kihara			interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
4103943e896STakeshi Kihara				      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
4113943e896STakeshi Kihara				      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
4123943e896STakeshi Kihara				      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
4133943e896STakeshi Kihara				      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
4143943e896STakeshi Kihara				      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
4153943e896STakeshi Kihara				      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
4163943e896STakeshi Kihara				      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
4173943e896STakeshi Kihara				      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
4183943e896STakeshi Kihara				      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
4193943e896STakeshi Kihara				      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
4203943e896STakeshi Kihara				      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
4213943e896STakeshi Kihara				      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
4223943e896STakeshi Kihara				      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
4233943e896STakeshi Kihara				      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
4243943e896STakeshi Kihara				      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
4253943e896STakeshi Kihara				      GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
4263943e896STakeshi Kihara			interrupt-names = "error",
4273943e896STakeshi Kihara					"ch0", "ch1", "ch2", "ch3",
4283943e896STakeshi Kihara					"ch4", "ch5", "ch6", "ch7",
4293943e896STakeshi Kihara					"ch8", "ch9", "ch10", "ch11",
4303943e896STakeshi Kihara					"ch12", "ch13", "ch14", "ch15";
4313943e896STakeshi Kihara			clocks = <&cpg CPG_MOD 219>;
4323943e896STakeshi Kihara			clock-names = "fck";
4333943e896STakeshi Kihara			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
4343943e896STakeshi Kihara			resets = <&cpg 219>;
4353943e896STakeshi Kihara			#dma-cells = <1>;
4363943e896STakeshi Kihara			dma-channels = <16>;
437f0f9f7a6SMagnus Damm			iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
438f0f9f7a6SMagnus Damm			       <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
439f0f9f7a6SMagnus Damm			       <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
440f0f9f7a6SMagnus Damm			       <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
441f0f9f7a6SMagnus Damm			       <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
442f0f9f7a6SMagnus Damm			       <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
443f0f9f7a6SMagnus Damm			       <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
444f0f9f7a6SMagnus Damm			       <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
4453943e896STakeshi Kihara		};
4463943e896STakeshi Kihara
4473943e896STakeshi Kihara		dmac1: dma-controller@e7300000 {
4483943e896STakeshi Kihara			compatible = "renesas,dmac-r8a77990",
4493943e896STakeshi Kihara				     "renesas,rcar-dmac";
4503943e896STakeshi Kihara			reg = <0 0xe7300000 0 0x10000>;
4513943e896STakeshi Kihara			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
4523943e896STakeshi Kihara				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
4533943e896STakeshi Kihara				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
4543943e896STakeshi Kihara				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
4553943e896STakeshi Kihara				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
4563943e896STakeshi Kihara				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
4573943e896STakeshi Kihara				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
4583943e896STakeshi Kihara				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
4593943e896STakeshi Kihara				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
4603943e896STakeshi Kihara				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
4613943e896STakeshi Kihara				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
4623943e896STakeshi Kihara				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
4633943e896STakeshi Kihara				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
4643943e896STakeshi Kihara				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
4653943e896STakeshi Kihara				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
4663943e896STakeshi Kihara				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
4673943e896STakeshi Kihara				      GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
4683943e896STakeshi Kihara			interrupt-names = "error",
4693943e896STakeshi Kihara					"ch0", "ch1", "ch2", "ch3",
4703943e896STakeshi Kihara					"ch4", "ch5", "ch6", "ch7",
4713943e896STakeshi Kihara					"ch8", "ch9", "ch10", "ch11",
4723943e896STakeshi Kihara					"ch12", "ch13", "ch14", "ch15";
4733943e896STakeshi Kihara			clocks = <&cpg CPG_MOD 218>;
4743943e896STakeshi Kihara			clock-names = "fck";
4753943e896STakeshi Kihara			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
4763943e896STakeshi Kihara			resets = <&cpg 218>;
4773943e896STakeshi Kihara			#dma-cells = <1>;
4783943e896STakeshi Kihara			dma-channels = <16>;
479f0f9f7a6SMagnus Damm			iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
480f0f9f7a6SMagnus Damm			       <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
481f0f9f7a6SMagnus Damm			       <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
482f0f9f7a6SMagnus Damm			       <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
483f0f9f7a6SMagnus Damm			       <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
484f0f9f7a6SMagnus Damm			       <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
485f0f9f7a6SMagnus Damm			       <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
486f0f9f7a6SMagnus Damm			       <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
4873943e896STakeshi Kihara		};
4883943e896STakeshi Kihara
4893943e896STakeshi Kihara		dmac2: dma-controller@e7310000 {
4903943e896STakeshi Kihara			compatible = "renesas,dmac-r8a77990",
4913943e896STakeshi Kihara				     "renesas,rcar-dmac";
4923943e896STakeshi Kihara			reg = <0 0xe7310000 0 0x10000>;
4933943e896STakeshi Kihara			interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
4943943e896STakeshi Kihara				      GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
4953943e896STakeshi Kihara				      GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
4963943e896STakeshi Kihara				      GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
4973943e896STakeshi Kihara				      GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
4983943e896STakeshi Kihara				      GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
4993943e896STakeshi Kihara				      GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
5003943e896STakeshi Kihara				      GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
5013943e896STakeshi Kihara				      GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
5023943e896STakeshi Kihara				      GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
5033943e896STakeshi Kihara				      GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
5043943e896STakeshi Kihara				      GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
5053943e896STakeshi Kihara				      GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
5063943e896STakeshi Kihara				      GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
5073943e896STakeshi Kihara				      GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
5083943e896STakeshi Kihara				      GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
5093943e896STakeshi Kihara				      GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
5103943e896STakeshi Kihara			interrupt-names = "error",
5113943e896STakeshi Kihara					"ch0", "ch1", "ch2", "ch3",
5123943e896STakeshi Kihara					"ch4", "ch5", "ch6", "ch7",
5133943e896STakeshi Kihara					"ch8", "ch9", "ch10", "ch11",
5143943e896STakeshi Kihara					"ch12", "ch13", "ch14", "ch15";
5153943e896STakeshi Kihara			clocks = <&cpg CPG_MOD 217>;
5163943e896STakeshi Kihara			clock-names = "fck";
5173943e896STakeshi Kihara			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
5183943e896STakeshi Kihara			resets = <&cpg 217>;
5193943e896STakeshi Kihara			#dma-cells = <1>;
5203943e896STakeshi Kihara			dma-channels = <16>;
521f0f9f7a6SMagnus Damm			iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
522f0f9f7a6SMagnus Damm			       <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
523f0f9f7a6SMagnus Damm			       <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
524f0f9f7a6SMagnus Damm			       <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
525f0f9f7a6SMagnus Damm			       <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
526f0f9f7a6SMagnus Damm			       <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
527f0f9f7a6SMagnus Damm			       <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
528f0f9f7a6SMagnus Damm			       <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
5293943e896STakeshi Kihara		};
5303943e896STakeshi Kihara
53155697cbbSMagnus Damm		ipmmu_ds0: mmu@e6740000 {
53255697cbbSMagnus Damm			compatible = "renesas,ipmmu-r8a77990";
53355697cbbSMagnus Damm			reg = <0 0xe6740000 0 0x1000>;
53455697cbbSMagnus Damm			renesas,ipmmu-main = <&ipmmu_mm 0>;
53555697cbbSMagnus Damm			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
53655697cbbSMagnus Damm			#iommu-cells = <1>;
53755697cbbSMagnus Damm		};
53855697cbbSMagnus Damm
53955697cbbSMagnus Damm		ipmmu_ds1: mmu@e7740000 {
54055697cbbSMagnus Damm			compatible = "renesas,ipmmu-r8a77990";
54155697cbbSMagnus Damm			reg = <0 0xe7740000 0 0x1000>;
54255697cbbSMagnus Damm			renesas,ipmmu-main = <&ipmmu_mm 1>;
54355697cbbSMagnus Damm			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
54455697cbbSMagnus Damm			#iommu-cells = <1>;
54555697cbbSMagnus Damm		};
54655697cbbSMagnus Damm
54755697cbbSMagnus Damm		ipmmu_hc: mmu@e6570000 {
54855697cbbSMagnus Damm			compatible = "renesas,ipmmu-r8a77990";
54955697cbbSMagnus Damm			reg = <0 0xe6570000 0 0x1000>;
55055697cbbSMagnus Damm			renesas,ipmmu-main = <&ipmmu_mm 2>;
55155697cbbSMagnus Damm			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
55255697cbbSMagnus Damm			#iommu-cells = <1>;
55355697cbbSMagnus Damm		};
55455697cbbSMagnus Damm
55555697cbbSMagnus Damm		ipmmu_mm: mmu@e67b0000 {
55655697cbbSMagnus Damm			compatible = "renesas,ipmmu-r8a77990";
55755697cbbSMagnus Damm			reg = <0 0xe67b0000 0 0x1000>;
55855697cbbSMagnus Damm			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
55955697cbbSMagnus Damm				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
56055697cbbSMagnus Damm			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
56155697cbbSMagnus Damm			#iommu-cells = <1>;
56255697cbbSMagnus Damm		};
56355697cbbSMagnus Damm
56455697cbbSMagnus Damm		ipmmu_mp: mmu@ec670000 {
56555697cbbSMagnus Damm			compatible = "renesas,ipmmu-r8a77990";
56655697cbbSMagnus Damm			reg = <0 0xec670000 0 0x1000>;
56755697cbbSMagnus Damm			renesas,ipmmu-main = <&ipmmu_mm 4>;
56855697cbbSMagnus Damm			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
56955697cbbSMagnus Damm			#iommu-cells = <1>;
57055697cbbSMagnus Damm		};
57155697cbbSMagnus Damm
57255697cbbSMagnus Damm		ipmmu_pv0: mmu@fd800000 {
57355697cbbSMagnus Damm			compatible = "renesas,ipmmu-r8a77990";
57455697cbbSMagnus Damm			reg = <0 0xfd800000 0 0x1000>;
57555697cbbSMagnus Damm			renesas,ipmmu-main = <&ipmmu_mm 6>;
57655697cbbSMagnus Damm			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
57755697cbbSMagnus Damm			#iommu-cells = <1>;
57855697cbbSMagnus Damm		};
57955697cbbSMagnus Damm
58055697cbbSMagnus Damm		ipmmu_rt: mmu@ffc80000 {
58155697cbbSMagnus Damm			compatible = "renesas,ipmmu-r8a77990";
58255697cbbSMagnus Damm			reg = <0 0xffc80000 0 0x1000>;
58355697cbbSMagnus Damm			renesas,ipmmu-main = <&ipmmu_mm 10>;
58455697cbbSMagnus Damm			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
58555697cbbSMagnus Damm			#iommu-cells = <1>;
58655697cbbSMagnus Damm		};
58755697cbbSMagnus Damm
58855697cbbSMagnus Damm		ipmmu_vc0: mmu@fe6b0000 {
58955697cbbSMagnus Damm			compatible = "renesas,ipmmu-r8a77990";
59055697cbbSMagnus Damm			reg = <0 0xfe6b0000 0 0x1000>;
59155697cbbSMagnus Damm			renesas,ipmmu-main = <&ipmmu_mm 12>;
59255697cbbSMagnus Damm			power-domains = <&sysc R8A77990_PD_A3VC>;
59355697cbbSMagnus Damm			#iommu-cells = <1>;
59455697cbbSMagnus Damm		};
59555697cbbSMagnus Damm
59655697cbbSMagnus Damm		ipmmu_vi0: mmu@febd0000 {
59755697cbbSMagnus Damm			compatible = "renesas,ipmmu-r8a77990";
59855697cbbSMagnus Damm			reg = <0 0xfebd0000 0 0x1000>;
59955697cbbSMagnus Damm			renesas,ipmmu-main = <&ipmmu_mm 14>;
60055697cbbSMagnus Damm			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
60155697cbbSMagnus Damm			#iommu-cells = <1>;
60255697cbbSMagnus Damm		};
60355697cbbSMagnus Damm
60455697cbbSMagnus Damm		ipmmu_vp0: mmu@fe990000 {
60555697cbbSMagnus Damm			compatible = "renesas,ipmmu-r8a77990";
60655697cbbSMagnus Damm			reg = <0 0xfe990000 0 0x1000>;
60755697cbbSMagnus Damm			renesas,ipmmu-main = <&ipmmu_mm 16>;
60855697cbbSMagnus Damm			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
60955697cbbSMagnus Damm			#iommu-cells = <1>;
61055697cbbSMagnus Damm		};
61155697cbbSMagnus Damm
612913a78b5SYoshihiro Shimoda		avb: ethernet@e6800000 {
613913a78b5SYoshihiro Shimoda			compatible = "renesas,etheravb-r8a77990",
614913a78b5SYoshihiro Shimoda				     "renesas,etheravb-rcar-gen3";
6154b03df5fSGeert Uytterhoeven			reg = <0 0xe6800000 0 0x800>;
616913a78b5SYoshihiro Shimoda			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
617913a78b5SYoshihiro Shimoda				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
618913a78b5SYoshihiro Shimoda				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
619913a78b5SYoshihiro Shimoda				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
620913a78b5SYoshihiro Shimoda				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
621913a78b5SYoshihiro Shimoda				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
622913a78b5SYoshihiro Shimoda				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
623913a78b5SYoshihiro Shimoda				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
624913a78b5SYoshihiro Shimoda				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
625913a78b5SYoshihiro Shimoda				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
626913a78b5SYoshihiro Shimoda				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
627913a78b5SYoshihiro Shimoda				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
628913a78b5SYoshihiro Shimoda				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
629913a78b5SYoshihiro Shimoda				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
630913a78b5SYoshihiro Shimoda				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
631913a78b5SYoshihiro Shimoda				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
632913a78b5SYoshihiro Shimoda				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
633913a78b5SYoshihiro Shimoda				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
634913a78b5SYoshihiro Shimoda				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
635913a78b5SYoshihiro Shimoda				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
636913a78b5SYoshihiro Shimoda				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
637913a78b5SYoshihiro Shimoda				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
638913a78b5SYoshihiro Shimoda				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
639913a78b5SYoshihiro Shimoda				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
640913a78b5SYoshihiro Shimoda				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
641913a78b5SYoshihiro Shimoda			interrupt-names = "ch0", "ch1", "ch2", "ch3",
642913a78b5SYoshihiro Shimoda					  "ch4", "ch5", "ch6", "ch7",
643913a78b5SYoshihiro Shimoda					  "ch8", "ch9", "ch10", "ch11",
644913a78b5SYoshihiro Shimoda					  "ch12", "ch13", "ch14", "ch15",
645913a78b5SYoshihiro Shimoda					  "ch16", "ch17", "ch18", "ch19",
646913a78b5SYoshihiro Shimoda					  "ch20", "ch21", "ch22", "ch23",
647913a78b5SYoshihiro Shimoda					  "ch24";
648913a78b5SYoshihiro Shimoda			clocks = <&cpg CPG_MOD 812>;
64983e7d2ecSGeert Uytterhoeven			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
650913a78b5SYoshihiro Shimoda			resets = <&cpg 812>;
651913a78b5SYoshihiro Shimoda			phy-mode = "rgmii";
65243021275SMagnus Damm			iommus = <&ipmmu_ds0 16>;
653913a78b5SYoshihiro Shimoda			#address-cells = <1>;
654913a78b5SYoshihiro Shimoda			#size-cells = <0>;
655913a78b5SYoshihiro Shimoda			status = "disabled";
656913a78b5SYoshihiro Shimoda		};
657913a78b5SYoshihiro Shimoda
65818048556SYoshihiro Shimoda		pwm0: pwm@e6e30000 {
65918048556SYoshihiro Shimoda			compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
66018048556SYoshihiro Shimoda			reg = <0 0xe6e30000 0 0x8>;
66118048556SYoshihiro Shimoda			clocks = <&cpg CPG_MOD 523>;
66218048556SYoshihiro Shimoda			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
66318048556SYoshihiro Shimoda			resets = <&cpg 523>;
66418048556SYoshihiro Shimoda			#pwm-cells = <2>;
66518048556SYoshihiro Shimoda			status = "disabled";
66618048556SYoshihiro Shimoda		};
66718048556SYoshihiro Shimoda
66818048556SYoshihiro Shimoda		pwm1: pwm@e6e31000 {
66918048556SYoshihiro Shimoda			compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
67018048556SYoshihiro Shimoda			reg = <0 0xe6e31000 0 0x8>;
67118048556SYoshihiro Shimoda			clocks = <&cpg CPG_MOD 523>;
67218048556SYoshihiro Shimoda			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
67318048556SYoshihiro Shimoda			resets = <&cpg 523>;
67418048556SYoshihiro Shimoda			#pwm-cells = <2>;
67518048556SYoshihiro Shimoda			status = "disabled";
67618048556SYoshihiro Shimoda		};
67718048556SYoshihiro Shimoda
67818048556SYoshihiro Shimoda		pwm2: pwm@e6e32000 {
67918048556SYoshihiro Shimoda			compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
68018048556SYoshihiro Shimoda			reg = <0 0xe6e32000 0 0x8>;
68118048556SYoshihiro Shimoda			clocks = <&cpg CPG_MOD 523>;
68218048556SYoshihiro Shimoda			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
68318048556SYoshihiro Shimoda			resets = <&cpg 523>;
68418048556SYoshihiro Shimoda			#pwm-cells = <2>;
68518048556SYoshihiro Shimoda			status = "disabled";
68618048556SYoshihiro Shimoda		};
68718048556SYoshihiro Shimoda
68818048556SYoshihiro Shimoda		pwm3: pwm@e6e33000 {
68918048556SYoshihiro Shimoda			compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
69018048556SYoshihiro Shimoda			reg = <0 0xe6e33000 0 0x8>;
69118048556SYoshihiro Shimoda			clocks = <&cpg CPG_MOD 523>;
69218048556SYoshihiro Shimoda			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
69318048556SYoshihiro Shimoda			resets = <&cpg 523>;
69418048556SYoshihiro Shimoda			#pwm-cells = <2>;
69518048556SYoshihiro Shimoda			status = "disabled";
69618048556SYoshihiro Shimoda		};
69718048556SYoshihiro Shimoda
69818048556SYoshihiro Shimoda		pwm4: pwm@e6e34000 {
69918048556SYoshihiro Shimoda			compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
70018048556SYoshihiro Shimoda			reg = <0 0xe6e34000 0 0x8>;
70118048556SYoshihiro Shimoda			clocks = <&cpg CPG_MOD 523>;
70218048556SYoshihiro Shimoda			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
70318048556SYoshihiro Shimoda			resets = <&cpg 523>;
70418048556SYoshihiro Shimoda			#pwm-cells = <2>;
70518048556SYoshihiro Shimoda			status = "disabled";
70618048556SYoshihiro Shimoda		};
70718048556SYoshihiro Shimoda
70818048556SYoshihiro Shimoda		pwm5: pwm@e6e35000 {
70918048556SYoshihiro Shimoda			compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
71018048556SYoshihiro Shimoda			reg = <0 0xe6e35000 0 0x8>;
71118048556SYoshihiro Shimoda			clocks = <&cpg CPG_MOD 523>;
71218048556SYoshihiro Shimoda			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
71318048556SYoshihiro Shimoda			resets = <&cpg 523>;
71418048556SYoshihiro Shimoda			#pwm-cells = <2>;
71518048556SYoshihiro Shimoda			status = "disabled";
71618048556SYoshihiro Shimoda		};
71718048556SYoshihiro Shimoda
71818048556SYoshihiro Shimoda		pwm6: pwm@e6e36000 {
71918048556SYoshihiro Shimoda			compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
72018048556SYoshihiro Shimoda			reg = <0 0xe6e36000 0 0x8>;
72118048556SYoshihiro Shimoda			clocks = <&cpg CPG_MOD 523>;
72218048556SYoshihiro Shimoda			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
72318048556SYoshihiro Shimoda			resets = <&cpg 523>;
72418048556SYoshihiro Shimoda			#pwm-cells = <2>;
72518048556SYoshihiro Shimoda			status = "disabled";
72618048556SYoshihiro Shimoda		};
72718048556SYoshihiro Shimoda
728a5ebe5e4STakeshi Kihara		scif0: serial@e6e60000 {
729a5ebe5e4STakeshi Kihara			compatible = "renesas,scif-r8a77990",
730a5ebe5e4STakeshi Kihara				     "renesas,rcar-gen3-scif", "renesas,scif";
731a5ebe5e4STakeshi Kihara			reg = <0 0xe6e60000 0 64>;
732a5ebe5e4STakeshi Kihara			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
733a5ebe5e4STakeshi Kihara			clocks = <&cpg CPG_MOD 207>,
734a5ebe5e4STakeshi Kihara				 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
735a5ebe5e4STakeshi Kihara				 <&scif_clk>;
736a5ebe5e4STakeshi Kihara			clock-names = "fck", "brg_int", "scif_clk";
737a5ebe5e4STakeshi Kihara			dmas = <&dmac1 0x51>, <&dmac1 0x50>,
738a5ebe5e4STakeshi Kihara			       <&dmac2 0x51>, <&dmac2 0x50>;
739a5ebe5e4STakeshi Kihara			dma-names = "tx", "rx", "tx", "rx";
740a5ebe5e4STakeshi Kihara			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
741a5ebe5e4STakeshi Kihara			resets = <&cpg 207>;
742a5ebe5e4STakeshi Kihara			status = "disabled";
743a5ebe5e4STakeshi Kihara		};
744a5ebe5e4STakeshi Kihara
745a5ebe5e4STakeshi Kihara		scif1: serial@e6e68000 {
746a5ebe5e4STakeshi Kihara			compatible = "renesas,scif-r8a77990",
747a5ebe5e4STakeshi Kihara				     "renesas,rcar-gen3-scif", "renesas,scif";
748a5ebe5e4STakeshi Kihara			reg = <0 0xe6e68000 0 64>;
749a5ebe5e4STakeshi Kihara			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
750a5ebe5e4STakeshi Kihara			clocks = <&cpg CPG_MOD 206>,
751a5ebe5e4STakeshi Kihara				 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
752a5ebe5e4STakeshi Kihara				 <&scif_clk>;
753a5ebe5e4STakeshi Kihara			clock-names = "fck", "brg_int", "scif_clk";
754a5ebe5e4STakeshi Kihara			dmas = <&dmac1 0x53>, <&dmac1 0x52>,
755a5ebe5e4STakeshi Kihara			       <&dmac2 0x53>, <&dmac2 0x52>;
756a5ebe5e4STakeshi Kihara			dma-names = "tx", "rx", "tx", "rx";
757a5ebe5e4STakeshi Kihara			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
758a5ebe5e4STakeshi Kihara			resets = <&cpg 206>;
759a5ebe5e4STakeshi Kihara			status = "disabled";
760a5ebe5e4STakeshi Kihara		};
761a5ebe5e4STakeshi Kihara
762f37a7767SYoshihiro Shimoda		scif2: serial@e6e88000 {
763f37a7767SYoshihiro Shimoda			compatible = "renesas,scif-r8a77990",
764f37a7767SYoshihiro Shimoda				     "renesas,rcar-gen3-scif", "renesas,scif";
765f37a7767SYoshihiro Shimoda			reg = <0 0xe6e88000 0 64>;
766f37a7767SYoshihiro Shimoda			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
767103db9b5STakeshi Kihara			clocks = <&cpg CPG_MOD 310>,
768103db9b5STakeshi Kihara				 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
769103db9b5STakeshi Kihara				 <&scif_clk>;
770103db9b5STakeshi Kihara			clock-names = "fck", "brg_int", "scif_clk";
771103db9b5STakeshi Kihara
77283e7d2ecSGeert Uytterhoeven			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
773f37a7767SYoshihiro Shimoda			resets = <&cpg 310>;
774f37a7767SYoshihiro Shimoda			status = "disabled";
775f37a7767SYoshihiro Shimoda		};
776f37a7767SYoshihiro Shimoda
777a5ebe5e4STakeshi Kihara		scif3: serial@e6c50000 {
778a5ebe5e4STakeshi Kihara			compatible = "renesas,scif-r8a77990",
779a5ebe5e4STakeshi Kihara				     "renesas,rcar-gen3-scif", "renesas,scif";
780a5ebe5e4STakeshi Kihara			reg = <0 0xe6c50000 0 64>;
781a5ebe5e4STakeshi Kihara			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
782a5ebe5e4STakeshi Kihara			clocks = <&cpg CPG_MOD 204>,
783a5ebe5e4STakeshi Kihara				 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
784a5ebe5e4STakeshi Kihara				 <&scif_clk>;
785a5ebe5e4STakeshi Kihara			clock-names = "fck", "brg_int", "scif_clk";
786a5ebe5e4STakeshi Kihara			dmas = <&dmac0 0x57>, <&dmac0 0x56>;
787a5ebe5e4STakeshi Kihara			dma-names = "tx", "rx";
788a5ebe5e4STakeshi Kihara			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
789a5ebe5e4STakeshi Kihara			resets = <&cpg 204>;
790a5ebe5e4STakeshi Kihara			status = "disabled";
791a5ebe5e4STakeshi Kihara		};
792a5ebe5e4STakeshi Kihara
793a5ebe5e4STakeshi Kihara		scif4: serial@e6c40000 {
794a5ebe5e4STakeshi Kihara			compatible = "renesas,scif-r8a77990",
795a5ebe5e4STakeshi Kihara				     "renesas,rcar-gen3-scif", "renesas,scif";
796a5ebe5e4STakeshi Kihara			reg = <0 0xe6c40000 0 64>;
797a5ebe5e4STakeshi Kihara			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
798a5ebe5e4STakeshi Kihara			clocks = <&cpg CPG_MOD 203>,
799a5ebe5e4STakeshi Kihara				 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
800a5ebe5e4STakeshi Kihara				 <&scif_clk>;
801a5ebe5e4STakeshi Kihara			clock-names = "fck", "brg_int", "scif_clk";
802a5ebe5e4STakeshi Kihara			dmas = <&dmac0 0x59>, <&dmac0 0x58>;
803a5ebe5e4STakeshi Kihara			dma-names = "tx", "rx";
804a5ebe5e4STakeshi Kihara			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
805a5ebe5e4STakeshi Kihara			resets = <&cpg 203>;
806a5ebe5e4STakeshi Kihara			status = "disabled";
807a5ebe5e4STakeshi Kihara		};
808a5ebe5e4STakeshi Kihara
809a5ebe5e4STakeshi Kihara		scif5: serial@e6f30000 {
810a5ebe5e4STakeshi Kihara			compatible = "renesas,scif-r8a77990",
811a5ebe5e4STakeshi Kihara				     "renesas,rcar-gen3-scif", "renesas,scif";
812a5ebe5e4STakeshi Kihara			reg = <0 0xe6f30000 0 64>;
813a5ebe5e4STakeshi Kihara			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
814a5ebe5e4STakeshi Kihara			clocks = <&cpg CPG_MOD 202>,
815a5ebe5e4STakeshi Kihara				 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
816a5ebe5e4STakeshi Kihara				 <&scif_clk>;
817a5ebe5e4STakeshi Kihara			clock-names = "fck", "brg_int", "scif_clk";
818a5ebe5e4STakeshi Kihara			dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
819a5ebe5e4STakeshi Kihara			       <&dmac2 0x5b>, <&dmac2 0x5a>;
820a5ebe5e4STakeshi Kihara			dma-names = "tx", "rx", "tx", "rx";
821a5ebe5e4STakeshi Kihara			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
822a5ebe5e4STakeshi Kihara			resets = <&cpg 202>;
823a5ebe5e4STakeshi Kihara			status = "disabled";
824a5ebe5e4STakeshi Kihara		};
825a5ebe5e4STakeshi Kihara
8264b7e3ab1SGeert Uytterhoeven		msiof0: spi@e6e90000 {
8274b7e3ab1SGeert Uytterhoeven			compatible = "renesas,msiof-r8a77990",
8284b7e3ab1SGeert Uytterhoeven				     "renesas,rcar-gen3-msiof";
8294b7e3ab1SGeert Uytterhoeven			reg = <0 0xe6e90000 0 0x0064>;
8304b7e3ab1SGeert Uytterhoeven			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
8314b7e3ab1SGeert Uytterhoeven			clocks = <&cpg CPG_MOD 211>;
83285170420SYoshihiro Kaneko			dmas = <&dmac1 0x41>, <&dmac1 0x40>,
83385170420SYoshihiro Kaneko			       <&dmac2 0x41>, <&dmac2 0x40>;
83485170420SYoshihiro Kaneko			dma-names = "tx", "rx", "tx", "rx";
8354b7e3ab1SGeert Uytterhoeven			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
8364b7e3ab1SGeert Uytterhoeven			resets = <&cpg 211>;
8374b7e3ab1SGeert Uytterhoeven			#address-cells = <1>;
8384b7e3ab1SGeert Uytterhoeven			#size-cells = <0>;
8394b7e3ab1SGeert Uytterhoeven			status = "disabled";
8404b7e3ab1SGeert Uytterhoeven		};
8414b7e3ab1SGeert Uytterhoeven
8424b7e3ab1SGeert Uytterhoeven		msiof1: spi@e6ea0000 {
8434b7e3ab1SGeert Uytterhoeven			compatible = "renesas,msiof-r8a77990",
8444b7e3ab1SGeert Uytterhoeven				     "renesas,rcar-gen3-msiof";
8454b7e3ab1SGeert Uytterhoeven			reg = <0 0xe6ea0000 0 0x0064>;
8464b7e3ab1SGeert Uytterhoeven			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
8474b7e3ab1SGeert Uytterhoeven			clocks = <&cpg CPG_MOD 210>;
84885170420SYoshihiro Kaneko			dmas = <&dmac1 0x43>, <&dmac1 0x42>,
84985170420SYoshihiro Kaneko			       <&dmac2 0x43>, <&dmac2 0x42>;
85085170420SYoshihiro Kaneko			dma-names = "tx", "rx", "tx", "rx";
8514b7e3ab1SGeert Uytterhoeven			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
8524b7e3ab1SGeert Uytterhoeven			resets = <&cpg 210>;
8534b7e3ab1SGeert Uytterhoeven			#address-cells = <1>;
8544b7e3ab1SGeert Uytterhoeven			#size-cells = <0>;
8554b7e3ab1SGeert Uytterhoeven			status = "disabled";
8564b7e3ab1SGeert Uytterhoeven		};
8574b7e3ab1SGeert Uytterhoeven
8584b7e3ab1SGeert Uytterhoeven		msiof2: spi@e6c00000 {
8594b7e3ab1SGeert Uytterhoeven			compatible = "renesas,msiof-r8a77990",
8604b7e3ab1SGeert Uytterhoeven				     "renesas,rcar-gen3-msiof";
8614b7e3ab1SGeert Uytterhoeven			reg = <0 0xe6c00000 0 0x0064>;
8624b7e3ab1SGeert Uytterhoeven			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
8634b7e3ab1SGeert Uytterhoeven			clocks = <&cpg CPG_MOD 209>;
86485170420SYoshihiro Kaneko			dmas = <&dmac0 0x45>, <&dmac0 0x44>;
86585170420SYoshihiro Kaneko			dma-names = "tx", "rx";
8664b7e3ab1SGeert Uytterhoeven			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
8674b7e3ab1SGeert Uytterhoeven			resets = <&cpg 209>;
8684b7e3ab1SGeert Uytterhoeven			#address-cells = <1>;
8694b7e3ab1SGeert Uytterhoeven			#size-cells = <0>;
8704b7e3ab1SGeert Uytterhoeven			status = "disabled";
8714b7e3ab1SGeert Uytterhoeven		};
8724b7e3ab1SGeert Uytterhoeven
8734b7e3ab1SGeert Uytterhoeven		msiof3: spi@e6c10000 {
8744b7e3ab1SGeert Uytterhoeven			compatible = "renesas,msiof-r8a77990",
8754b7e3ab1SGeert Uytterhoeven				     "renesas,rcar-gen3-msiof";
8764b7e3ab1SGeert Uytterhoeven			reg = <0 0xe6c10000 0 0x0064>;
8774b7e3ab1SGeert Uytterhoeven			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
8784b7e3ab1SGeert Uytterhoeven			clocks = <&cpg CPG_MOD 208>;
87985170420SYoshihiro Kaneko			dmas = <&dmac0 0x47>, <&dmac0 0x46>;
88085170420SYoshihiro Kaneko			dma-names = "tx", "rx";
8814b7e3ab1SGeert Uytterhoeven			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
8824b7e3ab1SGeert Uytterhoeven			resets = <&cpg 208>;
8834b7e3ab1SGeert Uytterhoeven			#address-cells = <1>;
8844b7e3ab1SGeert Uytterhoeven			#size-cells = <0>;
8854b7e3ab1SGeert Uytterhoeven			status = "disabled";
8864b7e3ab1SGeert Uytterhoeven		};
8874b7e3ab1SGeert Uytterhoeven
888ec70407aSKoji Matsuoka		vin4: video@e6ef4000 {
889ec70407aSKoji Matsuoka			compatible = "renesas,vin-r8a77990";
890ec70407aSKoji Matsuoka			reg = <0 0xe6ef4000 0 0x1000>;
891ec70407aSKoji Matsuoka			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
892ec70407aSKoji Matsuoka			clocks = <&cpg CPG_MOD 807>;
893ec70407aSKoji Matsuoka			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
894ec70407aSKoji Matsuoka			resets = <&cpg 807>;
895ec70407aSKoji Matsuoka			renesas,id = <4>;
896ec70407aSKoji Matsuoka			status = "disabled";
897ec70407aSKoji Matsuoka
898ec70407aSKoji Matsuoka			ports {
899ec70407aSKoji Matsuoka				#address-cells = <1>;
900ec70407aSKoji Matsuoka				#size-cells = <0>;
901ec70407aSKoji Matsuoka
902ec70407aSKoji Matsuoka				port@1 {
903ec70407aSKoji Matsuoka					reg = <1>;
904ec70407aSKoji Matsuoka
905ec70407aSKoji Matsuoka					vin4csi40: endpoint {
906ec70407aSKoji Matsuoka						remote-endpoint= <&csi40vin4>;
907ec70407aSKoji Matsuoka					};
908ec70407aSKoji Matsuoka				};
909ec70407aSKoji Matsuoka			};
910ec70407aSKoji Matsuoka		};
911ec70407aSKoji Matsuoka
912ec70407aSKoji Matsuoka		vin5: video@e6ef5000 {
913ec70407aSKoji Matsuoka			compatible = "renesas,vin-r8a77990";
914ec70407aSKoji Matsuoka			reg = <0 0xe6ef5000 0 0x1000>;
915ec70407aSKoji Matsuoka			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
916ec70407aSKoji Matsuoka			clocks = <&cpg CPG_MOD 806>;
917ec70407aSKoji Matsuoka			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
918ec70407aSKoji Matsuoka			resets = <&cpg 806>;
919ec70407aSKoji Matsuoka			renesas,id = <5>;
920ec70407aSKoji Matsuoka			status = "disabled";
921ec70407aSKoji Matsuoka
922ec70407aSKoji Matsuoka			ports {
923ec70407aSKoji Matsuoka				#address-cells = <1>;
924ec70407aSKoji Matsuoka				#size-cells = <0>;
925ec70407aSKoji Matsuoka
926ec70407aSKoji Matsuoka				port@1 {
927ec70407aSKoji Matsuoka					reg = <1>;
928ec70407aSKoji Matsuoka
929ec70407aSKoji Matsuoka					vin5csi40: endpoint {
930ec70407aSKoji Matsuoka						remote-endpoint= <&csi40vin5>;
931ec70407aSKoji Matsuoka					};
932ec70407aSKoji Matsuoka				};
933ec70407aSKoji Matsuoka			};
934ec70407aSKoji Matsuoka		};
935ec70407aSKoji Matsuoka
936fe1bc94aSYoshihiro Shimoda		xhci0: usb@ee000000 {
937fe1bc94aSYoshihiro Shimoda			compatible = "renesas,xhci-r8a77990",
938fe1bc94aSYoshihiro Shimoda				     "renesas,rcar-gen3-xhci";
939fe1bc94aSYoshihiro Shimoda			reg = <0 0xee000000 0 0xc00>;
940fe1bc94aSYoshihiro Shimoda			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
941fe1bc94aSYoshihiro Shimoda			clocks = <&cpg CPG_MOD 328>;
942fe1bc94aSYoshihiro Shimoda			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
943fe1bc94aSYoshihiro Shimoda			resets = <&cpg 328>;
944fe1bc94aSYoshihiro Shimoda			status = "disabled";
945fe1bc94aSYoshihiro Shimoda		};
946fe1bc94aSYoshihiro Shimoda
9478dae1d2bSYoshihiro Shimoda		usb3_peri0: usb@ee020000 {
9488dae1d2bSYoshihiro Shimoda			compatible = "renesas,r8a77990-usb3-peri",
9498dae1d2bSYoshihiro Shimoda				     "renesas,rcar-gen3-usb3-peri";
9508dae1d2bSYoshihiro Shimoda			reg = <0 0xee020000 0 0x400>;
9518dae1d2bSYoshihiro Shimoda			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
9528dae1d2bSYoshihiro Shimoda			clocks = <&cpg CPG_MOD 328>;
9538dae1d2bSYoshihiro Shimoda			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
9548dae1d2bSYoshihiro Shimoda			resets = <&cpg 328>;
9558dae1d2bSYoshihiro Shimoda			status = "disabled";
9568dae1d2bSYoshihiro Shimoda		};
9578dae1d2bSYoshihiro Shimoda
9586dd72b4dSYoshihiro Shimoda		ohci0: usb@ee080000 {
9596dd72b4dSYoshihiro Shimoda			compatible = "generic-ohci";
9606dd72b4dSYoshihiro Shimoda			reg = <0 0xee080000 0 0x100>;
9616dd72b4dSYoshihiro Shimoda			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
962737e05bfSYoshihiro Shimoda			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
9636dd72b4dSYoshihiro Shimoda			phys = <&usb2_phy0>;
9646dd72b4dSYoshihiro Shimoda			phy-names = "usb";
96583e7d2ecSGeert Uytterhoeven			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
966737e05bfSYoshihiro Shimoda			resets = <&cpg 703>, <&cpg 704>;
9676dd72b4dSYoshihiro Shimoda			status = "disabled";
9686dd72b4dSYoshihiro Shimoda		};
9696dd72b4dSYoshihiro Shimoda
9706dd72b4dSYoshihiro Shimoda		ehci0: usb@ee080100 {
9716dd72b4dSYoshihiro Shimoda			compatible = "generic-ehci";
9726dd72b4dSYoshihiro Shimoda			reg = <0 0xee080100 0 0x100>;
9736dd72b4dSYoshihiro Shimoda			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
974737e05bfSYoshihiro Shimoda			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
9756dd72b4dSYoshihiro Shimoda			phys = <&usb2_phy0>;
9766dd72b4dSYoshihiro Shimoda			phy-names = "usb";
9776dd72b4dSYoshihiro Shimoda			companion = <&ohci0>;
97883e7d2ecSGeert Uytterhoeven			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
979737e05bfSYoshihiro Shimoda			resets = <&cpg 703>, <&cpg 704>;
9806dd72b4dSYoshihiro Shimoda			status = "disabled";
9816dd72b4dSYoshihiro Shimoda		};
9826dd72b4dSYoshihiro Shimoda
9836dd72b4dSYoshihiro Shimoda		usb2_phy0: usb-phy@ee080200 {
9846dd72b4dSYoshihiro Shimoda			compatible = "renesas,usb2-phy-r8a77990",
9856dd72b4dSYoshihiro Shimoda				     "renesas,rcar-gen3-usb2-phy";
9866dd72b4dSYoshihiro Shimoda			reg = <0 0xee080200 0 0x700>;
9876dd72b4dSYoshihiro Shimoda			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
988737e05bfSYoshihiro Shimoda			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
98983e7d2ecSGeert Uytterhoeven			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
990737e05bfSYoshihiro Shimoda			resets = <&cpg 703>, <&cpg 704>;
9916dd72b4dSYoshihiro Shimoda			#phy-cells = <0>;
9926dd72b4dSYoshihiro Shimoda			status = "disabled";
9936dd72b4dSYoshihiro Shimoda		};
9946dd72b4dSYoshihiro Shimoda
995f37a7767SYoshihiro Shimoda		gic: interrupt-controller@f1010000 {
996f37a7767SYoshihiro Shimoda			compatible = "arm,gic-400";
997f37a7767SYoshihiro Shimoda			#interrupt-cells = <3>;
998f37a7767SYoshihiro Shimoda			#address-cells = <0>;
999f37a7767SYoshihiro Shimoda			interrupt-controller;
1000f37a7767SYoshihiro Shimoda			reg = <0x0 0xf1010000 0 0x1000>,
1001f37a7767SYoshihiro Shimoda			      <0x0 0xf1020000 0 0x20000>,
1002f37a7767SYoshihiro Shimoda			      <0x0 0xf1040000 0 0x20000>,
1003f37a7767SYoshihiro Shimoda			      <0x0 0xf1060000 0 0x20000>;
1004f37a7767SYoshihiro Shimoda			interrupts = <GIC_PPI 9
10057085f5d9SGeert Uytterhoeven					(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
1006f37a7767SYoshihiro Shimoda			clocks = <&cpg CPG_MOD 408>;
1007f37a7767SYoshihiro Shimoda			clock-names = "clk";
100883e7d2ecSGeert Uytterhoeven			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1009f37a7767SYoshihiro Shimoda			resets = <&cpg 408>;
1010f37a7767SYoshihiro Shimoda		};
1011f37a7767SYoshihiro Shimoda
101213ee2bfcSLaurent Pinchart		vspb0: vsp@fe960000 {
101313ee2bfcSLaurent Pinchart			compatible = "renesas,vsp2";
101413ee2bfcSLaurent Pinchart			reg = <0 0xfe960000 0 0x8000>;
101513ee2bfcSLaurent Pinchart			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
101613ee2bfcSLaurent Pinchart			clocks = <&cpg CPG_MOD 626>;
101713ee2bfcSLaurent Pinchart			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
101813ee2bfcSLaurent Pinchart			resets = <&cpg 626>;
101913ee2bfcSLaurent Pinchart			renesas,fcp = <&fcpvb0>;
102013ee2bfcSLaurent Pinchart		};
102113ee2bfcSLaurent Pinchart
102213ee2bfcSLaurent Pinchart		fcpvb0: fcp@fe96f000 {
102313ee2bfcSLaurent Pinchart			compatible = "renesas,fcpv";
102413ee2bfcSLaurent Pinchart			reg = <0 0xfe96f000 0 0x200>;
102513ee2bfcSLaurent Pinchart			clocks = <&cpg CPG_MOD 607>;
102613ee2bfcSLaurent Pinchart			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
102713ee2bfcSLaurent Pinchart			resets = <&cpg 607>;
102813ee2bfcSLaurent Pinchart			iommus = <&ipmmu_vp0 5>;
102913ee2bfcSLaurent Pinchart		};
103013ee2bfcSLaurent Pinchart
103113ee2bfcSLaurent Pinchart		vspi0: vsp@fe9a0000 {
103213ee2bfcSLaurent Pinchart			compatible = "renesas,vsp2";
103313ee2bfcSLaurent Pinchart			reg = <0 0xfe9a0000 0 0x8000>;
103413ee2bfcSLaurent Pinchart			interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
103513ee2bfcSLaurent Pinchart			clocks = <&cpg CPG_MOD 631>;
103613ee2bfcSLaurent Pinchart			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
103713ee2bfcSLaurent Pinchart			resets = <&cpg 631>;
103813ee2bfcSLaurent Pinchart			renesas,fcp = <&fcpvi0>;
103913ee2bfcSLaurent Pinchart		};
104013ee2bfcSLaurent Pinchart
104113ee2bfcSLaurent Pinchart		fcpvi0: fcp@fe9af000 {
104213ee2bfcSLaurent Pinchart			compatible = "renesas,fcpv";
104313ee2bfcSLaurent Pinchart			reg = <0 0xfe9af000 0 0x200>;
104413ee2bfcSLaurent Pinchart			clocks = <&cpg CPG_MOD 611>;
104513ee2bfcSLaurent Pinchart			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
104613ee2bfcSLaurent Pinchart			resets = <&cpg 611>;
104713ee2bfcSLaurent Pinchart			iommus = <&ipmmu_vp0 8>;
104813ee2bfcSLaurent Pinchart		};
104913ee2bfcSLaurent Pinchart
105013ee2bfcSLaurent Pinchart		vspd0: vsp@fea20000 {
105113ee2bfcSLaurent Pinchart			compatible = "renesas,vsp2";
105213ee2bfcSLaurent Pinchart			reg = <0 0xfea20000 0 0x7000>;
105313ee2bfcSLaurent Pinchart			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
105413ee2bfcSLaurent Pinchart			clocks = <&cpg CPG_MOD 623>;
105513ee2bfcSLaurent Pinchart			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
105613ee2bfcSLaurent Pinchart			resets = <&cpg 623>;
105713ee2bfcSLaurent Pinchart			renesas,fcp = <&fcpvd0>;
105813ee2bfcSLaurent Pinchart		};
105913ee2bfcSLaurent Pinchart
106013ee2bfcSLaurent Pinchart		fcpvd0: fcp@fea27000 {
106113ee2bfcSLaurent Pinchart			compatible = "renesas,fcpv";
106213ee2bfcSLaurent Pinchart			reg = <0 0xfea27000 0 0x200>;
106313ee2bfcSLaurent Pinchart			clocks = <&cpg CPG_MOD 603>;
106413ee2bfcSLaurent Pinchart			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
106513ee2bfcSLaurent Pinchart			resets = <&cpg 603>;
106613ee2bfcSLaurent Pinchart			iommus = <&ipmmu_vi0 8>;
106713ee2bfcSLaurent Pinchart		};
106813ee2bfcSLaurent Pinchart
106913ee2bfcSLaurent Pinchart		vspd1: vsp@fea28000 {
107013ee2bfcSLaurent Pinchart			compatible = "renesas,vsp2";
107113ee2bfcSLaurent Pinchart			reg = <0 0xfea28000 0 0x7000>;
107213ee2bfcSLaurent Pinchart			interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
107313ee2bfcSLaurent Pinchart			clocks = <&cpg CPG_MOD 622>;
107413ee2bfcSLaurent Pinchart			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
107513ee2bfcSLaurent Pinchart			resets = <&cpg 622>;
107613ee2bfcSLaurent Pinchart			renesas,fcp = <&fcpvd1>;
107713ee2bfcSLaurent Pinchart		};
107813ee2bfcSLaurent Pinchart
107913ee2bfcSLaurent Pinchart		fcpvd1: fcp@fea2f000 {
108013ee2bfcSLaurent Pinchart			compatible = "renesas,fcpv";
108113ee2bfcSLaurent Pinchart			reg = <0 0xfea2f000 0 0x200>;
108213ee2bfcSLaurent Pinchart			clocks = <&cpg CPG_MOD 602>;
108313ee2bfcSLaurent Pinchart			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
108413ee2bfcSLaurent Pinchart			resets = <&cpg 602>;
108513ee2bfcSLaurent Pinchart			iommus = <&ipmmu_vi0 9>;
108613ee2bfcSLaurent Pinchart		};
108713ee2bfcSLaurent Pinchart
1088ec70407aSKoji Matsuoka		csi40: csi2@feaa0000 {
1089ec70407aSKoji Matsuoka			compatible = "renesas,r8a77990-csi2", "renesas,rcar-gen3-csi2";
1090ec70407aSKoji Matsuoka			reg = <0 0xfeaa0000 0 0x10000>;
1091ec70407aSKoji Matsuoka			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1092ec70407aSKoji Matsuoka			clocks = <&cpg CPG_MOD 716>;
1093ec70407aSKoji Matsuoka			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1094ec70407aSKoji Matsuoka			resets = <&cpg 716>;
1095ec70407aSKoji Matsuoka			status = "disabled";
1096ec70407aSKoji Matsuoka
1097ec70407aSKoji Matsuoka			ports {
1098ec70407aSKoji Matsuoka				#address-cells = <1>;
1099ec70407aSKoji Matsuoka				#size-cells = <0>;
1100ec70407aSKoji Matsuoka
1101ec70407aSKoji Matsuoka				port@1 {
1102ec70407aSKoji Matsuoka					#address-cells = <1>;
1103ec70407aSKoji Matsuoka					#size-cells = <0>;
1104ec70407aSKoji Matsuoka
1105ec70407aSKoji Matsuoka					reg = <1>;
1106ec70407aSKoji Matsuoka
1107ec70407aSKoji Matsuoka					csi40vin4: endpoint@0 {
1108ec70407aSKoji Matsuoka						reg = <0>;
1109ec70407aSKoji Matsuoka						remote-endpoint = <&vin4csi40>;
1110ec70407aSKoji Matsuoka					};
1111ec70407aSKoji Matsuoka					csi40vin5: endpoint@1 {
1112ec70407aSKoji Matsuoka						reg = <1>;
1113ec70407aSKoji Matsuoka						remote-endpoint = <&vin5csi40>;
1114ec70407aSKoji Matsuoka					};
1115ec70407aSKoji Matsuoka				};
1116ec70407aSKoji Matsuoka			};
1117ec70407aSKoji Matsuoka		};
1118ec70407aSKoji Matsuoka
111913ee2bfcSLaurent Pinchart		du: display@feb00000 {
112013ee2bfcSLaurent Pinchart			compatible = "renesas,du-r8a77990";
112113ee2bfcSLaurent Pinchart			reg = <0 0xfeb00000 0 0x80000>;
112213ee2bfcSLaurent Pinchart			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
112313ee2bfcSLaurent Pinchart				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
112413ee2bfcSLaurent Pinchart			clocks = <&cpg CPG_MOD 724>,
112513ee2bfcSLaurent Pinchart				 <&cpg CPG_MOD 723>;
112613ee2bfcSLaurent Pinchart			clock-names = "du.0", "du.1";
112713ee2bfcSLaurent Pinchart			vsps = <&vspd0 0 &vspd1 0>;
112813ee2bfcSLaurent Pinchart			status = "disabled";
112913ee2bfcSLaurent Pinchart
113013ee2bfcSLaurent Pinchart			ports {
113113ee2bfcSLaurent Pinchart				#address-cells = <1>;
113213ee2bfcSLaurent Pinchart				#size-cells = <0>;
113313ee2bfcSLaurent Pinchart
113413ee2bfcSLaurent Pinchart				port@0 {
113513ee2bfcSLaurent Pinchart					reg = <0>;
113613ee2bfcSLaurent Pinchart					du_out_rgb: endpoint {
113713ee2bfcSLaurent Pinchart					};
113813ee2bfcSLaurent Pinchart				};
113913ee2bfcSLaurent Pinchart
114013ee2bfcSLaurent Pinchart				port@1 {
114113ee2bfcSLaurent Pinchart					reg = <1>;
114213ee2bfcSLaurent Pinchart					du_out_lvds0: endpoint {
114313ee2bfcSLaurent Pinchart						remote-endpoint = <&lvds0_in>;
114413ee2bfcSLaurent Pinchart					};
114513ee2bfcSLaurent Pinchart				};
114613ee2bfcSLaurent Pinchart
114713ee2bfcSLaurent Pinchart				port@2 {
114813ee2bfcSLaurent Pinchart					reg = <2>;
114913ee2bfcSLaurent Pinchart					du_out_lvds1: endpoint {
115013ee2bfcSLaurent Pinchart						remote-endpoint = <&lvds1_in>;
115113ee2bfcSLaurent Pinchart					};
115213ee2bfcSLaurent Pinchart				};
115313ee2bfcSLaurent Pinchart			};
115413ee2bfcSLaurent Pinchart		};
115513ee2bfcSLaurent Pinchart
115613ee2bfcSLaurent Pinchart		lvds0: lvds-encoder@feb90000 {
115713ee2bfcSLaurent Pinchart			compatible = "renesas,r8a77990-lvds";
115813ee2bfcSLaurent Pinchart			reg = <0 0xfeb90000 0 0x20>;
115913ee2bfcSLaurent Pinchart			clocks = <&cpg CPG_MOD 727>;
116013ee2bfcSLaurent Pinchart			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
116113ee2bfcSLaurent Pinchart			resets = <&cpg 727>;
116213ee2bfcSLaurent Pinchart			status = "disabled";
116313ee2bfcSLaurent Pinchart
116413ee2bfcSLaurent Pinchart			ports {
116513ee2bfcSLaurent Pinchart				#address-cells = <1>;
116613ee2bfcSLaurent Pinchart				#size-cells = <0>;
116713ee2bfcSLaurent Pinchart
116813ee2bfcSLaurent Pinchart				port@0 {
116913ee2bfcSLaurent Pinchart					reg = <0>;
117013ee2bfcSLaurent Pinchart					lvds0_in: endpoint {
117113ee2bfcSLaurent Pinchart						remote-endpoint = <&du_out_lvds0>;
117213ee2bfcSLaurent Pinchart					};
117313ee2bfcSLaurent Pinchart				};
117413ee2bfcSLaurent Pinchart
117513ee2bfcSLaurent Pinchart				port@1 {
117613ee2bfcSLaurent Pinchart					reg = <1>;
117713ee2bfcSLaurent Pinchart					lvds0_out: endpoint {
117813ee2bfcSLaurent Pinchart					};
117913ee2bfcSLaurent Pinchart				};
118013ee2bfcSLaurent Pinchart			};
118113ee2bfcSLaurent Pinchart		};
118213ee2bfcSLaurent Pinchart
118313ee2bfcSLaurent Pinchart		lvds1: lvds-encoder@feb90100 {
118413ee2bfcSLaurent Pinchart			compatible = "renesas,r8a77990-lvds";
118513ee2bfcSLaurent Pinchart			reg = <0 0xfeb90100 0 0x20>;
118613ee2bfcSLaurent Pinchart			clocks = <&cpg CPG_MOD 727>;
118713ee2bfcSLaurent Pinchart			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
118813ee2bfcSLaurent Pinchart			resets = <&cpg 726>;
118913ee2bfcSLaurent Pinchart			status = "disabled";
119013ee2bfcSLaurent Pinchart
119113ee2bfcSLaurent Pinchart			ports {
119213ee2bfcSLaurent Pinchart				#address-cells = <1>;
119313ee2bfcSLaurent Pinchart				#size-cells = <0>;
119413ee2bfcSLaurent Pinchart
119513ee2bfcSLaurent Pinchart				port@0 {
119613ee2bfcSLaurent Pinchart					reg = <0>;
119713ee2bfcSLaurent Pinchart					lvds1_in: endpoint {
119813ee2bfcSLaurent Pinchart						remote-endpoint = <&du_out_lvds1>;
119913ee2bfcSLaurent Pinchart					};
120013ee2bfcSLaurent Pinchart				};
120113ee2bfcSLaurent Pinchart
120213ee2bfcSLaurent Pinchart				port@1 {
120313ee2bfcSLaurent Pinchart					reg = <1>;
120413ee2bfcSLaurent Pinchart					lvds1_out: endpoint {
120513ee2bfcSLaurent Pinchart					};
120613ee2bfcSLaurent Pinchart				};
120713ee2bfcSLaurent Pinchart			};
120813ee2bfcSLaurent Pinchart		};
120913ee2bfcSLaurent Pinchart
1210f37a7767SYoshihiro Shimoda		prr: chipid@fff00044 {
1211f37a7767SYoshihiro Shimoda			compatible = "renesas,prr";
1212f37a7767SYoshihiro Shimoda			reg = <0 0xfff00044 0 4>;
1213f37a7767SYoshihiro Shimoda		};
1214f37a7767SYoshihiro Shimoda	};
1215f37a7767SYoshihiro Shimoda
1216f37a7767SYoshihiro Shimoda	timer {
1217f37a7767SYoshihiro Shimoda		compatible = "arm,armv8-timer";
12187085f5d9SGeert Uytterhoeven		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
12197085f5d9SGeert Uytterhoeven				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
12207085f5d9SGeert Uytterhoeven				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
12217085f5d9SGeert Uytterhoeven				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
1222f37a7767SYoshihiro Shimoda	};
1223f37a7767SYoshihiro Shimoda};
1224