xref: /linux/scripts/dtc/include-prefixes/arm64/renesas/r8a77990.dtsi (revision 103db9b539567073de2200a8a0a725646610865d)

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Device Tree Source for the R-Car E3 (R8A77990) SoC
 *
 * Copyright (C) 2018 Renesas Electronics Corp.
 */

#include <dt-bindings/clock/r8a77990-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a77990-sysc.h>

/ {
	compatible = "renesas,r8a77990";
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		a53_0: cpu@0 {
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0>;
			device_type = "cpu";
			power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
			next-level-cache = <&L2_CA53>;
			enable-method = "psci";
		};

		a53_1: cpu@1 {
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <1>;
			device_type = "cpu";
			power-domains = <&sysc R8A77990_PD_CA53_CPU1>;
			next-level-cache = <&L2_CA53>;
			enable-method = "psci";
		};

		L2_CA53: cache-controller-0 {
			compatible = "cache";
			power-domains = <&sysc R8A77990_PD_CA53_SCU>;
			cache-unified;
			cache-level = <2>;
		};
	};

	extal_clk: extal {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by the board */
		clock-frequency = <0>;
	};

	pmu_a53 {
		compatible = "arm,cortex-a53-pmu";
		interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
				      <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&a53_0>, <&a53_1>;
	};

	psci {
		compatible = "arm,psci-1.0", "arm,psci-0.2";
		method = "smc";
	};

	/* External SCIF clock - to be overridden by boards that provide it */
	scif_clk: scif {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};

	soc: soc {
		compatible = "simple-bus";
		interrupt-parent = <&gic>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		rwdt: watchdog@e6020000 {
			compatible = "renesas,r8a77990-wdt",
				     "renesas,rcar-gen3-wdt";
			reg = <0 0xe6020000 0 0x0c>;
			clocks = <&cpg CPG_MOD 402>;
			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
			resets = <&cpg 402>;
			status = "disabled";
		};

		gpio0: gpio@e6050000 {
			compatible = "renesas,gpio-r8a77990",
				     "renesas,rcar-gen3-gpio";
			reg = <0 0xe6050000 0 0x50>;
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 0 18>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 912>;
			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
			resets = <&cpg 912>;
		};

		gpio1: gpio@e6051000 {
			compatible = "renesas,gpio-r8a77990",
				     "renesas,rcar-gen3-gpio";
			reg = <0 0xe6051000 0 0x50>;
			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 32 23>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 911>;
			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
			resets = <&cpg 911>;
		};

		gpio2: gpio@e6052000 {
			compatible = "renesas,gpio-r8a77990",
				     "renesas,rcar-gen3-gpio";
			reg = <0 0xe6052000 0 0x50>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 64 26>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 910>;
			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
			resets = <&cpg 910>;
		};

		gpio3: gpio@e6053000 {
			compatible = "renesas,gpio-r8a77990",
				     "renesas,rcar-gen3-gpio";
			reg = <0 0xe6053000 0 0x50>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 96 16>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 909>;
			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
			resets = <&cpg 909>;
		};

		gpio4: gpio@e6054000 {
			compatible = "renesas,gpio-r8a77990",
				     "renesas,rcar-gen3-gpio";
			reg = <0 0xe6054000 0 0x50>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 128 11>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 908>;
			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
			resets = <&cpg 908>;
		};

		gpio5: gpio@e6055000 {
			compatible = "renesas,gpio-r8a77990",
				     "renesas,rcar-gen3-gpio";
			reg = <0 0xe6055000 0 0x50>;
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 160 20>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 907>;
			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
			resets = <&cpg 907>;
		};

		gpio6: gpio@e6055400 {
			compatible = "renesas,gpio-r8a77990",
				     "renesas,rcar-gen3-gpio";
			reg = <0 0xe6055400 0 0x50>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 192 18>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 906>;
			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
			resets = <&cpg 906>;
		};

		pfc: pin-controller@e6060000 {
			compatible = "renesas,pfc-r8a77990";
			reg = <0 0xe6060000 0 0x508>;
		};

		cpg: clock-controller@e6150000 {
			compatible = "renesas,r8a77990-cpg-mssr";
			reg = <0 0xe6150000 0 0x1000>;
			clocks = <&extal_clk>;
			clock-names = "extal";
			#clock-cells = <2>;
			#power-domain-cells = <0>;
			#reset-cells = <1>;
		};

		rst: reset-controller@e6160000 {
			compatible = "renesas,r8a77990-rst";
			reg = <0 0xe6160000 0 0x0200>;
		};

		sysc: system-controller@e6180000 {
			compatible = "renesas,r8a77990-sysc";
			reg = <0 0xe6180000 0 0x0400>;
			#power-domain-cells = <1>;
		};

		ipmmu_ds0: mmu@e6740000 {
			compatible = "renesas,ipmmu-r8a77990";
			reg = <0 0xe6740000 0 0x1000>;
			renesas,ipmmu-main = <&ipmmu_mm 0>;
			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
			#iommu-cells = <1>;
		};

		ipmmu_ds1: mmu@e7740000 {
			compatible = "renesas,ipmmu-r8a77990";
			reg = <0 0xe7740000 0 0x1000>;
			renesas,ipmmu-main = <&ipmmu_mm 1>;
			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
			#iommu-cells = <1>;
		};

		ipmmu_hc: mmu@e6570000 {
			compatible = "renesas,ipmmu-r8a77990";
			reg = <0 0xe6570000 0 0x1000>;
			renesas,ipmmu-main = <&ipmmu_mm 2>;
			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
			#iommu-cells = <1>;
		};

		ipmmu_mm: mmu@e67b0000 {
			compatible = "renesas,ipmmu-r8a77990";
			reg = <0 0xe67b0000 0 0x1000>;
			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
			#iommu-cells = <1>;
		};

		ipmmu_mp: mmu@ec670000 {
			compatible = "renesas,ipmmu-r8a77990";
			reg = <0 0xec670000 0 0x1000>;
			renesas,ipmmu-main = <&ipmmu_mm 4>;
			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
			#iommu-cells = <1>;
		};

		ipmmu_pv0: mmu@fd800000 {
			compatible = "renesas,ipmmu-r8a77990";
			reg = <0 0xfd800000 0 0x1000>;
			renesas,ipmmu-main = <&ipmmu_mm 6>;
			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
			#iommu-cells = <1>;
		};

		ipmmu_rt: mmu@ffc80000 {
			compatible = "renesas,ipmmu-r8a77990";
			reg = <0 0xffc80000 0 0x1000>;
			renesas,ipmmu-main = <&ipmmu_mm 10>;
			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
			#iommu-cells = <1>;
		};

		ipmmu_vc0: mmu@fe6b0000 {
			compatible = "renesas,ipmmu-r8a77990";
			reg = <0 0xfe6b0000 0 0x1000>;
			renesas,ipmmu-main = <&ipmmu_mm 12>;
			power-domains = <&sysc R8A77990_PD_A3VC>;
			#iommu-cells = <1>;
		};

		ipmmu_vi0: mmu@febd0000 {
			compatible = "renesas,ipmmu-r8a77990";
			reg = <0 0xfebd0000 0 0x1000>;
			renesas,ipmmu-main = <&ipmmu_mm 14>;
			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
			#iommu-cells = <1>;
		};

		ipmmu_vp0: mmu@fe990000 {
			compatible = "renesas,ipmmu-r8a77990";
			reg = <0 0xfe990000 0 0x1000>;
			renesas,ipmmu-main = <&ipmmu_mm 16>;
			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
			#iommu-cells = <1>;
		};

		avb: ethernet@e6800000 {
			compatible = "renesas,etheravb-r8a77990",
				     "renesas,etheravb-rcar-gen3";
			reg = <0 0xe6800000 0 0x800>;
			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "ch0", "ch1", "ch2", "ch3",
					  "ch4", "ch5", "ch6", "ch7",
					  "ch8", "ch9", "ch10", "ch11",
					  "ch12", "ch13", "ch14", "ch15",
					  "ch16", "ch17", "ch18", "ch19",
					  "ch20", "ch21", "ch22", "ch23",
					  "ch24";
			clocks = <&cpg CPG_MOD 812>;
			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
			resets = <&cpg 812>;
			phy-mode = "rgmii";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		pwm0: pwm@e6e30000 {
			compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
			reg = <0 0xe6e30000 0 0x8>;
			clocks = <&cpg CPG_MOD 523>;
			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
			resets = <&cpg 523>;
			#pwm-cells = <2>;
			status = "disabled";
		};

		pwm1: pwm@e6e31000 {
			compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
			reg = <0 0xe6e31000 0 0x8>;
			clocks = <&cpg CPG_MOD 523>;
			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
			resets = <&cpg 523>;
			#pwm-cells = <2>;
			status = "disabled";
		};

		pwm2: pwm@e6e32000 {
			compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
			reg = <0 0xe6e32000 0 0x8>;
			clocks = <&cpg CPG_MOD 523>;
			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
			resets = <&cpg 523>;
			#pwm-cells = <2>;
			status = "disabled";
		};

		pwm3: pwm@e6e33000 {
			compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
			reg = <0 0xe6e33000 0 0x8>;
			clocks = <&cpg CPG_MOD 523>;
			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
			resets = <&cpg 523>;
			#pwm-cells = <2>;
			status = "disabled";
		};

		pwm4: pwm@e6e34000 {
			compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
			reg = <0 0xe6e34000 0 0x8>;
			clocks = <&cpg CPG_MOD 523>;
			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
			resets = <&cpg 523>;
			#pwm-cells = <2>;
			status = "disabled";
		};

		pwm5: pwm@e6e35000 {
			compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
			reg = <0 0xe6e35000 0 0x8>;
			clocks = <&cpg CPG_MOD 523>;
			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
			resets = <&cpg 523>;
			#pwm-cells = <2>;
			status = "disabled";
		};

		pwm6: pwm@e6e36000 {
			compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
			reg = <0 0xe6e36000 0 0x8>;
			clocks = <&cpg CPG_MOD 523>;
			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
			resets = <&cpg 523>;
			#pwm-cells = <2>;
			status = "disabled";
		};

		scif2: serial@e6e88000 {
			compatible = "renesas,scif-r8a77990",
				     "renesas,rcar-gen3-scif", "renesas,scif";
			reg = <0 0xe6e88000 0 64>;
			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 310>,
				 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
				 <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";

			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
			resets = <&cpg 310>;
			status = "disabled";
		};

		xhci0: usb@ee000000 {
			compatible = "renesas,xhci-r8a77990",
				     "renesas,rcar-gen3-xhci";
			reg = <0 0xee000000 0 0xc00>;
			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 328>;
			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
			resets = <&cpg 328>;
			status = "disabled";
		};

		ohci0: usb@ee080000 {
			compatible = "generic-ohci";
			reg = <0 0xee080000 0 0x100>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 703>;
			phys = <&usb2_phy0>;
			phy-names = "usb";
			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
			resets = <&cpg 703>;
			status = "disabled";
		};

		ehci0: usb@ee080100 {
			compatible = "generic-ehci";
			reg = <0 0xee080100 0 0x100>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 703>;
			phys = <&usb2_phy0>;
			phy-names = "usb";
			companion = <&ohci0>;
			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
			resets = <&cpg 703>;
			status = "disabled";
		};

		usb2_phy0: usb-phy@ee080200 {
			compatible = "renesas,usb2-phy-r8a77990",
				     "renesas,rcar-gen3-usb2-phy";
			reg = <0 0xee080200 0 0x700>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 703>;
			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
			resets = <&cpg 703>;
			#phy-cells = <0>;
			status = "disabled";
		};

		gic: interrupt-controller@f1010000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0x0 0xf1010000 0 0x1000>,
			      <0x0 0xf1020000 0 0x20000>,
			      <0x0 0xf1040000 0 0x20000>,
			      <0x0 0xf1060000 0 0x20000>;
			interrupts = <GIC_PPI 9
					(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
			clocks = <&cpg CPG_MOD 408>;
			clock-names = "clk";
			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
			resets = <&cpg 408>;
		};

		prr: chipid@fff00044 {
			compatible = "renesas,prr";
			reg = <0 0xfff00044 0 4>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
	};
};