1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a77980 SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 * Copyright (C) 2018 Cogent Embedded, Inc. 7 */ 8 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/clock/renesas-cpg-mssr.h> 12 13/ { 14 compatible = "renesas,r8a77980"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 a53_0: cpu@0 { 23 device_type = "cpu"; 24 compatible = "arm,cortex-a53", "arm,armv8"; 25 reg = <0>; 26 clocks = <&cpg CPG_CORE 0>; 27 power-domains = <&sysc 5>; 28 next-level-cache = <&L2_CA53>; 29 enable-method = "psci"; 30 }; 31 32 L2_CA53: cache-controller { 33 compatible = "cache"; 34 power-domains = <&sysc 21>; 35 cache-unified; 36 cache-level = <2>; 37 }; 38 }; 39 40 extal_clk: extal { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 /* This value must be overridden by the board */ 44 clock-frequency = <0>; 45 }; 46 47 extalr_clk: extalr { 48 compatible = "fixed-clock"; 49 #clock-cells = <0>; 50 /* This value must be overridden by the board */ 51 clock-frequency = <0>; 52 }; 53 54 psci { 55 compatible = "arm,psci-1.0", "arm,psci-0.2"; 56 method = "smc"; 57 }; 58 59 soc { 60 compatible = "simple-bus"; 61 interrupt-parent = <&gic>; 62 63 #address-cells = <2>; 64 #size-cells = <2>; 65 ranges; 66 67 cpg: clock-controller@e6150000 { 68 compatible = "renesas,r8a77980-cpg-mssr"; 69 reg = <0 0xe6150000 0 0x1000>; 70 clocks = <&extal_clk>, <&extalr_clk>; 71 clock-names = "extal", "extalr"; 72 #clock-cells = <2>; 73 #power-domain-cells = <0>; 74 #reset-cells = <1>; 75 }; 76 77 rst: reset-controller@e6160000 { 78 compatible = "renesas,r8a77980-rst"; 79 reg = <0 0xe6160000 0 0x200>; 80 }; 81 82 sysc: system-controller@e6180000 { 83 compatible = "renesas,r8a77980-sysc"; 84 reg = <0 0xe6180000 0 0x440>; 85 #power-domain-cells = <1>; 86 }; 87 88 gic: interrupt-controller@f1010000 { 89 compatible = "arm,gic-400"; 90 #interrupt-cells = <3>; 91 #address-cells = <0>; 92 interrupt-controller; 93 reg = <0x0 0xf1010000 0 0x1000>, 94 <0x0 0xf1020000 0 0x20000>, 95 <0x0 0xf1040000 0 0x20000>, 96 <0x0 0xf1060000 0 0x20000>; 97 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | 98 IRQ_TYPE_LEVEL_HIGH)>; 99 clocks = <&cpg CPG_MOD 408>; 100 clock-names = "clk"; 101 power-domains = <&sysc 32>; 102 resets = <&cpg 408>; 103 }; 104 105 prr: chipid@fff00044 { 106 compatible = "renesas,prr"; 107 reg = <0 0xfff00044 0 4>; 108 }; 109 }; 110 111 timer { 112 compatible = "arm,armv8-timer"; 113 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | 114 IRQ_TYPE_LEVEL_LOW)>, 115 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | 116 IRQ_TYPE_LEVEL_LOW)>, 117 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | 118 IRQ_TYPE_LEVEL_LOW)>, 119 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | 120 IRQ_TYPE_LEVEL_LOW)>; 121 }; 122}; 123