1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car V3H (R8A77980) SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 * Copyright (C) 2018 Cogent Embedded, Inc. 7 */ 8 9#include <dt-bindings/clock/r8a77980-cpg-mssr.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/power/r8a77980-sysc.h> 13 14/ { 15 compatible = "renesas,r8a77980"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 i2c0 = &i2c0; 21 i2c1 = &i2c1; 22 i2c2 = &i2c2; 23 i2c3 = &i2c3; 24 i2c4 = &i2c4; 25 i2c5 = &i2c5; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 a53_0: cpu@0 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a53", "arm,armv8"; 35 reg = <0>; 36 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 37 power-domains = <&sysc R8A77980_PD_CA53_CPU0>; 38 next-level-cache = <&L2_CA53>; 39 enable-method = "psci"; 40 }; 41 42 a53_1: cpu@1 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a53", "arm,armv8"; 45 reg = <1>; 46 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 47 power-domains = <&sysc R8A77980_PD_CA53_CPU1>; 48 next-level-cache = <&L2_CA53>; 49 enable-method = "psci"; 50 }; 51 52 a53_2: cpu@2 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a53", "arm,armv8"; 55 reg = <2>; 56 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 57 power-domains = <&sysc R8A77980_PD_CA53_CPU2>; 58 next-level-cache = <&L2_CA53>; 59 enable-method = "psci"; 60 }; 61 62 a53_3: cpu@3 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a53", "arm,armv8"; 65 reg = <3>; 66 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 67 power-domains = <&sysc R8A77980_PD_CA53_CPU3>; 68 next-level-cache = <&L2_CA53>; 69 enable-method = "psci"; 70 }; 71 72 L2_CA53: cache-controller { 73 compatible = "cache"; 74 power-domains = <&sysc R8A77980_PD_CA53_SCU>; 75 cache-unified; 76 cache-level = <2>; 77 }; 78 }; 79 80 /* External CAN clock - to be overridden by boards that provide it */ 81 can_clk: can { 82 compatible = "fixed-clock"; 83 #clock-cells = <0>; 84 clock-frequency = <0>; 85 }; 86 87 extal_clk: extal { 88 compatible = "fixed-clock"; 89 #clock-cells = <0>; 90 /* This value must be overridden by the board */ 91 clock-frequency = <0>; 92 }; 93 94 extalr_clk: extalr { 95 compatible = "fixed-clock"; 96 #clock-cells = <0>; 97 /* This value must be overridden by the board */ 98 clock-frequency = <0>; 99 }; 100 101 psci { 102 compatible = "arm,psci-1.0", "arm,psci-0.2"; 103 method = "smc"; 104 }; 105 106 /* External SCIF clock - to be overridden by boards that provide it */ 107 scif_clk: scif { 108 compatible = "fixed-clock"; 109 #clock-cells = <0>; 110 clock-frequency = <0>; 111 }; 112 113 soc { 114 compatible = "simple-bus"; 115 interrupt-parent = <&gic>; 116 117 #address-cells = <2>; 118 #size-cells = <2>; 119 ranges; 120 121 rwdt: watchdog@e6020000 { 122 compatible = "renesas,r8a77980-wdt", 123 "renesas,rcar-gen3-wdt"; 124 reg = <0 0xe6020000 0 0x0c>; 125 clocks = <&cpg CPG_MOD 402>; 126 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 127 resets = <&cpg 402>; 128 status = "disabled"; 129 }; 130 131 gpio0: gpio@e6050000 { 132 compatible = "renesas,gpio-r8a77980", 133 "renesas,rcar-gen3-gpio"; 134 reg = <0 0xe6050000 0 0x50>; 135 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 136 #gpio-cells = <2>; 137 gpio-controller; 138 gpio-ranges = <&pfc 0 0 22>; 139 #interrupt-cells = <2>; 140 interrupt-controller; 141 clocks = <&cpg CPG_MOD 912>; 142 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 143 resets = <&cpg 912>; 144 }; 145 146 gpio1: gpio@e6051000 { 147 compatible = "renesas,gpio-r8a77980", 148 "renesas,rcar-gen3-gpio"; 149 reg = <0 0xe6051000 0 0x50>; 150 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 151 #gpio-cells = <2>; 152 gpio-controller; 153 gpio-ranges = <&pfc 0 32 28>; 154 #interrupt-cells = <2>; 155 interrupt-controller; 156 clocks = <&cpg CPG_MOD 911>; 157 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 158 resets = <&cpg 911>; 159 }; 160 161 gpio2: gpio@e6052000 { 162 compatible = "renesas,gpio-r8a77980", 163 "renesas,rcar-gen3-gpio"; 164 reg = <0 0xe6052000 0 0x50>; 165 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 166 #gpio-cells = <2>; 167 gpio-controller; 168 gpio-ranges = <&pfc 0 64 30>; 169 #interrupt-cells = <2>; 170 interrupt-controller; 171 clocks = <&cpg CPG_MOD 910>; 172 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 173 resets = <&cpg 910>; 174 }; 175 176 gpio3: gpio@e6053000 { 177 compatible = "renesas,gpio-r8a77980", 178 "renesas,rcar-gen3-gpio"; 179 reg = <0 0xe6053000 0 0x50>; 180 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 181 #gpio-cells = <2>; 182 gpio-controller; 183 gpio-ranges = <&pfc 0 96 17>; 184 #interrupt-cells = <2>; 185 interrupt-controller; 186 clocks = <&cpg CPG_MOD 909>; 187 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 188 resets = <&cpg 909>; 189 }; 190 191 gpio4: gpio@e6054000 { 192 compatible = "renesas,gpio-r8a77980", 193 "renesas,rcar-gen3-gpio"; 194 reg = <0 0xe6054000 0 0x50>; 195 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 196 #gpio-cells = <2>; 197 gpio-controller; 198 gpio-ranges = <&pfc 0 128 25>; 199 #interrupt-cells = <2>; 200 interrupt-controller; 201 clocks = <&cpg CPG_MOD 908>; 202 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 203 resets = <&cpg 908>; 204 }; 205 206 gpio5: gpio@e6055000 { 207 compatible = "renesas,gpio-r8a77980", 208 "renesas,rcar-gen3-gpio"; 209 reg = <0 0xe6055000 0 0x50>; 210 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 211 #gpio-cells = <2>; 212 gpio-controller; 213 gpio-ranges = <&pfc 0 160 15>; 214 #interrupt-cells = <2>; 215 interrupt-controller; 216 clocks = <&cpg CPG_MOD 907>; 217 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 218 resets = <&cpg 907>; 219 }; 220 221 pfc: pin-controller@e6060000 { 222 compatible = "renesas,pfc-r8a77980"; 223 reg = <0 0xe6060000 0 0x50c>; 224 }; 225 226 cpg: clock-controller@e6150000 { 227 compatible = "renesas,r8a77980-cpg-mssr"; 228 reg = <0 0xe6150000 0 0x1000>; 229 clocks = <&extal_clk>, <&extalr_clk>; 230 clock-names = "extal", "extalr"; 231 #clock-cells = <2>; 232 #power-domain-cells = <0>; 233 #reset-cells = <1>; 234 }; 235 236 rst: reset-controller@e6160000 { 237 compatible = "renesas,r8a77980-rst"; 238 reg = <0 0xe6160000 0 0x200>; 239 }; 240 241 sysc: system-controller@e6180000 { 242 compatible = "renesas,r8a77980-sysc"; 243 reg = <0 0xe6180000 0 0x440>; 244 #power-domain-cells = <1>; 245 }; 246 247 intc_ex: interrupt-controller@e61c0000 { 248 compatible = "renesas,intc-ex-r8a77980", "renesas,irqc"; 249 #interrupt-cells = <2>; 250 interrupt-controller; 251 reg = <0 0xe61c0000 0 0x200>; 252 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 253 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 254 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 255 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 256 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 257 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 258 clocks = <&cpg CPG_MOD 407>; 259 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 260 resets = <&cpg 407>; 261 }; 262 263 i2c0: i2c@e6500000 { 264 compatible = "renesas,i2c-r8a77980", 265 "renesas,rcar-gen3-i2c"; 266 reg = <0 0xe6500000 0 0x40>; 267 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&cpg CPG_MOD 931>; 269 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 270 resets = <&cpg 931>; 271 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 272 <&dmac2 0x91>, <&dmac2 0x90>; 273 dma-names = "tx", "rx", "tx", "rx"; 274 i2c-scl-internal-delay-ns = <6>; 275 #address-cells = <1>; 276 #size-cells = <0>; 277 status = "disabled"; 278 }; 279 280 i2c1: i2c@e6508000 { 281 compatible = "renesas,i2c-r8a77980", 282 "renesas,rcar-gen3-i2c"; 283 reg = <0 0xe6508000 0 0x40>; 284 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 285 clocks = <&cpg CPG_MOD 930>; 286 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 287 resets = <&cpg 930>; 288 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 289 <&dmac2 0x93>, <&dmac2 0x92>; 290 dma-names = "tx", "rx", "tx", "rx"; 291 i2c-scl-internal-delay-ns = <6>; 292 #address-cells = <1>; 293 #size-cells = <0>; 294 status = "disabled"; 295 }; 296 297 i2c2: i2c@e6510000 { 298 compatible = "renesas,i2c-r8a77980", 299 "renesas,rcar-gen3-i2c"; 300 reg = <0 0xe6510000 0 0x40>; 301 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&cpg CPG_MOD 929>; 303 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 304 resets = <&cpg 929>; 305 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 306 <&dmac2 0x95>, <&dmac2 0x94>; 307 dma-names = "tx", "rx", "tx", "rx"; 308 i2c-scl-internal-delay-ns = <6>; 309 #address-cells = <1>; 310 #size-cells = <0>; 311 status = "disabled"; 312 }; 313 314 i2c3: i2c@e66d0000 { 315 compatible = "renesas,i2c-r8a77980", 316 "renesas,rcar-gen3-i2c"; 317 reg = <0 0xe66d0000 0 0x40>; 318 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&cpg CPG_MOD 928>; 320 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 321 resets = <&cpg 928>; 322 i2c-scl-internal-delay-ns = <6>; 323 #address-cells = <1>; 324 #size-cells = <0>; 325 status = "disabled"; 326 }; 327 328 i2c4: i2c@e66d8000 { 329 compatible = "renesas,i2c-r8a77980", 330 "renesas,rcar-gen3-i2c"; 331 reg = <0 0xe66d8000 0 0x40>; 332 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&cpg CPG_MOD 927>; 334 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 335 resets = <&cpg 927>; 336 i2c-scl-internal-delay-ns = <6>; 337 #address-cells = <1>; 338 #size-cells = <0>; 339 status = "disabled"; 340 }; 341 342 i2c5: i2c@e66e0000 { 343 compatible = "renesas,i2c-r8a77980", 344 "renesas,rcar-gen3-i2c"; 345 reg = <0 0xe66e0000 0 0x40>; 346 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&cpg CPG_MOD 919>; 348 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 349 resets = <&cpg 919>; 350 dmas = <&dmac1 0x9b>, <&dmac1 0x9a>, 351 <&dmac2 0x9b>, <&dmac2 0x9a>; 352 dma-names = "tx", "rx", "tx", "rx"; 353 i2c-scl-internal-delay-ns = <6>; 354 #address-cells = <1>; 355 #size-cells = <0>; 356 status = "disabled"; 357 }; 358 359 hscif0: serial@e6540000 { 360 compatible = "renesas,hscif-r8a77980", 361 "renesas,rcar-gen3-hscif", 362 "renesas,hscif"; 363 reg = <0 0xe6540000 0 0x60>; 364 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&cpg CPG_MOD 520>, 366 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 367 <&scif_clk>; 368 clock-names = "fck", "brg_int", "scif_clk"; 369 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 370 <&dmac2 0x31>, <&dmac2 0x30>; 371 dma-names = "tx", "rx", "tx", "rx"; 372 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 373 resets = <&cpg 520>; 374 status = "disabled"; 375 }; 376 377 hscif1: serial@e6550000 { 378 compatible = "renesas,hscif-r8a77980", 379 "renesas,rcar-gen3-hscif", 380 "renesas,hscif"; 381 reg = <0 0xe6550000 0 0x60>; 382 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&cpg CPG_MOD 519>, 384 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 385 <&scif_clk>; 386 clock-names = "fck", "brg_int", "scif_clk"; 387 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 388 <&dmac2 0x33>, <&dmac2 0x32>; 389 dma-names = "tx", "rx", "tx", "rx"; 390 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 391 resets = <&cpg 519>; 392 status = "disabled"; 393 }; 394 395 hscif2: serial@e6560000 { 396 compatible = "renesas,hscif-r8a77980", 397 "renesas,rcar-gen3-hscif", 398 "renesas,hscif"; 399 reg = <0 0xe6560000 0 0x60>; 400 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 401 clocks = <&cpg CPG_MOD 518>, 402 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 403 <&scif_clk>; 404 clock-names = "fck", "brg_int", "scif_clk"; 405 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 406 <&dmac2 0x35>, <&dmac2 0x34>; 407 dma-names = "tx", "rx", "tx", "rx"; 408 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 409 resets = <&cpg 518>; 410 status = "disabled"; 411 }; 412 413 hscif3: serial@e66a0000 { 414 compatible = "renesas,hscif-r8a77980", 415 "renesas,rcar-gen3-hscif", 416 "renesas,hscif"; 417 reg = <0 0xe66a0000 0 0x60>; 418 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 419 clocks = <&cpg CPG_MOD 517>, 420 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 421 <&scif_clk>; 422 clock-names = "fck", "brg_int", "scif_clk"; 423 dmas = <&dmac1 0x37>, <&dmac1 0x36>, 424 <&dmac2 0x37>, <&dmac2 0x36>; 425 dma-names = "tx", "rx", "tx", "rx"; 426 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 427 resets = <&cpg 517>; 428 status = "disabled"; 429 }; 430 431 canfd: can@e66c0000 { 432 compatible = "renesas,r8a77980-canfd", 433 "renesas,rcar-gen3-canfd"; 434 reg = <0 0xe66c0000 0 0x8000>; 435 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 437 clocks = <&cpg CPG_MOD 914>, 438 <&cpg CPG_CORE R8A77980_CLK_CANFD>, 439 <&can_clk>; 440 clock-names = "fck", "canfd", "can_clk"; 441 assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>; 442 assigned-clock-rates = <40000000>; 443 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 444 resets = <&cpg 914>; 445 status = "disabled"; 446 447 channel0 { 448 status = "disabled"; 449 }; 450 451 channel1 { 452 status = "disabled"; 453 }; 454 }; 455 456 ipmmu_ds1: mmu@e7740000 { 457 compatible = "renesas,ipmmu-r8a77980"; 458 reg = <0 0xe7740000 0 0x1000>; 459 renesas,ipmmu-main = <&ipmmu_mm 0>; 460 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 461 #iommu-cells = <1>; 462 }; 463 464 ipmmu_vip0: mmu@e7b00000 { 465 compatible = "renesas,ipmmu-r8a77980"; 466 reg = <0 0xe7b00000 0 0x1000>; 467 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 468 #iommu-cells = <1>; 469 }; 470 471 ipmmu_vip1: mmu@e7960000 { 472 compatible = "renesas,ipmmu-r8a77980"; 473 reg = <0 0xe7960000 0 0x1000>; 474 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 475 #iommu-cells = <1>; 476 }; 477 478 ipmmu_ir: mmu@ff8b0000 { 479 compatible = "renesas,ipmmu-r8a77980"; 480 reg = <0 0xff8b0000 0 0x1000>; 481 renesas,ipmmu-main = <&ipmmu_mm 3>; 482 power-domains = <&sysc R8A77980_PD_A3IR>; 483 #iommu-cells = <1>; 484 }; 485 486 ipmmu_mm: mmu@e67b0000 { 487 compatible = "renesas,ipmmu-r8a77980"; 488 reg = <0 0xe67b0000 0 0x1000>; 489 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 491 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 492 #iommu-cells = <1>; 493 }; 494 495 ipmmu_rt: mmu@ffc80000 { 496 compatible = "renesas,ipmmu-r8a77980"; 497 reg = <0 0xffc80000 0 0x1000>; 498 renesas,ipmmu-main = <&ipmmu_mm 10>; 499 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 500 #iommu-cells = <1>; 501 }; 502 503 ipmmu_vc0: mmu@fe6b0000 { 504 compatible = "renesas,ipmmu-r8a77980"; 505 reg = <0 0xfe6b0000 0 0x1000>; 506 renesas,ipmmu-main = <&ipmmu_mm 12>; 507 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 508 #iommu-cells = <1>; 509 }; 510 511 ipmmu_vi0: mmu@febd0000 { 512 compatible = "renesas,ipmmu-r8a77980"; 513 reg = <0 0xfebd0000 0 0x1000>; 514 renesas,ipmmu-main = <&ipmmu_mm 14>; 515 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 516 #iommu-cells = <1>; 517 }; 518 519 avb: ethernet@e6800000 { 520 compatible = "renesas,etheravb-r8a77980", 521 "renesas,etheravb-rcar-gen3"; 522 reg = <0 0xe6800000 0 0x800>; 523 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 548 interrupt-names = "ch0", "ch1", "ch2", "ch3", 549 "ch4", "ch5", "ch6", "ch7", 550 "ch8", "ch9", "ch10", "ch11", 551 "ch12", "ch13", "ch14", "ch15", 552 "ch16", "ch17", "ch18", "ch19", 553 "ch20", "ch21", "ch22", "ch23", 554 "ch24"; 555 clocks = <&cpg CPG_MOD 812>; 556 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 557 resets = <&cpg 812>; 558 phy-mode = "rgmii"; 559 #address-cells = <1>; 560 #size-cells = <0>; 561 status = "disabled"; 562 }; 563 564 scif0: serial@e6e60000 { 565 compatible = "renesas,scif-r8a77980", 566 "renesas,rcar-gen3-scif", 567 "renesas,scif"; 568 reg = <0 0xe6e60000 0 0x40>; 569 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 570 clocks = <&cpg CPG_MOD 207>, 571 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 572 <&scif_clk>; 573 clock-names = "fck", "brg_int", "scif_clk"; 574 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 575 <&dmac2 0x51>, <&dmac2 0x50>; 576 dma-names = "tx", "rx", "tx", "rx"; 577 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 578 resets = <&cpg 207>; 579 status = "disabled"; 580 }; 581 582 scif1: serial@e6e68000 { 583 compatible = "renesas,scif-r8a77980", 584 "renesas,rcar-gen3-scif", 585 "renesas,scif"; 586 reg = <0 0xe6e68000 0 0x40>; 587 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 588 clocks = <&cpg CPG_MOD 206>, 589 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 590 <&scif_clk>; 591 clock-names = "fck", "brg_int", "scif_clk"; 592 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 593 <&dmac2 0x53>, <&dmac2 0x52>; 594 dma-names = "tx", "rx", "tx", "rx"; 595 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 596 resets = <&cpg 206>; 597 status = "disabled"; 598 }; 599 600 scif3: serial@e6c50000 { 601 compatible = "renesas,scif-r8a77980", 602 "renesas,rcar-gen3-scif", 603 "renesas,scif"; 604 reg = <0 0xe6c50000 0 0x40>; 605 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 606 clocks = <&cpg CPG_MOD 204>, 607 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 608 <&scif_clk>; 609 clock-names = "fck", "brg_int", "scif_clk"; 610 dmas = <&dmac1 0x57>, <&dmac1 0x56>, 611 <&dmac2 0x57>, <&dmac2 0x56>; 612 dma-names = "tx", "rx", "tx", "rx"; 613 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 614 resets = <&cpg 204>; 615 status = "disabled"; 616 }; 617 618 scif4: serial@e6c40000 { 619 compatible = "renesas,scif-r8a77980", 620 "renesas,rcar-gen3-scif", 621 "renesas,scif"; 622 reg = <0 0xe6c40000 0 0x40>; 623 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 624 clocks = <&cpg CPG_MOD 203>, 625 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 626 <&scif_clk>; 627 clock-names = "fck", "brg_int", "scif_clk"; 628 dmas = <&dmac1 0x59>, <&dmac1 0x58>, 629 <&dmac2 0x59>, <&dmac2 0x58>; 630 dma-names = "tx", "rx", "tx", "rx"; 631 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 632 resets = <&cpg 203>; 633 status = "disabled"; 634 }; 635 636 dmac1: dma-controller@e7300000 { 637 compatible = "renesas,dmac-r8a77980", 638 "renesas,rcar-dmac"; 639 reg = <0 0xe7300000 0 0x10000>; 640 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 641 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 642 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 643 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 644 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 645 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 646 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 647 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 648 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 649 GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 650 GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 651 GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 652 GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 653 GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 654 GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 655 GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 656 GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 657 interrupt-names = "error", 658 "ch0", "ch1", "ch2", "ch3", 659 "ch4", "ch5", "ch6", "ch7", 660 "ch8", "ch9", "ch10", "ch11", 661 "ch12", "ch13", "ch14", "ch15"; 662 clocks = <&cpg CPG_MOD 218>; 663 clock-names = "fck"; 664 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 665 resets = <&cpg 218>; 666 #dma-cells = <1>; 667 dma-channels = <16>; 668 }; 669 670 dmac2: dma-controller@e7310000 { 671 compatible = "renesas,dmac-r8a77980", 672 "renesas,rcar-dmac"; 673 reg = <0 0xe7310000 0 0x10000>; 674 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 675 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 676 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 677 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 678 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 679 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 680 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 681 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 682 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 683 GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 684 GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 685 GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 686 GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 687 GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 688 GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH 689 GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 690 GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 691 interrupt-names = "error", 692 "ch0", "ch1", "ch2", "ch3", 693 "ch4", "ch5", "ch6", "ch7", 694 "ch8", "ch9", "ch10", "ch11", 695 "ch12", "ch13", "ch14", "ch15"; 696 clocks = <&cpg CPG_MOD 217>; 697 clock-names = "fck"; 698 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 699 resets = <&cpg 217>; 700 #dma-cells = <1>; 701 dma-channels = <16>; 702 }; 703 704 gether: ethernet@e7400000 { 705 compatible = "renesas,gether-r8a77980"; 706 reg = <0 0xe7400000 0 0x1000>; 707 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 708 clocks = <&cpg CPG_MOD 813>; 709 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 710 resets = <&cpg 813>; 711 #address-cells = <1>; 712 #size-cells = <0>; 713 status = "disabled"; 714 }; 715 716 mmc0: mmc@ee140000 { 717 compatible = "renesas,sdhi-r8a77980", 718 "renesas,rcar-gen3-sdhi"; 719 reg = <0 0xee140000 0 0x2000>; 720 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&cpg CPG_MOD 314>; 722 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 723 resets = <&cpg 314>; 724 max-frequency = <200000000>; 725 status = "disabled"; 726 }; 727 728 gic: interrupt-controller@f1010000 { 729 compatible = "arm,gic-400"; 730 #interrupt-cells = <3>; 731 #address-cells = <0>; 732 interrupt-controller; 733 reg = <0x0 0xf1010000 0 0x1000>, 734 <0x0 0xf1020000 0 0x20000>, 735 <0x0 0xf1040000 0 0x20000>, 736 <0x0 0xf1060000 0 0x20000>; 737 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 738 IRQ_TYPE_LEVEL_HIGH)>; 739 clocks = <&cpg CPG_MOD 408>; 740 clock-names = "clk"; 741 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 742 resets = <&cpg 408>; 743 }; 744 745 vspd0: vsp@fea20000 { 746 compatible = "renesas,vsp2"; 747 reg = <0 0xfea20000 0 0x5000>; 748 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 749 clocks = <&cpg CPG_MOD 623>; 750 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 751 resets = <&cpg 623>; 752 renesas,fcp = <&fcpvd0>; 753 }; 754 755 fcpvd0: fcp@fea27000 { 756 compatible = "renesas,fcpv"; 757 reg = <0 0xfea27000 0 0x200>; 758 clocks = <&cpg CPG_MOD 603>; 759 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 760 resets = <&cpg 603>; 761 }; 762 763 du: display@feb00000 { 764 compatible = "renesas,du-r8a77980", 765 "renesas,du-r8a77970"; 766 reg = <0 0xfeb00000 0 0x80000>; 767 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 768 clocks = <&cpg CPG_MOD 724>; 769 clock-names = "du.0"; 770 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 771 resets = <&cpg 724>; 772 vsps = <&vspd0>; 773 status = "disabled"; 774 775 ports { 776 #address-cells = <1>; 777 #size-cells = <0>; 778 779 port@0 { 780 reg = <0>; 781 du_out_rgb: endpoint { 782 }; 783 }; 784 785 port@1 { 786 reg = <1>; 787 du_out_lvds0: endpoint { 788 remote-endpoint = <&lvds0_in>; 789 }; 790 }; 791 }; 792 }; 793 794 lvds0: lvds-encoder@feb90000 { 795 compatible = "renesas,r8a77980-lvds"; 796 reg = <0 0xfeb90000 0 0x14>; 797 clocks = <&cpg CPG_MOD 727>; 798 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 799 resets = <&cpg 727>; 800 status = "disabled"; 801 802 ports { 803 #address-cells = <1>; 804 #size-cells = <0>; 805 806 port@0 { 807 reg = <0>; 808 lvds0_in: endpoint { 809 remote-endpoint = 810 <&du_out_lvds0>; 811 }; 812 }; 813 814 port@1 { 815 reg = <1>; 816 lvds0_out: endpoint { 817 }; 818 }; 819 }; 820 }; 821 822 prr: chipid@fff00044 { 823 compatible = "renesas,prr"; 824 reg = <0 0xfff00044 0 4>; 825 }; 826 }; 827 828 timer { 829 compatible = "arm,armv8-timer"; 830 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 831 IRQ_TYPE_LEVEL_LOW)>, 832 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 833 IRQ_TYPE_LEVEL_LOW)>, 834 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 835 IRQ_TYPE_LEVEL_LOW)>, 836 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 837 IRQ_TYPE_LEVEL_LOW)>; 838 }; 839}; 840