1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car V3H (R8A77980) SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 * Copyright (C) 2018 Cogent Embedded, Inc. 7 */ 8 9#include <dt-bindings/clock/r8a77980-cpg-mssr.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/power/r8a77980-sysc.h> 13 14/ { 15 compatible = "renesas,r8a77980"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 i2c0 = &i2c0; 21 i2c1 = &i2c1; 22 i2c2 = &i2c2; 23 i2c3 = &i2c3; 24 i2c4 = &i2c4; 25 i2c5 = &i2c5; 26 }; 27 28 /* External CAN clock - to be overridden by boards that provide it */ 29 can_clk: can { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <0>; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 a53_0: cpu@0 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a53", "arm,armv8"; 42 reg = <0>; 43 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 44 power-domains = <&sysc R8A77980_PD_CA53_CPU0>; 45 next-level-cache = <&L2_CA53>; 46 enable-method = "psci"; 47 }; 48 49 a53_1: cpu@1 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53", "arm,armv8"; 52 reg = <1>; 53 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 54 power-domains = <&sysc R8A77980_PD_CA53_CPU1>; 55 next-level-cache = <&L2_CA53>; 56 enable-method = "psci"; 57 }; 58 59 a53_2: cpu@2 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53", "arm,armv8"; 62 reg = <2>; 63 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 64 power-domains = <&sysc R8A77980_PD_CA53_CPU2>; 65 next-level-cache = <&L2_CA53>; 66 enable-method = "psci"; 67 }; 68 69 a53_3: cpu@3 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53", "arm,armv8"; 72 reg = <3>; 73 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 74 power-domains = <&sysc R8A77980_PD_CA53_CPU3>; 75 next-level-cache = <&L2_CA53>; 76 enable-method = "psci"; 77 }; 78 79 L2_CA53: cache-controller { 80 compatible = "cache"; 81 power-domains = <&sysc R8A77980_PD_CA53_SCU>; 82 cache-unified; 83 cache-level = <2>; 84 }; 85 }; 86 87 extal_clk: extal { 88 compatible = "fixed-clock"; 89 #clock-cells = <0>; 90 /* This value must be overridden by the board */ 91 clock-frequency = <0>; 92 }; 93 94 extalr_clk: extalr { 95 compatible = "fixed-clock"; 96 #clock-cells = <0>; 97 /* This value must be overridden by the board */ 98 clock-frequency = <0>; 99 }; 100 101 /* External PCIe clock - can be overridden by the board */ 102 pcie_bus_clk: pcie_bus { 103 compatible = "fixed-clock"; 104 #clock-cells = <0>; 105 clock-frequency = <0>; 106 }; 107 108 pmu_a53 { 109 compatible = "arm,cortex-a53-pmu"; 110 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 111 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 112 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 113 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 114 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 115 }; 116 117 psci { 118 compatible = "arm,psci-1.0", "arm,psci-0.2"; 119 method = "smc"; 120 }; 121 122 /* External SCIF clock - to be overridden by boards that provide it */ 123 scif_clk: scif { 124 compatible = "fixed-clock"; 125 #clock-cells = <0>; 126 clock-frequency = <0>; 127 }; 128 129 soc { 130 compatible = "simple-bus"; 131 interrupt-parent = <&gic>; 132 133 #address-cells = <2>; 134 #size-cells = <2>; 135 ranges; 136 137 rwdt: watchdog@e6020000 { 138 compatible = "renesas,r8a77980-wdt", 139 "renesas,rcar-gen3-wdt"; 140 reg = <0 0xe6020000 0 0x0c>; 141 clocks = <&cpg CPG_MOD 402>; 142 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 143 resets = <&cpg 402>; 144 status = "disabled"; 145 }; 146 147 gpio0: gpio@e6050000 { 148 compatible = "renesas,gpio-r8a77980", 149 "renesas,rcar-gen3-gpio"; 150 reg = <0 0xe6050000 0 0x50>; 151 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 152 #gpio-cells = <2>; 153 gpio-controller; 154 gpio-ranges = <&pfc 0 0 22>; 155 #interrupt-cells = <2>; 156 interrupt-controller; 157 clocks = <&cpg CPG_MOD 912>; 158 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 159 resets = <&cpg 912>; 160 }; 161 162 gpio1: gpio@e6051000 { 163 compatible = "renesas,gpio-r8a77980", 164 "renesas,rcar-gen3-gpio"; 165 reg = <0 0xe6051000 0 0x50>; 166 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 167 #gpio-cells = <2>; 168 gpio-controller; 169 gpio-ranges = <&pfc 0 32 28>; 170 #interrupt-cells = <2>; 171 interrupt-controller; 172 clocks = <&cpg CPG_MOD 911>; 173 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 174 resets = <&cpg 911>; 175 }; 176 177 gpio2: gpio@e6052000 { 178 compatible = "renesas,gpio-r8a77980", 179 "renesas,rcar-gen3-gpio"; 180 reg = <0 0xe6052000 0 0x50>; 181 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 182 #gpio-cells = <2>; 183 gpio-controller; 184 gpio-ranges = <&pfc 0 64 30>; 185 #interrupt-cells = <2>; 186 interrupt-controller; 187 clocks = <&cpg CPG_MOD 910>; 188 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 189 resets = <&cpg 910>; 190 }; 191 192 gpio3: gpio@e6053000 { 193 compatible = "renesas,gpio-r8a77980", 194 "renesas,rcar-gen3-gpio"; 195 reg = <0 0xe6053000 0 0x50>; 196 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 197 #gpio-cells = <2>; 198 gpio-controller; 199 gpio-ranges = <&pfc 0 96 17>; 200 #interrupt-cells = <2>; 201 interrupt-controller; 202 clocks = <&cpg CPG_MOD 909>; 203 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 204 resets = <&cpg 909>; 205 }; 206 207 gpio4: gpio@e6054000 { 208 compatible = "renesas,gpio-r8a77980", 209 "renesas,rcar-gen3-gpio"; 210 reg = <0 0xe6054000 0 0x50>; 211 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 212 #gpio-cells = <2>; 213 gpio-controller; 214 gpio-ranges = <&pfc 0 128 25>; 215 #interrupt-cells = <2>; 216 interrupt-controller; 217 clocks = <&cpg CPG_MOD 908>; 218 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 219 resets = <&cpg 908>; 220 }; 221 222 gpio5: gpio@e6055000 { 223 compatible = "renesas,gpio-r8a77980", 224 "renesas,rcar-gen3-gpio"; 225 reg = <0 0xe6055000 0 0x50>; 226 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 227 #gpio-cells = <2>; 228 gpio-controller; 229 gpio-ranges = <&pfc 0 160 15>; 230 #interrupt-cells = <2>; 231 interrupt-controller; 232 clocks = <&cpg CPG_MOD 907>; 233 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 234 resets = <&cpg 907>; 235 }; 236 237 pfc: pin-controller@e6060000 { 238 compatible = "renesas,pfc-r8a77980"; 239 reg = <0 0xe6060000 0 0x50c>; 240 }; 241 242 cpg: clock-controller@e6150000 { 243 compatible = "renesas,r8a77980-cpg-mssr"; 244 reg = <0 0xe6150000 0 0x1000>; 245 clocks = <&extal_clk>, <&extalr_clk>; 246 clock-names = "extal", "extalr"; 247 #clock-cells = <2>; 248 #power-domain-cells = <0>; 249 #reset-cells = <1>; 250 }; 251 252 rst: reset-controller@e6160000 { 253 compatible = "renesas,r8a77980-rst"; 254 reg = <0 0xe6160000 0 0x200>; 255 }; 256 257 sysc: system-controller@e6180000 { 258 compatible = "renesas,r8a77980-sysc"; 259 reg = <0 0xe6180000 0 0x440>; 260 #power-domain-cells = <1>; 261 }; 262 263 intc_ex: interrupt-controller@e61c0000 { 264 compatible = "renesas,intc-ex-r8a77980", "renesas,irqc"; 265 #interrupt-cells = <2>; 266 interrupt-controller; 267 reg = <0 0xe61c0000 0 0x200>; 268 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 269 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 270 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 271 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 272 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 273 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 274 clocks = <&cpg CPG_MOD 407>; 275 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 276 resets = <&cpg 407>; 277 }; 278 279 i2c0: i2c@e6500000 { 280 compatible = "renesas,i2c-r8a77980", 281 "renesas,rcar-gen3-i2c"; 282 reg = <0 0xe6500000 0 0x40>; 283 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 284 clocks = <&cpg CPG_MOD 931>; 285 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 286 resets = <&cpg 931>; 287 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 288 <&dmac2 0x91>, <&dmac2 0x90>; 289 dma-names = "tx", "rx", "tx", "rx"; 290 i2c-scl-internal-delay-ns = <6>; 291 #address-cells = <1>; 292 #size-cells = <0>; 293 status = "disabled"; 294 }; 295 296 i2c1: i2c@e6508000 { 297 compatible = "renesas,i2c-r8a77980", 298 "renesas,rcar-gen3-i2c"; 299 reg = <0 0xe6508000 0 0x40>; 300 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&cpg CPG_MOD 930>; 302 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 303 resets = <&cpg 930>; 304 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 305 <&dmac2 0x93>, <&dmac2 0x92>; 306 dma-names = "tx", "rx", "tx", "rx"; 307 i2c-scl-internal-delay-ns = <6>; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 status = "disabled"; 311 }; 312 313 i2c2: i2c@e6510000 { 314 compatible = "renesas,i2c-r8a77980", 315 "renesas,rcar-gen3-i2c"; 316 reg = <0 0xe6510000 0 0x40>; 317 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&cpg CPG_MOD 929>; 319 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 320 resets = <&cpg 929>; 321 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 322 <&dmac2 0x95>, <&dmac2 0x94>; 323 dma-names = "tx", "rx", "tx", "rx"; 324 i2c-scl-internal-delay-ns = <6>; 325 #address-cells = <1>; 326 #size-cells = <0>; 327 status = "disabled"; 328 }; 329 330 i2c3: i2c@e66d0000 { 331 compatible = "renesas,i2c-r8a77980", 332 "renesas,rcar-gen3-i2c"; 333 reg = <0 0xe66d0000 0 0x40>; 334 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 335 clocks = <&cpg CPG_MOD 928>; 336 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 337 resets = <&cpg 928>; 338 i2c-scl-internal-delay-ns = <6>; 339 #address-cells = <1>; 340 #size-cells = <0>; 341 status = "disabled"; 342 }; 343 344 i2c4: i2c@e66d8000 { 345 compatible = "renesas,i2c-r8a77980", 346 "renesas,rcar-gen3-i2c"; 347 reg = <0 0xe66d8000 0 0x40>; 348 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&cpg CPG_MOD 927>; 350 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 351 resets = <&cpg 927>; 352 i2c-scl-internal-delay-ns = <6>; 353 #address-cells = <1>; 354 #size-cells = <0>; 355 status = "disabled"; 356 }; 357 358 i2c5: i2c@e66e0000 { 359 compatible = "renesas,i2c-r8a77980", 360 "renesas,rcar-gen3-i2c"; 361 reg = <0 0xe66e0000 0 0x40>; 362 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 363 clocks = <&cpg CPG_MOD 919>; 364 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 365 resets = <&cpg 919>; 366 dmas = <&dmac1 0x9b>, <&dmac1 0x9a>, 367 <&dmac2 0x9b>, <&dmac2 0x9a>; 368 dma-names = "tx", "rx", "tx", "rx"; 369 i2c-scl-internal-delay-ns = <6>; 370 #address-cells = <1>; 371 #size-cells = <0>; 372 status = "disabled"; 373 }; 374 375 hscif0: serial@e6540000 { 376 compatible = "renesas,hscif-r8a77980", 377 "renesas,rcar-gen3-hscif", 378 "renesas,hscif"; 379 reg = <0 0xe6540000 0 0x60>; 380 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 381 clocks = <&cpg CPG_MOD 520>, 382 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 383 <&scif_clk>; 384 clock-names = "fck", "brg_int", "scif_clk"; 385 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 386 <&dmac2 0x31>, <&dmac2 0x30>; 387 dma-names = "tx", "rx", "tx", "rx"; 388 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 389 resets = <&cpg 520>; 390 status = "disabled"; 391 }; 392 393 hscif1: serial@e6550000 { 394 compatible = "renesas,hscif-r8a77980", 395 "renesas,rcar-gen3-hscif", 396 "renesas,hscif"; 397 reg = <0 0xe6550000 0 0x60>; 398 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 399 clocks = <&cpg CPG_MOD 519>, 400 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 401 <&scif_clk>; 402 clock-names = "fck", "brg_int", "scif_clk"; 403 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 404 <&dmac2 0x33>, <&dmac2 0x32>; 405 dma-names = "tx", "rx", "tx", "rx"; 406 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 407 resets = <&cpg 519>; 408 status = "disabled"; 409 }; 410 411 hscif2: serial@e6560000 { 412 compatible = "renesas,hscif-r8a77980", 413 "renesas,rcar-gen3-hscif", 414 "renesas,hscif"; 415 reg = <0 0xe6560000 0 0x60>; 416 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 417 clocks = <&cpg CPG_MOD 518>, 418 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 419 <&scif_clk>; 420 clock-names = "fck", "brg_int", "scif_clk"; 421 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 422 <&dmac2 0x35>, <&dmac2 0x34>; 423 dma-names = "tx", "rx", "tx", "rx"; 424 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 425 resets = <&cpg 518>; 426 status = "disabled"; 427 }; 428 429 hscif3: serial@e66a0000 { 430 compatible = "renesas,hscif-r8a77980", 431 "renesas,rcar-gen3-hscif", 432 "renesas,hscif"; 433 reg = <0 0xe66a0000 0 0x60>; 434 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 435 clocks = <&cpg CPG_MOD 517>, 436 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 437 <&scif_clk>; 438 clock-names = "fck", "brg_int", "scif_clk"; 439 dmas = <&dmac1 0x37>, <&dmac1 0x36>, 440 <&dmac2 0x37>, <&dmac2 0x36>; 441 dma-names = "tx", "rx", "tx", "rx"; 442 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 443 resets = <&cpg 517>; 444 status = "disabled"; 445 }; 446 447 pcie_phy: pcie-phy@e65d0000 { 448 compatible = "renesas,r8a77980-pcie-phy"; 449 reg = <0 0xe65d0000 0 0x8000>; 450 #phy-cells = <0>; 451 clocks = <&cpg CPG_MOD 319>; 452 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 453 resets = <&cpg 319>; 454 status = "disabled"; 455 }; 456 457 canfd: can@e66c0000 { 458 compatible = "renesas,r8a77980-canfd", 459 "renesas,rcar-gen3-canfd"; 460 reg = <0 0xe66c0000 0 0x8000>; 461 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&cpg CPG_MOD 914>, 464 <&cpg CPG_CORE R8A77980_CLK_CANFD>, 465 <&can_clk>; 466 clock-names = "fck", "canfd", "can_clk"; 467 assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>; 468 assigned-clock-rates = <40000000>; 469 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 470 resets = <&cpg 914>; 471 status = "disabled"; 472 473 channel0 { 474 status = "disabled"; 475 }; 476 477 channel1 { 478 status = "disabled"; 479 }; 480 }; 481 482 avb: ethernet@e6800000 { 483 compatible = "renesas,etheravb-r8a77980", 484 "renesas,etheravb-rcar-gen3"; 485 reg = <0 0xe6800000 0 0x800>; 486 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 511 interrupt-names = "ch0", "ch1", "ch2", "ch3", 512 "ch4", "ch5", "ch6", "ch7", 513 "ch8", "ch9", "ch10", "ch11", 514 "ch12", "ch13", "ch14", "ch15", 515 "ch16", "ch17", "ch18", "ch19", 516 "ch20", "ch21", "ch22", "ch23", 517 "ch24"; 518 clocks = <&cpg CPG_MOD 812>; 519 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 520 resets = <&cpg 812>; 521 phy-mode = "rgmii"; 522 #address-cells = <1>; 523 #size-cells = <0>; 524 status = "disabled"; 525 }; 526 527 scif0: serial@e6e60000 { 528 compatible = "renesas,scif-r8a77980", 529 "renesas,rcar-gen3-scif", 530 "renesas,scif"; 531 reg = <0 0xe6e60000 0 0x40>; 532 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 533 clocks = <&cpg CPG_MOD 207>, 534 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 535 <&scif_clk>; 536 clock-names = "fck", "brg_int", "scif_clk"; 537 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 538 <&dmac2 0x51>, <&dmac2 0x50>; 539 dma-names = "tx", "rx", "tx", "rx"; 540 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 541 resets = <&cpg 207>; 542 status = "disabled"; 543 }; 544 545 scif1: serial@e6e68000 { 546 compatible = "renesas,scif-r8a77980", 547 "renesas,rcar-gen3-scif", 548 "renesas,scif"; 549 reg = <0 0xe6e68000 0 0x40>; 550 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 551 clocks = <&cpg CPG_MOD 206>, 552 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 553 <&scif_clk>; 554 clock-names = "fck", "brg_int", "scif_clk"; 555 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 556 <&dmac2 0x53>, <&dmac2 0x52>; 557 dma-names = "tx", "rx", "tx", "rx"; 558 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 559 resets = <&cpg 206>; 560 status = "disabled"; 561 }; 562 563 scif3: serial@e6c50000 { 564 compatible = "renesas,scif-r8a77980", 565 "renesas,rcar-gen3-scif", 566 "renesas,scif"; 567 reg = <0 0xe6c50000 0 0x40>; 568 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 569 clocks = <&cpg CPG_MOD 204>, 570 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 571 <&scif_clk>; 572 clock-names = "fck", "brg_int", "scif_clk"; 573 dmas = <&dmac1 0x57>, <&dmac1 0x56>, 574 <&dmac2 0x57>, <&dmac2 0x56>; 575 dma-names = "tx", "rx", "tx", "rx"; 576 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 577 resets = <&cpg 204>; 578 status = "disabled"; 579 }; 580 581 scif4: serial@e6c40000 { 582 compatible = "renesas,scif-r8a77980", 583 "renesas,rcar-gen3-scif", 584 "renesas,scif"; 585 reg = <0 0xe6c40000 0 0x40>; 586 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 587 clocks = <&cpg CPG_MOD 203>, 588 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 589 <&scif_clk>; 590 clock-names = "fck", "brg_int", "scif_clk"; 591 dmas = <&dmac1 0x59>, <&dmac1 0x58>, 592 <&dmac2 0x59>, <&dmac2 0x58>; 593 dma-names = "tx", "rx", "tx", "rx"; 594 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 595 resets = <&cpg 203>; 596 status = "disabled"; 597 }; 598 599 vin0: video@e6ef0000 { 600 compatible = "renesas,vin-r8a77980"; 601 reg = <0 0xe6ef0000 0 0x1000>; 602 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 603 clocks = <&cpg CPG_MOD 811>; 604 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 605 resets = <&cpg 811>; 606 status = "disabled"; 607 608 ports { 609 #address-cells = <1>; 610 #size-cells = <0>; 611 612 port@1 { 613 #address-cells = <1>; 614 #size-cells = <0>; 615 616 reg = <1>; 617 618 vin0csi40: endpoint@2 { 619 reg = <2>; 620 remote-endpoint = <&csi40vin0>; 621 }; 622 }; 623 }; 624 }; 625 626 vin1: video@e6ef1000 { 627 compatible = "renesas,vin-r8a77980"; 628 reg = <0 0xe6ef1000 0 0x1000>; 629 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 630 clocks = <&cpg CPG_MOD 810>; 631 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 632 status = "disabled"; 633 resets = <&cpg 810>; 634 635 ports { 636 #address-cells = <1>; 637 #size-cells = <0>; 638 639 port@1 { 640 #address-cells = <1>; 641 #size-cells = <0>; 642 643 reg = <1>; 644 645 vin1csi40: endpoint@2 { 646 reg = <2>; 647 remote-endpoint = <&csi40vin1>; 648 }; 649 }; 650 }; 651 }; 652 653 vin2: video@e6ef2000 { 654 compatible = "renesas,vin-r8a77980"; 655 reg = <0 0xe6ef2000 0 0x1000>; 656 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 657 clocks = <&cpg CPG_MOD 809>; 658 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 659 resets = <&cpg 809>; 660 status = "disabled"; 661 662 ports { 663 #address-cells = <1>; 664 #size-cells = <0>; 665 666 port@1 { 667 #address-cells = <1>; 668 #size-cells = <0>; 669 670 reg = <1>; 671 672 vin2csi40: endpoint@2 { 673 reg = <2>; 674 remote-endpoint = <&csi40vin2>; 675 }; 676 }; 677 }; 678 }; 679 680 vin3: video@e6ef3000 { 681 compatible = "renesas,vin-r8a77980"; 682 reg = <0 0xe6ef3000 0 0x1000>; 683 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 684 clocks = <&cpg CPG_MOD 808>; 685 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 686 resets = <&cpg 808>; 687 status = "disabled"; 688 689 ports { 690 #address-cells = <1>; 691 #size-cells = <0>; 692 693 port@1 { 694 #address-cells = <1>; 695 #size-cells = <0>; 696 697 reg = <1>; 698 699 vin3csi40: endpoint@2 { 700 reg = <2>; 701 remote-endpoint = <&csi40vin3>; 702 }; 703 }; 704 }; 705 }; 706 707 vin4: video@e6ef4000 { 708 compatible = "renesas,vin-r8a77980"; 709 reg = <0 0xe6ef4000 0 0x1000>; 710 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 711 clocks = <&cpg CPG_MOD 807>; 712 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 713 resets = <&cpg 807>; 714 status = "disabled"; 715 716 ports { 717 #address-cells = <1>; 718 #size-cells = <0>; 719 720 port@1 { 721 #address-cells = <1>; 722 #size-cells = <0>; 723 724 reg = <1>; 725 726 vin4csi41: endpoint@2 { 727 reg = <2>; 728 remote-endpoint = <&csi41vin4>; 729 }; 730 }; 731 }; 732 }; 733 734 vin5: video@e6ef5000 { 735 compatible = "renesas,vin-r8a77980"; 736 reg = <0 0xe6ef5000 0 0x1000>; 737 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 738 clocks = <&cpg CPG_MOD 806>; 739 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 740 resets = <&cpg 806>; 741 status = "disabled"; 742 743 ports { 744 #address-cells = <1>; 745 #size-cells = <0>; 746 747 port@1 { 748 #address-cells = <1>; 749 #size-cells = <0>; 750 751 reg = <1>; 752 753 vin5csi41: endpoint@2 { 754 reg = <2>; 755 remote-endpoint = <&csi41vin5>; 756 }; 757 }; 758 }; 759 }; 760 761 vin6: video@e6ef6000 { 762 compatible = "renesas,vin-r8a77980"; 763 reg = <0 0xe6ef6000 0 0x1000>; 764 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 765 clocks = <&cpg CPG_MOD 805>; 766 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 767 resets = <&cpg 805>; 768 status = "disabled"; 769 770 ports { 771 #address-cells = <1>; 772 #size-cells = <0>; 773 774 port@1 { 775 #address-cells = <1>; 776 #size-cells = <0>; 777 778 reg = <1>; 779 780 vin6csi41: endpoint@2 { 781 reg = <2>; 782 remote-endpoint = <&csi41vin6>; 783 }; 784 }; 785 }; 786 }; 787 788 vin7: video@e6ef7000 { 789 compatible = "renesas,vin-r8a77980"; 790 reg = <0 0xe6ef7000 0 0x1000>; 791 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 792 clocks = <&cpg CPG_MOD 804>; 793 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 794 resets = <&cpg 804>; 795 status = "disabled"; 796 797 ports { 798 #address-cells = <1>; 799 #size-cells = <0>; 800 801 port@1 { 802 #address-cells = <1>; 803 #size-cells = <0>; 804 805 reg = <1>; 806 807 vin7csi41: endpoint@2 { 808 reg = <2>; 809 remote-endpoint = <&csi41vin7>; 810 }; 811 }; 812 }; 813 }; 814 815 vin8: video@e6ef8000 { 816 compatible = "renesas,vin-r8a77980"; 817 reg = <0 0xe6ef8000 0 0x1000>; 818 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 819 clocks = <&cpg CPG_MOD 628>; 820 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 821 resets = <&cpg 628>; 822 status = "disabled"; 823 }; 824 825 vin9: video@e6ef9000 { 826 compatible = "renesas,vin-r8a77980"; 827 reg = <0 0xe6ef9000 0 0x1000>; 828 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 829 clocks = <&cpg CPG_MOD 627>; 830 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 831 resets = <&cpg 627>; 832 status = "disabled"; 833 }; 834 835 vin10: video@e6efa000 { 836 compatible = "renesas,vin-r8a77980"; 837 reg = <0 0xe6efa000 0 0x1000>; 838 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>; 839 clocks = <&cpg CPG_MOD 625>; 840 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 841 resets = <&cpg 625>; 842 status = "disabled"; 843 }; 844 845 vin11: video@e6efb000 { 846 compatible = "renesas,vin-r8a77980"; 847 reg = <0 0xe6efb000 0 0x1000>; 848 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; 849 clocks = <&cpg CPG_MOD 618>; 850 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 851 resets = <&cpg 618>; 852 status = "disabled"; 853 }; 854 855 vin12: video@e6efc000 { 856 compatible = "renesas,vin-r8a77980"; 857 reg = <0 0xe6efc000 0 0x1000>; 858 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 859 clocks = <&cpg CPG_MOD 612>; 860 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 861 resets = <&cpg 612>; 862 status = "disabled"; 863 }; 864 865 vin13: video@e6efd000 { 866 compatible = "renesas,vin-r8a77980"; 867 reg = <0 0xe6efd000 0 0x1000>; 868 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 869 clocks = <&cpg CPG_MOD 608>; 870 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 871 resets = <&cpg 608>; 872 status = "disabled"; 873 }; 874 875 vin14: video@e6efe000 { 876 compatible = "renesas,vin-r8a77980"; 877 reg = <0 0xe6efe000 0 0x1000>; 878 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>; 879 clocks = <&cpg CPG_MOD 605>; 880 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 881 resets = <&cpg 605>; 882 status = "disabled"; 883 }; 884 885 vin15: video@e6eff000 { 886 compatible = "renesas,vin-r8a77980"; 887 reg = <0 0xe6eff000 0 0x1000>; 888 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; 889 clocks = <&cpg CPG_MOD 604>; 890 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 891 resets = <&cpg 604>; 892 status = "disabled"; 893 }; 894 895 dmac1: dma-controller@e7300000 { 896 compatible = "renesas,dmac-r8a77980", 897 "renesas,rcar-dmac"; 898 reg = <0 0xe7300000 0 0x10000>; 899 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 900 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 901 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 902 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 903 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 904 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 905 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 906 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 907 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 908 GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 909 GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 910 GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 911 GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 912 GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 913 GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 914 GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 915 GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 916 interrupt-names = "error", 917 "ch0", "ch1", "ch2", "ch3", 918 "ch4", "ch5", "ch6", "ch7", 919 "ch8", "ch9", "ch10", "ch11", 920 "ch12", "ch13", "ch14", "ch15"; 921 clocks = <&cpg CPG_MOD 218>; 922 clock-names = "fck"; 923 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 924 resets = <&cpg 218>; 925 #dma-cells = <1>; 926 dma-channels = <16>; 927 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 928 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 929 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 930 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 931 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 932 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 933 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 934 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 935 }; 936 937 dmac2: dma-controller@e7310000 { 938 compatible = "renesas,dmac-r8a77980", 939 "renesas,rcar-dmac"; 940 reg = <0 0xe7310000 0 0x10000>; 941 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 942 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 943 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 944 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 945 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 946 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 947 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 948 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 949 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 950 GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 951 GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 952 GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 953 GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 954 GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 955 GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH 956 GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 957 GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 958 interrupt-names = "error", 959 "ch0", "ch1", "ch2", "ch3", 960 "ch4", "ch5", "ch6", "ch7", 961 "ch8", "ch9", "ch10", "ch11", 962 "ch12", "ch13", "ch14", "ch15"; 963 clocks = <&cpg CPG_MOD 217>; 964 clock-names = "fck"; 965 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 966 resets = <&cpg 217>; 967 #dma-cells = <1>; 968 dma-channels = <16>; 969 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 970 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 971 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 972 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 973 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 974 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 975 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 976 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 977 }; 978 979 gether: ethernet@e7400000 { 980 compatible = "renesas,gether-r8a77980"; 981 reg = <0 0xe7400000 0 0x1000>; 982 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 983 clocks = <&cpg CPG_MOD 813>; 984 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 985 resets = <&cpg 813>; 986 #address-cells = <1>; 987 #size-cells = <0>; 988 status = "disabled"; 989 }; 990 991 ipmmu_ds1: mmu@e7740000 { 992 compatible = "renesas,ipmmu-r8a77980"; 993 reg = <0 0xe7740000 0 0x1000>; 994 renesas,ipmmu-main = <&ipmmu_mm 0>; 995 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 996 #iommu-cells = <1>; 997 }; 998 999 ipmmu_ir: mmu@ff8b0000 { 1000 compatible = "renesas,ipmmu-r8a77980"; 1001 reg = <0 0xff8b0000 0 0x1000>; 1002 renesas,ipmmu-main = <&ipmmu_mm 3>; 1003 power-domains = <&sysc R8A77980_PD_A3IR>; 1004 #iommu-cells = <1>; 1005 }; 1006 1007 ipmmu_mm: mmu@e67b0000 { 1008 compatible = "renesas,ipmmu-r8a77980"; 1009 reg = <0 0xe67b0000 0 0x1000>; 1010 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1011 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1012 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1013 #iommu-cells = <1>; 1014 }; 1015 1016 ipmmu_rt: mmu@ffc80000 { 1017 compatible = "renesas,ipmmu-r8a77980"; 1018 reg = <0 0xffc80000 0 0x1000>; 1019 renesas,ipmmu-main = <&ipmmu_mm 10>; 1020 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1021 #iommu-cells = <1>; 1022 }; 1023 1024 ipmmu_vc0: mmu@fe6b0000 { 1025 compatible = "renesas,ipmmu-r8a77980"; 1026 reg = <0 0xfe6b0000 0 0x1000>; 1027 renesas,ipmmu-main = <&ipmmu_mm 12>; 1028 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1029 #iommu-cells = <1>; 1030 }; 1031 1032 ipmmu_vi0: mmu@febd0000 { 1033 compatible = "renesas,ipmmu-r8a77980"; 1034 reg = <0 0xfebd0000 0 0x1000>; 1035 renesas,ipmmu-main = <&ipmmu_mm 14>; 1036 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1037 #iommu-cells = <1>; 1038 }; 1039 1040 ipmmu_vip0: mmu@e7b00000 { 1041 compatible = "renesas,ipmmu-r8a77980"; 1042 reg = <0 0xe7b00000 0 0x1000>; 1043 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1044 #iommu-cells = <1>; 1045 }; 1046 1047 ipmmu_vip1: mmu@e7960000 { 1048 compatible = "renesas,ipmmu-r8a77980"; 1049 reg = <0 0xe7960000 0 0x1000>; 1050 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1051 #iommu-cells = <1>; 1052 }; 1053 1054 mmc0: mmc@ee140000 { 1055 compatible = "renesas,sdhi-r8a77980", 1056 "renesas,rcar-gen3-sdhi"; 1057 reg = <0 0xee140000 0 0x2000>; 1058 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1059 clocks = <&cpg CPG_MOD 314>; 1060 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1061 resets = <&cpg 314>; 1062 max-frequency = <200000000>; 1063 status = "disabled"; 1064 }; 1065 1066 gic: interrupt-controller@f1010000 { 1067 compatible = "arm,gic-400"; 1068 #interrupt-cells = <3>; 1069 #address-cells = <0>; 1070 interrupt-controller; 1071 reg = <0x0 0xf1010000 0 0x1000>, 1072 <0x0 0xf1020000 0 0x20000>, 1073 <0x0 0xf1040000 0 0x20000>, 1074 <0x0 0xf1060000 0 0x20000>; 1075 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 1076 IRQ_TYPE_LEVEL_HIGH)>; 1077 clocks = <&cpg CPG_MOD 408>; 1078 clock-names = "clk"; 1079 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1080 resets = <&cpg 408>; 1081 }; 1082 1083 pciec: pcie@fe000000 { 1084 compatible = "renesas,pcie-r8a77980", 1085 "renesas,pcie-rcar-gen3"; 1086 reg = <0 0xfe000000 0 0x80000>; 1087 #address-cells = <3>; 1088 #size-cells = <2>; 1089 bus-range = <0x00 0xff>; 1090 device_type = "pci"; 1091 ranges = < 1092 0x01000000 0 0x00000000 0 0xfe100000 0 0x0100000 1093 0x02000000 0 0xfe200000 0 0xfe200000 0 0x0200000 1094 0x02000000 0 0x30000000 0 0x30000000 0 0x8000000 1095 0x42000000 0 0x38000000 0 0x38000000 0 0x8000000 1096 >; 1097 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 1098 0 0x80000000>; 1099 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1102 #interrupt-cells = <1>; 1103 interrupt-map-mask = <0 0 0 0>; 1104 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 1105 IRQ_TYPE_LEVEL_HIGH>; 1106 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 1107 clock-names = "pcie", "pcie_bus"; 1108 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1109 resets = <&cpg 319>; 1110 phys = <&pcie_phy>; 1111 phy-names = "pcie"; 1112 status = "disabled"; 1113 }; 1114 1115 vspd0: vsp@fea20000 { 1116 compatible = "renesas,vsp2"; 1117 reg = <0 0xfea20000 0 0x5000>; 1118 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 1119 clocks = <&cpg CPG_MOD 623>; 1120 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1121 resets = <&cpg 623>; 1122 renesas,fcp = <&fcpvd0>; 1123 }; 1124 1125 fcpvd0: fcp@fea27000 { 1126 compatible = "renesas,fcpv"; 1127 reg = <0 0xfea27000 0 0x200>; 1128 clocks = <&cpg CPG_MOD 603>; 1129 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1130 resets = <&cpg 603>; 1131 }; 1132 1133 csi40: csi2@feaa0000 { 1134 compatible = "renesas,r8a77980-csi2"; 1135 reg = <0 0xfeaa0000 0 0x10000>; 1136 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1137 clocks = <&cpg CPG_MOD 716>; 1138 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1139 resets = <&cpg 716>; 1140 status = "disabled"; 1141 1142 ports { 1143 #address-cells = <1>; 1144 #size-cells = <0>; 1145 1146 port@1 { 1147 #address-cells = <1>; 1148 #size-cells = <0>; 1149 1150 reg = <1>; 1151 1152 csi40vin0: endpoint@0 { 1153 reg = <0>; 1154 remote-endpoint = <&vin0csi40>; 1155 }; 1156 csi40vin1: endpoint@1 { 1157 reg = <1>; 1158 remote-endpoint = <&vin1csi40>; 1159 }; 1160 csi40vin2: endpoint@2 { 1161 reg = <2>; 1162 remote-endpoint = <&vin2csi40>; 1163 }; 1164 csi40vin3: endpoint@3 { 1165 reg = <3>; 1166 remote-endpoint = <&vin3csi40>; 1167 }; 1168 }; 1169 }; 1170 }; 1171 1172 csi41: csi2@feab0000 { 1173 compatible = "renesas,r8a77980-csi2"; 1174 reg = <0 0xfeab0000 0 0x10000>; 1175 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1176 clocks = <&cpg CPG_MOD 715>; 1177 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1178 resets = <&cpg 715>; 1179 status = "disabled"; 1180 1181 ports { 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 1185 port@1 { 1186 #address-cells = <1>; 1187 #size-cells = <0>; 1188 1189 reg = <1>; 1190 1191 csi41vin4: endpoint@0 { 1192 reg = <0>; 1193 remote-endpoint = <&vin4csi41>; 1194 }; 1195 csi41vin5: endpoint@1 { 1196 reg = <1>; 1197 remote-endpoint = <&vin5csi41>; 1198 }; 1199 csi41vin6: endpoint@2 { 1200 reg = <2>; 1201 remote-endpoint = <&vin6csi41>; 1202 }; 1203 csi41vin7: endpoint@3 { 1204 reg = <3>; 1205 remote-endpoint = <&vin7csi41>; 1206 }; 1207 }; 1208 }; 1209 }; 1210 1211 du: display@feb00000 { 1212 compatible = "renesas,du-r8a77980", 1213 "renesas,du-r8a77970"; 1214 reg = <0 0xfeb00000 0 0x80000>; 1215 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1216 clocks = <&cpg CPG_MOD 724>; 1217 clock-names = "du.0"; 1218 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1219 resets = <&cpg 724>; 1220 vsps = <&vspd0>; 1221 status = "disabled"; 1222 1223 ports { 1224 #address-cells = <1>; 1225 #size-cells = <0>; 1226 1227 port@0 { 1228 reg = <0>; 1229 du_out_rgb: endpoint { 1230 }; 1231 }; 1232 1233 port@1 { 1234 reg = <1>; 1235 du_out_lvds0: endpoint { 1236 remote-endpoint = <&lvds0_in>; 1237 }; 1238 }; 1239 }; 1240 }; 1241 1242 lvds0: lvds-encoder@feb90000 { 1243 compatible = "renesas,r8a77980-lvds"; 1244 reg = <0 0xfeb90000 0 0x14>; 1245 clocks = <&cpg CPG_MOD 727>; 1246 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1247 resets = <&cpg 727>; 1248 status = "disabled"; 1249 1250 ports { 1251 #address-cells = <1>; 1252 #size-cells = <0>; 1253 1254 port@0 { 1255 reg = <0>; 1256 lvds0_in: endpoint { 1257 remote-endpoint = 1258 <&du_out_lvds0>; 1259 }; 1260 }; 1261 1262 port@1 { 1263 reg = <1>; 1264 lvds0_out: endpoint { 1265 }; 1266 }; 1267 }; 1268 }; 1269 1270 prr: chipid@fff00044 { 1271 compatible = "renesas,prr"; 1272 reg = <0 0xfff00044 0 4>; 1273 }; 1274 }; 1275 1276 timer { 1277 compatible = "arm,armv8-timer"; 1278 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 1279 IRQ_TYPE_LEVEL_LOW)>, 1280 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 1281 IRQ_TYPE_LEVEL_LOW)>, 1282 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 1283 IRQ_TYPE_LEVEL_LOW)>, 1284 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 1285 IRQ_TYPE_LEVEL_LOW)>; 1286 }; 1287}; 1288