1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a77980 SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 * Copyright (C) 2018 Cogent Embedded, Inc. 7 */ 8 9#include <dt-bindings/clock/r8a77980-cpg-mssr.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12 13/ { 14 compatible = "renesas,r8a77980"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 a53_0: cpu@0 { 23 device_type = "cpu"; 24 compatible = "arm,cortex-a53", "arm,armv8"; 25 reg = <0>; 26 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 27 power-domains = <&sysc 5>; 28 next-level-cache = <&L2_CA53>; 29 enable-method = "psci"; 30 }; 31 32 L2_CA53: cache-controller { 33 compatible = "cache"; 34 power-domains = <&sysc 21>; 35 cache-unified; 36 cache-level = <2>; 37 }; 38 }; 39 40 extal_clk: extal { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 /* This value must be overridden by the board */ 44 clock-frequency = <0>; 45 }; 46 47 extalr_clk: extalr { 48 compatible = "fixed-clock"; 49 #clock-cells = <0>; 50 /* This value must be overridden by the board */ 51 clock-frequency = <0>; 52 }; 53 54 psci { 55 compatible = "arm,psci-1.0", "arm,psci-0.2"; 56 method = "smc"; 57 }; 58 59 /* External SCIF clock - to be overridden by boards that provide it */ 60 scif_clk: scif { 61 compatible = "fixed-clock"; 62 #clock-cells = <0>; 63 clock-frequency = <0>; 64 }; 65 66 soc { 67 compatible = "simple-bus"; 68 interrupt-parent = <&gic>; 69 70 #address-cells = <2>; 71 #size-cells = <2>; 72 ranges; 73 74 pfc: pin-controller@e6060000 { 75 compatible = "renesas,pfc-r8a77980"; 76 reg = <0 0xe6060000 0 0x50c>; 77 }; 78 79 cpg: clock-controller@e6150000 { 80 compatible = "renesas,r8a77980-cpg-mssr"; 81 reg = <0 0xe6150000 0 0x1000>; 82 clocks = <&extal_clk>, <&extalr_clk>; 83 clock-names = "extal", "extalr"; 84 #clock-cells = <2>; 85 #power-domain-cells = <0>; 86 #reset-cells = <1>; 87 }; 88 89 rst: reset-controller@e6160000 { 90 compatible = "renesas,r8a77980-rst"; 91 reg = <0 0xe6160000 0 0x200>; 92 }; 93 94 sysc: system-controller@e6180000 { 95 compatible = "renesas,r8a77980-sysc"; 96 reg = <0 0xe6180000 0 0x440>; 97 #power-domain-cells = <1>; 98 }; 99 100 hscif0: serial@e6540000 { 101 compatible = "renesas,hscif-r8a77980", 102 "renesas,rcar-gen3-hscif", 103 "renesas,hscif"; 104 reg = <0 0xe6540000 0 0x60>; 105 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 106 clocks = <&cpg CPG_MOD 520>, 107 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 108 <&scif_clk>; 109 clock-names = "fck", "brg_int", "scif_clk"; 110 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 111 <&dmac2 0x31>, <&dmac2 0x30>; 112 dma-names = "tx", "rx", "tx", "rx"; 113 power-domains = <&sysc 32>; 114 resets = <&cpg 520>; 115 status = "disabled"; 116 }; 117 118 hscif1: serial@e6550000 { 119 compatible = "renesas,hscif-r8a77980", 120 "renesas,rcar-gen3-hscif", 121 "renesas,hscif"; 122 reg = <0 0xe6550000 0 0x60>; 123 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 124 clocks = <&cpg CPG_MOD 519>, 125 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 126 <&scif_clk>; 127 clock-names = "fck", "brg_int", "scif_clk"; 128 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 129 <&dmac2 0x33>, <&dmac2 0x32>; 130 dma-names = "tx", "rx", "tx", "rx"; 131 power-domains = <&sysc 32>; 132 resets = <&cpg 519>; 133 status = "disabled"; 134 }; 135 136 hscif2: serial@e6560000 { 137 compatible = "renesas,hscif-r8a77980", 138 "renesas,rcar-gen3-hscif", 139 "renesas,hscif"; 140 reg = <0 0xe6560000 0 0x60>; 141 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 142 clocks = <&cpg CPG_MOD 518>, 143 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 144 <&scif_clk>; 145 clock-names = "fck", "brg_int", "scif_clk"; 146 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 147 <&dmac2 0x35>, <&dmac2 0x34>; 148 dma-names = "tx", "rx", "tx", "rx"; 149 power-domains = <&sysc 32>; 150 resets = <&cpg 518>; 151 status = "disabled"; 152 }; 153 154 hscif3: serial@e66a0000 { 155 compatible = "renesas,hscif-r8a77980", 156 "renesas,rcar-gen3-hscif", 157 "renesas,hscif"; 158 reg = <0 0xe66a0000 0 0x60>; 159 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 160 clocks = <&cpg CPG_MOD 517>, 161 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 162 <&scif_clk>; 163 clock-names = "fck", "brg_int", "scif_clk"; 164 dmas = <&dmac1 0x37>, <&dmac1 0x36>, 165 <&dmac2 0x37>, <&dmac2 0x36>; 166 dma-names = "tx", "rx", "tx", "rx"; 167 power-domains = <&sysc 32>; 168 resets = <&cpg 517>; 169 status = "disabled"; 170 }; 171 172 avb: ethernet@e6800000 { 173 compatible = "renesas,etheravb-r8a77980", 174 "renesas,etheravb-rcar-gen3"; 175 reg = <0 0xe6800000 0 0x800>; 176 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 201 interrupt-names = "ch0", "ch1", "ch2", "ch3", 202 "ch4", "ch5", "ch6", "ch7", 203 "ch8", "ch9", "ch10", "ch11", 204 "ch12", "ch13", "ch14", "ch15", 205 "ch16", "ch17", "ch18", "ch19", 206 "ch20", "ch21", "ch22", "ch23", 207 "ch24"; 208 clocks = <&cpg CPG_MOD 812>; 209 power-domains = <&sysc 32>; 210 resets = <&cpg 812>; 211 phy-mode = "rgmii"; 212 #address-cells = <1>; 213 #size-cells = <0>; 214 }; 215 216 scif0: serial@e6e60000 { 217 compatible = "renesas,scif-r8a77980", 218 "renesas,rcar-gen3-scif", 219 "renesas,scif"; 220 reg = <0 0xe6e60000 0 0x40>; 221 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 222 clocks = <&cpg CPG_MOD 207>, 223 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 224 <&scif_clk>; 225 clock-names = "fck", "brg_int", "scif_clk"; 226 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 227 <&dmac2 0x51>, <&dmac2 0x50>; 228 dma-names = "tx", "rx", "tx", "rx"; 229 power-domains = <&sysc 32>; 230 resets = <&cpg 207>; 231 status = "disabled"; 232 }; 233 234 scif1: serial@e6e68000 { 235 compatible = "renesas,scif-r8a77980", 236 "renesas,rcar-gen3-scif", 237 "renesas,scif"; 238 reg = <0 0xe6e68000 0 0x40>; 239 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 240 clocks = <&cpg CPG_MOD 206>, 241 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 242 <&scif_clk>; 243 clock-names = "fck", "brg_int", "scif_clk"; 244 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 245 <&dmac2 0x53>, <&dmac2 0x52>; 246 dma-names = "tx", "rx", "tx", "rx"; 247 power-domains = <&sysc 32>; 248 resets = <&cpg 206>; 249 status = "disabled"; 250 }; 251 252 scif3: serial@e6c50000 { 253 compatible = "renesas,scif-r8a77980", 254 "renesas,rcar-gen3-scif", 255 "renesas,scif"; 256 reg = <0 0xe6c50000 0 0x40>; 257 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 258 clocks = <&cpg CPG_MOD 204>, 259 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 260 <&scif_clk>; 261 clock-names = "fck", "brg_int", "scif_clk"; 262 dmas = <&dmac1 0x57>, <&dmac1 0x56>, 263 <&dmac2 0x57>, <&dmac2 0x56>; 264 dma-names = "tx", "rx", "tx", "rx"; 265 power-domains = <&sysc 32>; 266 resets = <&cpg 204>; 267 status = "disabled"; 268 }; 269 270 scif4: serial@e6c40000 { 271 compatible = "renesas,scif-r8a77980", 272 "renesas,rcar-gen3-scif", 273 "renesas,scif"; 274 reg = <0 0xe6c40000 0 0x40>; 275 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 276 clocks = <&cpg CPG_MOD 203>, 277 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 278 <&scif_clk>; 279 clock-names = "fck", "brg_int", "scif_clk"; 280 dmas = <&dmac1 0x59>, <&dmac1 0x58>, 281 <&dmac2 0x59>, <&dmac2 0x58>; 282 dma-names = "tx", "rx", "tx", "rx"; 283 power-domains = <&sysc 32>; 284 resets = <&cpg 203>; 285 status = "disabled"; 286 }; 287 288 dmac1: dma-controller@e7300000 { 289 compatible = "renesas,dmac-r8a77980", 290 "renesas,rcar-dmac"; 291 reg = <0 0xe7300000 0 0x10000>; 292 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 293 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 294 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 295 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 296 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 297 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 298 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 299 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 300 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 301 GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 302 GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 303 GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 304 GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 305 GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 306 GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 307 GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 308 GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 309 interrupt-names = "error", 310 "ch0", "ch1", "ch2", "ch3", 311 "ch4", "ch5", "ch6", "ch7", 312 "ch8", "ch9", "ch10", "ch11", 313 "ch12", "ch13", "ch14", "ch15"; 314 clocks = <&cpg CPG_MOD 218>; 315 clock-names = "fck"; 316 power-domains = <&sysc 32>; 317 resets = <&cpg 218>; 318 #dma-cells = <1>; 319 dma-channels = <16>; 320 }; 321 322 dmac2: dma-controller@e7310000 { 323 compatible = "renesas,dmac-r8a77980", 324 "renesas,rcar-dmac"; 325 reg = <0 0xe7310000 0 0x10000>; 326 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 327 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 328 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 329 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 330 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 331 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 332 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 333 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 334 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 335 GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 336 GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 337 GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 338 GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 339 GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 340 GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH 341 GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 342 GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 343 interrupt-names = "error", 344 "ch0", "ch1", "ch2", "ch3", 345 "ch4", "ch5", "ch6", "ch7", 346 "ch8", "ch9", "ch10", "ch11", 347 "ch12", "ch13", "ch14", "ch15"; 348 clocks = <&cpg CPG_MOD 217>; 349 clock-names = "fck"; 350 power-domains = <&sysc 32>; 351 resets = <&cpg 217>; 352 #dma-cells = <1>; 353 dma-channels = <16>; 354 }; 355 356 mmc0: mmc@ee140000 { 357 compatible = "renesas,sdhi-r8a77980", 358 "renesas,rcar-gen3-sdhi"; 359 reg = <0 0xee140000 0 0x2000>; 360 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 361 clocks = <&cpg CPG_MOD 314>; 362 power-domains = <&sysc 32>; 363 resets = <&cpg 314>; 364 max-frequency = <200000000>; 365 status = "disabled"; 366 }; 367 368 gic: interrupt-controller@f1010000 { 369 compatible = "arm,gic-400"; 370 #interrupt-cells = <3>; 371 #address-cells = <0>; 372 interrupt-controller; 373 reg = <0x0 0xf1010000 0 0x1000>, 374 <0x0 0xf1020000 0 0x20000>, 375 <0x0 0xf1040000 0 0x20000>, 376 <0x0 0xf1060000 0 0x20000>; 377 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | 378 IRQ_TYPE_LEVEL_HIGH)>; 379 clocks = <&cpg CPG_MOD 408>; 380 clock-names = "clk"; 381 power-domains = <&sysc 32>; 382 resets = <&cpg 408>; 383 }; 384 385 prr: chipid@fff00044 { 386 compatible = "renesas,prr"; 387 reg = <0 0xfff00044 0 4>; 388 }; 389 }; 390 391 timer { 392 compatible = "arm,armv8-timer"; 393 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | 394 IRQ_TYPE_LEVEL_LOW)>, 395 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | 396 IRQ_TYPE_LEVEL_LOW)>, 397 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | 398 IRQ_TYPE_LEVEL_LOW)>, 399 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | 400 IRQ_TYPE_LEVEL_LOW)>; 401 }; 402}; 403