1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a77980 SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 * Copyright (C) 2018 Cogent Embedded, Inc. 7 */ 8 9#include <dt-bindings/clock/r8a77980-cpg-mssr.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/power/r8a77980-sysc.h> 13 14/ { 15 compatible = "renesas,r8a77980"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 i2c0 = &i2c0; 21 i2c1 = &i2c1; 22 i2c2 = &i2c2; 23 i2c3 = &i2c3; 24 i2c4 = &i2c4; 25 i2c5 = &i2c5; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 a53_0: cpu@0 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a53", "arm,armv8"; 35 reg = <0>; 36 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 37 power-domains = <&sysc R8A77980_PD_CA53_CPU0>; 38 next-level-cache = <&L2_CA53>; 39 enable-method = "psci"; 40 }; 41 42 a53_1: cpu@1 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a53", "arm,armv8"; 45 reg = <1>; 46 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 47 power-domains = <&sysc R8A77980_PD_CA53_CPU1>; 48 next-level-cache = <&L2_CA53>; 49 enable-method = "psci"; 50 }; 51 52 a53_2: cpu@2 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a53", "arm,armv8"; 55 reg = <2>; 56 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 57 power-domains = <&sysc R8A77980_PD_CA53_CPU2>; 58 next-level-cache = <&L2_CA53>; 59 enable-method = "psci"; 60 }; 61 62 a53_3: cpu@3 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a53", "arm,armv8"; 65 reg = <3>; 66 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 67 power-domains = <&sysc R8A77980_PD_CA53_CPU3>; 68 next-level-cache = <&L2_CA53>; 69 enable-method = "psci"; 70 }; 71 72 L2_CA53: cache-controller { 73 compatible = "cache"; 74 power-domains = <&sysc R8A77980_PD_CA53_SCU>; 75 cache-unified; 76 cache-level = <2>; 77 }; 78 }; 79 80 /* External CAN clock - to be overridden by boards that provide it */ 81 can_clk: can { 82 compatible = "fixed-clock"; 83 #clock-cells = <0>; 84 clock-frequency = <0>; 85 }; 86 87 extal_clk: extal { 88 compatible = "fixed-clock"; 89 #clock-cells = <0>; 90 /* This value must be overridden by the board */ 91 clock-frequency = <0>; 92 }; 93 94 extalr_clk: extalr { 95 compatible = "fixed-clock"; 96 #clock-cells = <0>; 97 /* This value must be overridden by the board */ 98 clock-frequency = <0>; 99 }; 100 101 psci { 102 compatible = "arm,psci-1.0", "arm,psci-0.2"; 103 method = "smc"; 104 }; 105 106 /* External SCIF clock - to be overridden by boards that provide it */ 107 scif_clk: scif { 108 compatible = "fixed-clock"; 109 #clock-cells = <0>; 110 clock-frequency = <0>; 111 }; 112 113 soc { 114 compatible = "simple-bus"; 115 interrupt-parent = <&gic>; 116 117 #address-cells = <2>; 118 #size-cells = <2>; 119 ranges; 120 121 pfc: pin-controller@e6060000 { 122 compatible = "renesas,pfc-r8a77980"; 123 reg = <0 0xe6060000 0 0x50c>; 124 }; 125 126 cpg: clock-controller@e6150000 { 127 compatible = "renesas,r8a77980-cpg-mssr"; 128 reg = <0 0xe6150000 0 0x1000>; 129 clocks = <&extal_clk>, <&extalr_clk>; 130 clock-names = "extal", "extalr"; 131 #clock-cells = <2>; 132 #power-domain-cells = <0>; 133 #reset-cells = <1>; 134 }; 135 136 rst: reset-controller@e6160000 { 137 compatible = "renesas,r8a77980-rst"; 138 reg = <0 0xe6160000 0 0x200>; 139 }; 140 141 sysc: system-controller@e6180000 { 142 compatible = "renesas,r8a77980-sysc"; 143 reg = <0 0xe6180000 0 0x440>; 144 #power-domain-cells = <1>; 145 }; 146 147 i2c0: i2c@e6500000 { 148 compatible = "renesas,i2c-r8a77980", 149 "renesas,rcar-gen3-i2c"; 150 reg = <0 0xe6500000 0 0x40>; 151 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 152 clocks = <&cpg CPG_MOD 931>; 153 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 154 resets = <&cpg 931>; 155 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 156 <&dmac2 0x91>, <&dmac2 0x90>; 157 dma-names = "tx", "rx", "tx", "rx"; 158 i2c-scl-internal-delay-ns = <6>; 159 #address-cells = <1>; 160 #size-cells = <0>; 161 status = "disabled"; 162 }; 163 164 i2c1: i2c@e6508000 { 165 compatible = "renesas,i2c-r8a77980", 166 "renesas,rcar-gen3-i2c"; 167 reg = <0 0xe6508000 0 0x40>; 168 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 169 clocks = <&cpg CPG_MOD 930>; 170 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 171 resets = <&cpg 930>; 172 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 173 <&dmac2 0x93>, <&dmac2 0x92>; 174 dma-names = "tx", "rx", "tx", "rx"; 175 i2c-scl-internal-delay-ns = <6>; 176 #address-cells = <1>; 177 #size-cells = <0>; 178 status = "disabled"; 179 }; 180 181 i2c2: i2c@e6510000 { 182 compatible = "renesas,i2c-r8a77980", 183 "renesas,rcar-gen3-i2c"; 184 reg = <0 0xe6510000 0 0x40>; 185 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 186 clocks = <&cpg CPG_MOD 929>; 187 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 188 resets = <&cpg 929>; 189 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 190 <&dmac2 0x95>, <&dmac2 0x94>; 191 dma-names = "tx", "rx", "tx", "rx"; 192 i2c-scl-internal-delay-ns = <6>; 193 #address-cells = <1>; 194 #size-cells = <0>; 195 status = "disabled"; 196 }; 197 198 i2c3: i2c@e66d0000 { 199 compatible = "renesas,i2c-r8a77980", 200 "renesas,rcar-gen3-i2c"; 201 reg = <0 0xe66d0000 0 0x40>; 202 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 203 clocks = <&cpg CPG_MOD 928>; 204 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 205 resets = <&cpg 928>; 206 i2c-scl-internal-delay-ns = <6>; 207 #address-cells = <1>; 208 #size-cells = <0>; 209 status = "disabled"; 210 }; 211 212 i2c4: i2c@e66d8000 { 213 compatible = "renesas,i2c-r8a77980", 214 "renesas,rcar-gen3-i2c"; 215 reg = <0 0xe66d8000 0 0x40>; 216 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 217 clocks = <&cpg CPG_MOD 927>; 218 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 219 resets = <&cpg 927>; 220 i2c-scl-internal-delay-ns = <6>; 221 #address-cells = <1>; 222 #size-cells = <0>; 223 status = "disabled"; 224 }; 225 226 i2c5: i2c@e66e0000 { 227 compatible = "renesas,i2c-r8a77980", 228 "renesas,rcar-gen3-i2c"; 229 reg = <0 0xe66e0000 0 0x40>; 230 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 231 clocks = <&cpg CPG_MOD 919>; 232 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 233 resets = <&cpg 919>; 234 dmas = <&dmac1 0x9b>, <&dmac1 0x9a>, 235 <&dmac2 0x9b>, <&dmac2 0x9a>; 236 dma-names = "tx", "rx", "tx", "rx"; 237 i2c-scl-internal-delay-ns = <6>; 238 #address-cells = <1>; 239 #size-cells = <0>; 240 status = "disabled"; 241 }; 242 243 hscif0: serial@e6540000 { 244 compatible = "renesas,hscif-r8a77980", 245 "renesas,rcar-gen3-hscif", 246 "renesas,hscif"; 247 reg = <0 0xe6540000 0 0x60>; 248 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 249 clocks = <&cpg CPG_MOD 520>, 250 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 251 <&scif_clk>; 252 clock-names = "fck", "brg_int", "scif_clk"; 253 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 254 <&dmac2 0x31>, <&dmac2 0x30>; 255 dma-names = "tx", "rx", "tx", "rx"; 256 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 257 resets = <&cpg 520>; 258 status = "disabled"; 259 }; 260 261 hscif1: serial@e6550000 { 262 compatible = "renesas,hscif-r8a77980", 263 "renesas,rcar-gen3-hscif", 264 "renesas,hscif"; 265 reg = <0 0xe6550000 0 0x60>; 266 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&cpg CPG_MOD 519>, 268 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 269 <&scif_clk>; 270 clock-names = "fck", "brg_int", "scif_clk"; 271 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 272 <&dmac2 0x33>, <&dmac2 0x32>; 273 dma-names = "tx", "rx", "tx", "rx"; 274 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 275 resets = <&cpg 519>; 276 status = "disabled"; 277 }; 278 279 hscif2: serial@e6560000 { 280 compatible = "renesas,hscif-r8a77980", 281 "renesas,rcar-gen3-hscif", 282 "renesas,hscif"; 283 reg = <0 0xe6560000 0 0x60>; 284 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 285 clocks = <&cpg CPG_MOD 518>, 286 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 287 <&scif_clk>; 288 clock-names = "fck", "brg_int", "scif_clk"; 289 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 290 <&dmac2 0x35>, <&dmac2 0x34>; 291 dma-names = "tx", "rx", "tx", "rx"; 292 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 293 resets = <&cpg 518>; 294 status = "disabled"; 295 }; 296 297 hscif3: serial@e66a0000 { 298 compatible = "renesas,hscif-r8a77980", 299 "renesas,rcar-gen3-hscif", 300 "renesas,hscif"; 301 reg = <0 0xe66a0000 0 0x60>; 302 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 303 clocks = <&cpg CPG_MOD 517>, 304 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 305 <&scif_clk>; 306 clock-names = "fck", "brg_int", "scif_clk"; 307 dmas = <&dmac1 0x37>, <&dmac1 0x36>, 308 <&dmac2 0x37>, <&dmac2 0x36>; 309 dma-names = "tx", "rx", "tx", "rx"; 310 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 311 resets = <&cpg 517>; 312 status = "disabled"; 313 }; 314 315 canfd: can@e66c0000 { 316 compatible = "renesas,r8a77980-canfd", 317 "renesas,rcar-gen3-canfd"; 318 reg = <0 0xe66c0000 0 0x8000>; 319 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&cpg CPG_MOD 914>, 322 <&cpg CPG_CORE R8A77980_CLK_CANFD>, 323 <&can_clk>; 324 clock-names = "fck", "canfd", "can_clk"; 325 assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>; 326 assigned-clock-rates = <40000000>; 327 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 328 resets = <&cpg 914>; 329 status = "disabled"; 330 331 channel0 { 332 status = "disabled"; 333 }; 334 335 channel1 { 336 status = "disabled"; 337 }; 338 }; 339 340 avb: ethernet@e6800000 { 341 compatible = "renesas,etheravb-r8a77980", 342 "renesas,etheravb-rcar-gen3"; 343 reg = <0 0xe6800000 0 0x800>; 344 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 346 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 347 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 348 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 349 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 350 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 351 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 352 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 353 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 354 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 365 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 366 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 367 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 368 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 369 interrupt-names = "ch0", "ch1", "ch2", "ch3", 370 "ch4", "ch5", "ch6", "ch7", 371 "ch8", "ch9", "ch10", "ch11", 372 "ch12", "ch13", "ch14", "ch15", 373 "ch16", "ch17", "ch18", "ch19", 374 "ch20", "ch21", "ch22", "ch23", 375 "ch24"; 376 clocks = <&cpg CPG_MOD 812>; 377 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 378 resets = <&cpg 812>; 379 phy-mode = "rgmii"; 380 #address-cells = <1>; 381 #size-cells = <0>; 382 status = "disabled"; 383 }; 384 385 scif0: serial@e6e60000 { 386 compatible = "renesas,scif-r8a77980", 387 "renesas,rcar-gen3-scif", 388 "renesas,scif"; 389 reg = <0 0xe6e60000 0 0x40>; 390 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 391 clocks = <&cpg CPG_MOD 207>, 392 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 393 <&scif_clk>; 394 clock-names = "fck", "brg_int", "scif_clk"; 395 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 396 <&dmac2 0x51>, <&dmac2 0x50>; 397 dma-names = "tx", "rx", "tx", "rx"; 398 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 399 resets = <&cpg 207>; 400 status = "disabled"; 401 }; 402 403 scif1: serial@e6e68000 { 404 compatible = "renesas,scif-r8a77980", 405 "renesas,rcar-gen3-scif", 406 "renesas,scif"; 407 reg = <0 0xe6e68000 0 0x40>; 408 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 409 clocks = <&cpg CPG_MOD 206>, 410 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 411 <&scif_clk>; 412 clock-names = "fck", "brg_int", "scif_clk"; 413 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 414 <&dmac2 0x53>, <&dmac2 0x52>; 415 dma-names = "tx", "rx", "tx", "rx"; 416 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 417 resets = <&cpg 206>; 418 status = "disabled"; 419 }; 420 421 scif3: serial@e6c50000 { 422 compatible = "renesas,scif-r8a77980", 423 "renesas,rcar-gen3-scif", 424 "renesas,scif"; 425 reg = <0 0xe6c50000 0 0x40>; 426 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 427 clocks = <&cpg CPG_MOD 204>, 428 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 429 <&scif_clk>; 430 clock-names = "fck", "brg_int", "scif_clk"; 431 dmas = <&dmac1 0x57>, <&dmac1 0x56>, 432 <&dmac2 0x57>, <&dmac2 0x56>; 433 dma-names = "tx", "rx", "tx", "rx"; 434 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 435 resets = <&cpg 204>; 436 status = "disabled"; 437 }; 438 439 scif4: serial@e6c40000 { 440 compatible = "renesas,scif-r8a77980", 441 "renesas,rcar-gen3-scif", 442 "renesas,scif"; 443 reg = <0 0xe6c40000 0 0x40>; 444 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 445 clocks = <&cpg CPG_MOD 203>, 446 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 447 <&scif_clk>; 448 clock-names = "fck", "brg_int", "scif_clk"; 449 dmas = <&dmac1 0x59>, <&dmac1 0x58>, 450 <&dmac2 0x59>, <&dmac2 0x58>; 451 dma-names = "tx", "rx", "tx", "rx"; 452 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 453 resets = <&cpg 203>; 454 status = "disabled"; 455 }; 456 457 dmac1: dma-controller@e7300000 { 458 compatible = "renesas,dmac-r8a77980", 459 "renesas,rcar-dmac"; 460 reg = <0 0xe7300000 0 0x10000>; 461 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 462 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 463 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 464 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 465 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 466 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 467 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 468 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 469 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 470 GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 471 GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 472 GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 473 GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 474 GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 475 GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 476 GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 477 GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 478 interrupt-names = "error", 479 "ch0", "ch1", "ch2", "ch3", 480 "ch4", "ch5", "ch6", "ch7", 481 "ch8", "ch9", "ch10", "ch11", 482 "ch12", "ch13", "ch14", "ch15"; 483 clocks = <&cpg CPG_MOD 218>; 484 clock-names = "fck"; 485 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 486 resets = <&cpg 218>; 487 #dma-cells = <1>; 488 dma-channels = <16>; 489 }; 490 491 dmac2: dma-controller@e7310000 { 492 compatible = "renesas,dmac-r8a77980", 493 "renesas,rcar-dmac"; 494 reg = <0 0xe7310000 0 0x10000>; 495 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 496 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 497 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 498 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 499 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 500 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 501 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 502 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 503 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 504 GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 505 GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 506 GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 507 GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 508 GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 509 GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH 510 GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 511 GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 512 interrupt-names = "error", 513 "ch0", "ch1", "ch2", "ch3", 514 "ch4", "ch5", "ch6", "ch7", 515 "ch8", "ch9", "ch10", "ch11", 516 "ch12", "ch13", "ch14", "ch15"; 517 clocks = <&cpg CPG_MOD 217>; 518 clock-names = "fck"; 519 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 520 resets = <&cpg 217>; 521 #dma-cells = <1>; 522 dma-channels = <16>; 523 }; 524 525 gether: ethernet@e7400000 { 526 compatible = "renesas,gether-r8a77980"; 527 reg = <0 0xe7400000 0 0x1000>; 528 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 529 clocks = <&cpg CPG_MOD 813>; 530 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 531 resets = <&cpg 813>; 532 #address-cells = <1>; 533 #size-cells = <0>; 534 status = "disabled"; 535 }; 536 537 mmc0: mmc@ee140000 { 538 compatible = "renesas,sdhi-r8a77980", 539 "renesas,rcar-gen3-sdhi"; 540 reg = <0 0xee140000 0 0x2000>; 541 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&cpg CPG_MOD 314>; 543 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 544 resets = <&cpg 314>; 545 max-frequency = <200000000>; 546 status = "disabled"; 547 }; 548 549 gic: interrupt-controller@f1010000 { 550 compatible = "arm,gic-400"; 551 #interrupt-cells = <3>; 552 #address-cells = <0>; 553 interrupt-controller; 554 reg = <0x0 0xf1010000 0 0x1000>, 555 <0x0 0xf1020000 0 0x20000>, 556 <0x0 0xf1040000 0 0x20000>, 557 <0x0 0xf1060000 0 0x20000>; 558 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 559 IRQ_TYPE_LEVEL_HIGH)>; 560 clocks = <&cpg CPG_MOD 408>; 561 clock-names = "clk"; 562 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 563 resets = <&cpg 408>; 564 }; 565 566 prr: chipid@fff00044 { 567 compatible = "renesas,prr"; 568 reg = <0 0xfff00044 0 4>; 569 }; 570 }; 571 572 timer { 573 compatible = "arm,armv8-timer"; 574 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 575 IRQ_TYPE_LEVEL_LOW)>, 576 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 577 IRQ_TYPE_LEVEL_LOW)>, 578 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 579 IRQ_TYPE_LEVEL_LOW)>, 580 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 581 IRQ_TYPE_LEVEL_LOW)>; 582 }; 583}; 584